Lines Matching +full:power +full:- +full:reg
1 // SPDX-License-Identifier: GPL-2.0+
7 /dts-v1/;
8 #include <dt-bindings/clock/mediatek,mt8188-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/mailbox/mediatek,mt8188-gce.h>
12 #include <dt-bindings/memory/mediatek,mt8188-memory-port.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
15 #include <dt-bindings/power/mediatek,mt8188-power.h>
16 #include <dt-bindings/reset/mt8188-resets.h>
17 #include <dt-bindings/thermal/thermal.h>
18 #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
27 dp-intf0 = &dp_intf0;
28 dp-intf1 = &dp_intf1;
49 vdo1-rdma0 = &vdo1_rdma0;
50 vdo1-rdma1 = &vdo1_rdma1;
51 vdo1-rdma2 = &vdo1_rdma2;
52 vdo1-rdma3 = &vdo1_rdma3;
53 vdo1-rdma4 = &vdo1_rdma4;
54 vdo1-rdma5 = &vdo1_rdma5;
55 vdo1-rdma6 = &vdo1_rdma6;
56 vdo1-rdma7 = &vdo1_rdma7;
60 #address-cells = <1>;
61 #size-cells = <0>;
65 compatible = "arm,cortex-a55";
66 reg = <0x000>;
67 enable-method = "psci";
68 clock-frequency = <2000000000>;
69 capacity-dmips-mhz = <282>;
70 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
71 i-cache-size = <32768>;
72 i-cache-line-size = <64>;
73 i-cache-sets = <128>;
74 d-cache-size = <32768>;
75 d-cache-line-size = <64>;
76 d-cache-sets = <128>;
77 next-level-cache = <&l2_0>;
78 performance-domains = <&performance 0>;
79 #cooling-cells = <2>;
84 compatible = "arm,cortex-a55";
85 reg = <0x100>;
86 enable-method = "psci";
87 clock-frequency = <2000000000>;
88 capacity-dmips-mhz = <282>;
89 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
90 i-cache-size = <32768>;
91 i-cache-line-size = <64>;
92 i-cache-sets = <128>;
93 d-cache-size = <32768>;
94 d-cache-line-size = <64>;
95 d-cache-sets = <128>;
96 next-level-cache = <&l2_0>;
97 performance-domains = <&performance 0>;
98 #cooling-cells = <2>;
103 compatible = "arm,cortex-a55";
104 reg = <0x200>;
105 enable-method = "psci";
106 clock-frequency = <2000000000>;
107 capacity-dmips-mhz = <282>;
108 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
109 i-cache-size = <32768>;
110 i-cache-line-size = <64>;
111 i-cache-sets = <128>;
112 d-cache-size = <32768>;
113 d-cache-line-size = <64>;
114 d-cache-sets = <128>;
115 next-level-cache = <&l2_0>;
116 performance-domains = <&performance 0>;
117 #cooling-cells = <2>;
122 compatible = "arm,cortex-a55";
123 reg = <0x300>;
124 enable-method = "psci";
125 clock-frequency = <2000000000>;
126 capacity-dmips-mhz = <282>;
127 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
128 i-cache-size = <32768>;
129 i-cache-line-size = <64>;
130 i-cache-sets = <128>;
131 d-cache-size = <32768>;
132 d-cache-line-size = <64>;
133 d-cache-sets = <128>;
134 next-level-cache = <&l2_0>;
135 performance-domains = <&performance 0>;
136 #cooling-cells = <2>;
141 compatible = "arm,cortex-a55";
142 reg = <0x400>;
143 enable-method = "psci";
144 clock-frequency = <2000000000>;
145 capacity-dmips-mhz = <282>;
146 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
147 i-cache-size = <32768>;
148 i-cache-line-size = <64>;
149 i-cache-sets = <128>;
150 d-cache-size = <32768>;
151 d-cache-line-size = <64>;
152 d-cache-sets = <128>;
153 next-level-cache = <&l2_0>;
154 performance-domains = <&performance 0>;
155 #cooling-cells = <2>;
160 compatible = "arm,cortex-a55";
161 reg = <0x500>;
162 enable-method = "psci";
163 clock-frequency = <2000000000>;
164 capacity-dmips-mhz = <282>;
165 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
166 i-cache-size = <32768>;
167 i-cache-line-size = <64>;
168 i-cache-sets = <128>;
169 d-cache-size = <32768>;
170 d-cache-line-size = <64>;
171 d-cache-sets = <128>;
172 next-level-cache = <&l2_0>;
173 performance-domains = <&performance 0>;
174 #cooling-cells = <2>;
179 compatible = "arm,cortex-a78";
180 reg = <0x600>;
181 enable-method = "psci";
182 clock-frequency = <2600000000>;
183 capacity-dmips-mhz = <1024>;
184 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
185 i-cache-size = <65536>;
186 i-cache-line-size = <64>;
187 i-cache-sets = <256>;
188 d-cache-size = <65536>;
189 d-cache-line-size = <64>;
190 d-cache-sets = <256>;
191 next-level-cache = <&l2_1>;
192 performance-domains = <&performance 1>;
193 #cooling-cells = <2>;
198 compatible = "arm,cortex-a78";
199 reg = <0x700>;
200 enable-method = "psci";
201 clock-frequency = <2600000000>;
202 capacity-dmips-mhz = <1024>;
203 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
204 i-cache-size = <65536>;
205 i-cache-line-size = <64>;
206 i-cache-sets = <256>;
207 d-cache-size = <65536>;
208 d-cache-line-size = <64>;
209 d-cache-sets = <256>;
210 next-level-cache = <&l2_1>;
211 performance-domains = <&performance 1>;
212 #cooling-cells = <2>;
215 cpu-map {
251 idle-states {
252 entry-method = "psci";
254 cpu_off_l: cpu-off-l {
255 compatible = "arm,idle-state";
256 arm,psci-suspend-param = <0x00010000>;
257 local-timer-stop;
258 entry-latency-us = <50>;
259 exit-latency-us = <95>;
260 min-residency-us = <580>;
263 cpu_off_b: cpu-off-b {
264 compatible = "arm,idle-state";
265 arm,psci-suspend-param = <0x00010000>;
266 local-timer-stop;
267 entry-latency-us = <45>;
268 exit-latency-us = <140>;
269 min-residency-us = <740>;
272 cluster_off_l: cluster-off-l {
273 compatible = "arm,idle-state";
274 arm,psci-suspend-param = <0x01010010>;
275 local-timer-stop;
276 entry-latency-us = <55>;
277 exit-latency-us = <155>;
278 min-residency-us = <840>;
281 cluster_off_b: cluster-off-b {
282 compatible = "arm,idle-state";
283 arm,psci-suspend-param = <0x01010010>;
284 local-timer-stop;
285 entry-latency-us = <50>;
286 exit-latency-us = <200>;
287 min-residency-us = <1000>;
291 l2_0: l2-cache0 {
293 cache-level = <2>;
294 cache-size = <131072>;
295 cache-line-size = <64>;
296 cache-sets = <512>;
297 next-level-cache = <&l3_0>;
298 cache-unified;
301 l2_1: l2-cache1 {
303 cache-level = <2>;
304 cache-size = <262144>;
305 cache-line-size = <64>;
306 cache-sets = <512>;
307 next-level-cache = <&l3_0>;
308 cache-unified;
311 l3_0: l3-cache {
313 cache-level = <3>;
314 cache-size = <2097152>;
315 cache-line-size = <64>;
316 cache-sets = <2048>;
317 cache-unified;
321 clk13m: oscillator-13m {
322 compatible = "fixed-clock";
323 #clock-cells = <0>;
324 clock-frequency = <13000000>;
325 clock-output-names = "clk13m";
328 clk26m: oscillator-26m {
329 compatible = "fixed-clock";
330 #clock-cells = <0>;
331 clock-frequency = <26000000>;
332 clock-output-names = "clk26m";
335 clk32k: oscillator-32k {
336 compatible = "fixed-clock";
337 #clock-cells = <0>;
338 clock-frequency = <32768>;
339 clock-output-names = "clk32k";
342 gpu_opp_table: opp-table-gpu {
343 compatible = "operating-points-v2";
344 opp-shared;
346 opp-390000000 {
347 opp-hz = /bits/ 64 <390000000>;
348 opp-microvolt = <575000>;
349 opp-supported-hw = <0xff>;
351 opp-431000000 {
352 opp-hz = /bits/ 64 <431000000>;
353 opp-microvolt = <587500>;
354 opp-supported-hw = <0xff>;
356 opp-473000000 {
357 opp-hz = /bits/ 64 <473000000>;
358 opp-microvolt = <600000>;
359 opp-supported-hw = <0xff>;
361 opp-515000000 {
362 opp-hz = /bits/ 64 <515000000>;
363 opp-microvolt = <612500>;
364 opp-supported-hw = <0xff>;
366 opp-556000000 {
367 opp-hz = /bits/ 64 <556000000>;
368 opp-microvolt = <625000>;
369 opp-supported-hw = <0xff>;
371 opp-598000000 {
372 opp-hz = /bits/ 64 <598000000>;
373 opp-microvolt = <637500>;
374 opp-supported-hw = <0xff>;
376 opp-640000000 {
377 opp-hz = /bits/ 64 <640000000>;
378 opp-microvolt = <650000>;
379 opp-supported-hw = <0xff>;
381 opp-670000000 {
382 opp-hz = /bits/ 64 <670000000>;
383 opp-microvolt = <662500>;
384 opp-supported-hw = <0xff>;
386 opp-700000000 {
387 opp-hz = /bits/ 64 <700000000>;
388 opp-microvolt = <675000>;
389 opp-supported-hw = <0xff>;
391 opp-730000000 {
392 opp-hz = /bits/ 64 <730000000>;
393 opp-microvolt = <687500>;
394 opp-supported-hw = <0xff>;
396 opp-760000000 {
397 opp-hz = /bits/ 64 <760000000>;
398 opp-microvolt = <700000>;
399 opp-supported-hw = <0xff>;
401 opp-790000000 {
402 opp-hz = /bits/ 64 <790000000>;
403 opp-microvolt = <712500>;
404 opp-supported-hw = <0xff>;
406 opp-835000000 {
407 opp-hz = /bits/ 64 <835000000>;
408 opp-microvolt = <731250>;
409 opp-supported-hw = <0xff>;
411 opp-880000000 {
412 opp-hz = /bits/ 64 <880000000>;
413 opp-microvolt = <750000>;
414 opp-supported-hw = <0xff>;
416 opp-915000000 {
417 opp-hz = /bits/ 64 <915000000>;
418 opp-microvolt = <775000>;
419 opp-supported-hw = <0x8f>;
421 opp-915000000-5 {
422 opp-hz = /bits/ 64 <915000000>;
423 opp-microvolt = <762500>;
424 opp-supported-hw = <0x30>;
426 opp-915000000-6 {
427 opp-hz = /bits/ 64 <915000000>;
428 opp-microvolt = <750000>;
429 opp-supported-hw = <0x70>;
431 opp-950000000 {
432 opp-hz = /bits/ 64 <950000000>;
433 opp-microvolt = <800000>;
434 opp-supported-hw = <0x8f>;
436 opp-950000000-5 {
437 opp-hz = /bits/ 64 <950000000>;
438 opp-microvolt = <775000>;
439 opp-supported-hw = <0x30>;
441 opp-950000000-6 {
442 opp-hz = /bits/ 64 <950000000>;
443 opp-microvolt = <750000>;
444 opp-supported-hw = <0x70>;
448 pmu-a55 {
449 compatible = "arm,cortex-a55-pmu";
450 interrupt-parent = <&gic>;
454 pmu-a78 {
455 compatible = "arm,cortex-a78-pmu";
456 interrupt-parent = <&gic>;
461 compatible = "arm,psci-1.0";
470 thermal_zones: thermal-zones {
471 cpu-little0-thermal {
472 polling-delay = <1000>;
473 polling-delay-passive = <150>;
474 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU0>;
477 cpu_little0_alert0: trip-alert0 {
483 cpu_little0_alert1: trip-alert1 {
489 cpu_little0_crit: trip-crit {
496 cooling-maps {
499 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
509 cpu-little1-thermal {
510 polling-delay = <1000>;
511 polling-delay-passive = <150>;
512 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU1>;
515 cpu_little1_alert0: trip-alert0 {
521 cpu_little1_alert1: trip-alert1 {
527 cpu_little1_crit: trip-crit {
534 cooling-maps {
537 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
547 cpu-little2-thermal {
548 polling-delay = <1000>;
549 polling-delay-passive = <150>;
550 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU2>;
553 cpu_little2_alert0: trip-alert0 {
559 cpu_little2_alert1: trip-alert1 {
565 cpu_little2_crit: trip-crit {
572 cooling-maps {
575 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
585 cpu-little3-thermal {
586 polling-delay = <1000>;
587 polling-delay-passive = <150>;
588 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU3>;
591 cpu_little3_alert0: trip-alert0 {
597 cpu_little3_alert1: trip-alert1 {
603 cpu_little3_crit: trip-crit {
610 cooling-maps {
613 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
623 cpu-big0-thermal {
624 polling-delay = <1000>;
625 polling-delay-passive = <100>;
626 thermal-sensors = <&lvts_mcu MT8188_MCU_BIG_CPU0>;
629 cpu_big0_alert0: trip-alert0 {
635 cpu_big0_alert1: trip-alert1 {
641 cpu_big0_crit: trip-crit {
648 cooling-maps {
651 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
657 cpu-big1-thermal {
658 polling-delay = <1000>;
659 polling-delay-passive = <100>;
660 thermal-sensors = <&lvts_mcu MT8188_MCU_BIG_CPU1>;
663 cpu_big1_alert0: trip-alert0 {
669 cpu_big1_alert1: trip-alert1 {
675 cpu_big1_crit: trip-crit {
682 cooling-maps {
685 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
691 apu-thermal {
692 polling-delay = <1000>;
693 polling-delay-passive = <250>;
694 thermal-sensors = <&lvts_ap MT8188_AP_APU>;
697 apu_alert0: trip-alert0 {
703 apu_alert1: trip-alert1 {
709 apu_crit: trip-crit {
717 gpu-thermal {
718 polling-delay = <1000>;
719 polling-delay-passive = <250>;
720 thermal-sensors = <&lvts_ap MT8188_AP_GPU0>;
723 gpu_alert0: trip-alert0 {
729 gpu_alert1: trip-alert1 {
735 gpu_crit: trip-crit {
742 cooling-maps {
745 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
750 gpu1-thermal {
751 polling-delay = <1000>;
752 polling-delay-passive = <250>;
753 thermal-sensors = <&lvts_ap MT8188_AP_GPU1>;
756 gpu1_alert0: trip-alert0 {
762 gpu1_alert1: trip-alert1 {
768 gpu1_crit: trip-crit {
775 cooling-maps {
778 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
783 adsp-thermal {
784 polling-delay = <1000>;
785 polling-delay-passive = <250>;
786 thermal-sensors = <&lvts_ap MT8188_AP_ADSP>;
789 soc_alert0: trip-alert0 {
795 soc_alert1: trip-alert1 {
801 soc_crit: trip-crit {
809 vdo-thermal {
810 polling-delay = <1000>;
811 polling-delay-passive = <250>;
812 thermal-sensors = <&lvts_ap MT8188_AP_VDO>;
815 soc1_alert0: trip-alert0 {
821 soc1_alert1: trip-alert1 {
827 soc1_crit: trip-crit {
835 infra-thermal {
836 polling-delay = <1000>;
837 polling-delay-passive = <250>;
838 thermal-sensors = <&lvts_ap MT8188_AP_INFRA>;
841 soc2_alert0: trip-alert0 {
847 soc2_alert1: trip-alert1 {
853 soc2_crit: trip-crit {
861 cam1-thermal {
862 polling-delay = <1000>;
863 polling-delay-passive = <250>;
864 thermal-sensors = <&lvts_ap MT8188_AP_CAM1>;
867 cam1_alert0: trip-alert0 {
873 cam1_alert1: trip-alert1 {
879 cam1_crit: trip-crit {
887 cam2-thermal {
888 polling-delay = <1000>;
889 polling-delay-passive = <250>;
890 thermal-sensors = <&lvts_ap MT8188_AP_CAM2>;
893 cam2_alert0: trip-alert0 {
899 cam2_alert1: trip-alert1 {
905 cam2_crit: trip-crit {
915 compatible = "arm,armv8-timer";
916 interrupt-parent = <&gic>;
921 clock-frequency = <13000000>;
925 #address-cells = <2>;
926 #size-cells = <2>;
927 compatible = "simple-bus";
928 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
931 performance: performance-controller@11bc10 {
932 compatible = "mediatek,cpufreq-hw";
933 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
934 #performance-domain-cells = <1>;
937 gic: interrupt-controller@c000000 {
938 compatible = "arm,gic-v3";
939 #interrupt-cells = <4>;
940 #redistributor-regions = <1>;
941 interrupt-parent = <&gic>;
942 interrupt-controller;
943 reg = <0 0x0c000000 0 0x40000>,
947 ppi-partitions {
948 ppi_cluster0: interrupt-partition-0 {
952 ppi_cluster1: interrupt-partition-1 {
959 compatible = "mediatek,mt8188-topckgen", "syscon";
960 reg = <0 0x10000000 0 0x1000>;
961 #clock-cells = <1>;
965 compatible = "mediatek,mt8188-infracfg-ao", "syscon";
966 reg = <0 0x10001000 0 0x1000>;
967 #clock-cells = <1>;
968 #reset-cells = <1>;
972 compatible = "mediatek,mt8188-pericfg", "syscon";
973 reg = <0 0x10003000 0 0x1000>;
974 #clock-cells = <1>;
978 compatible = "mediatek,mt8188-pinctrl";
979 reg = <0 0x10005000 0 0x1000>,
985 reg-names = "iocfg0", "iocfg_rm", "iocfg_lt",
987 gpio-controller;
988 #gpio-cells = <2>;
989 gpio-ranges = <&pio 0 0 176>;
990 interrupt-controller;
992 #interrupt-cells = <2>;
996 compatible = "mediatek,mt8188-scpsys", "syscon", "simple-mfd";
997 reg = <0 0x10006000 0 0x1000>;
999 /* System Power Manager */
1000 spm: power-controller {
1001 compatible = "mediatek,mt8188-power-controller";
1002 #address-cells = <1>;
1003 #size-cells = <0>;
1004 #power-domain-cells = <1>;
1006 /* power domain of the SoC */
1007 mfg0: power-domain@MT8188_POWER_DOMAIN_MFG0 {
1008 reg = <MT8188_POWER_DOMAIN_MFG0>;
1009 #address-cells = <1>;
1010 #size-cells = <0>;
1011 #power-domain-cells = <1>;
1013 mfg1: power-domain@MT8188_POWER_DOMAIN_MFG1 {
1014 reg = <MT8188_POWER_DOMAIN_MFG1>;
1017 clock-names = "mfg", "alt";
1019 #address-cells = <1>;
1020 #size-cells = <0>;
1021 #power-domain-cells = <1>;
1023 power-domain@MT8188_POWER_DOMAIN_MFG2 {
1024 reg = <MT8188_POWER_DOMAIN_MFG2>;
1025 #power-domain-cells = <0>;
1028 power-domain@MT8188_POWER_DOMAIN_MFG3 {
1029 reg = <MT8188_POWER_DOMAIN_MFG3>;
1030 #power-domain-cells = <0>;
1033 power-domain@MT8188_POWER_DOMAIN_MFG4 {
1034 reg = <MT8188_POWER_DOMAIN_MFG4>;
1035 #power-domain-cells = <0>;
1040 power-domain@MT8188_POWER_DOMAIN_VPPSYS0 {
1041 reg = <MT8188_POWER_DOMAIN_VPPSYS0>;
1070 clock-names = "top", "cam", "ccu", "img", "venc",
1072 "ss-sram-cmn", "ss-sram-v0l0", "ss-sram-v0l1",
1073 "ss-sram-ve0", "ss-sram-ve1", "ss-sram-ifa",
1074 "ss-sram-cam", "ss-sram-v1l5", "ss-sram-v1l6",
1075 "ss-sram-rdr", "ss-iommu", "ss-imgcam",
1076 "ss-emi", "ss-subcmn-rdr", "ss-rsi",
1077 "ss-cmn-l4", "ss-vdec1", "ss-wpe",
1078 "ss-cvdo-ve1";
1080 #address-cells = <1>;
1081 #size-cells = <0>;
1082 #power-domain-cells = <1>;
1084 power-domain@MT8188_POWER_DOMAIN_VDOSYS0 {
1085 reg = <MT8188_POWER_DOMAIN_VDOSYS0>;
1095 clock-names = "cfgck", "cfgxo", "ss-gals",
1096 "ss-cmn", "ss-emi", "ss-iommu",
1097 "ss-larb", "ss-rsi", "ss-bus";
1099 #address-cells = <1>;
1100 #size-cells = <0>;
1101 #power-domain-cells = <1>;
1103 power-domain@MT8188_POWER_DOMAIN_VPPSYS1 {
1104 reg = <MT8188_POWER_DOMAIN_VPPSYS1>;
1111 clock-names = "cfgck", "cfgxo",
1112 "ss-vpp1-g5", "ss-vpp1-g6",
1113 "ss-vpp1-l5", "ss-vpp1-l6";
1115 #power-domain-cells = <0>;
1118 power-domain@MT8188_POWER_DOMAIN_VDEC0 {
1119 reg = <MT8188_POWER_DOMAIN_VDEC0>;
1121 clock-names = "ss-vdec1-soc-l1";
1123 #address-cells = <1>;
1124 #size-cells = <0>;
1125 #power-domain-cells = <1>;
1127 power-domain@MT8188_POWER_DOMAIN_VDEC1 {
1128 reg = <MT8188_POWER_DOMAIN_VDEC1>;
1130 clock-names = "ss-vdec2-l1";
1132 #power-domain-cells = <0>;
1136 cam_vcore: power-domain@MT8188_POWER_DOMAIN_CAM_VCORE {
1137 reg = <MT8188_POWER_DOMAIN_CAM_VCORE>;
1142 clock-names = "cam", "ccu", "bus", "cfgck";
1144 #address-cells = <1>;
1145 #size-cells = <0>;
1146 #power-domain-cells = <1>;
1148 power-domain@MT8188_POWER_DOMAIN_CAM_MAIN {
1149 reg = <MT8188_POWER_DOMAIN_CAM_MAIN>;
1155 clock-names= "ss-cam-l13", "ss-cam-l14",
1156 "ss-cam-mm0", "ss-cam-mm1",
1157 "ss-camsys";
1159 #address-cells = <1>;
1160 #size-cells = <0>;
1161 #power-domain-cells = <1>;
1163 power-domain@MT8188_POWER_DOMAIN_CAM_SUBB {
1164 reg = <MT8188_POWER_DOMAIN_CAM_SUBB>;
1168 clock-names = "ss-camb-sub",
1169 "ss-camb-raw",
1170 "ss-camb-yuv";
1171 #power-domain-cells = <0>;
1174 power-domain@MT8188_POWER_DOMAIN_CAM_SUBA {
1175 reg =<MT8188_POWER_DOMAIN_CAM_SUBA>;
1179 clock-names = "ss-cama-sub",
1180 "ss-cama-raw",
1181 "ss-cama-yuv";
1182 #power-domain-cells = <0>;
1187 power-domain@MT8188_POWER_DOMAIN_VDOSYS1 {
1188 reg = <MT8188_POWER_DOMAIN_VDOSYS1>;
1194 clock-names = "cfgck", "cfgxo", "ss-larb2",
1195 "ss-larb3", "ss-gals";
1197 #address-cells = <1>;
1198 #size-cells = <0>;
1199 #power-domain-cells = <1>;
1201 power-domain@MT8188_POWER_DOMAIN_HDMI_TX {
1202 reg = <MT8188_POWER_DOMAIN_HDMI_TX>;
1205 clock-names = "bus", "hdcp";
1207 #power-domain-cells = <0>;
1210 power-domain@MT8188_POWER_DOMAIN_DP_TX {
1211 reg = <MT8188_POWER_DOMAIN_DP_TX>;
1213 #power-domain-cells = <0>;
1216 power-domain@MT8188_POWER_DOMAIN_EDP_TX {
1217 reg = <MT8188_POWER_DOMAIN_EDP_TX>;
1219 #power-domain-cells = <0>;
1223 power-domain@MT8188_POWER_DOMAIN_VENC {
1224 reg = <MT8188_POWER_DOMAIN_VENC>;
1229 clock-names = "ss-ve1-larb", "ss-ve1-core",
1230 "ss-ve1-gals", "ss-ve1-sram";
1232 #power-domain-cells = <0>;
1235 power-domain@MT8188_POWER_DOMAIN_WPE {
1236 reg = <MT8188_POWER_DOMAIN_WPE>;
1239 clock-names = "ss-wpe-l7", "ss-wpe-l7pce";
1241 #power-domain-cells = <0>;
1246 power-domain@MT8188_POWER_DOMAIN_PEXTP_MAC_P0 {
1247 reg = <MT8188_POWER_DOMAIN_PEXTP_MAC_P0>;
1250 clock-names = "ss-pextp-fmem";
1251 #power-domain-cells = <0>;
1254 power-domain@MT8188_POWER_DOMAIN_CSIRX_TOP {
1255 reg = <MT8188_POWER_DOMAIN_CSIRX_TOP>;
1258 clock-names = "seninf0", "seninf1";
1259 #power-domain-cells = <0>;
1262 power-domain@MT8188_POWER_DOMAIN_PEXTP_PHY_TOP {
1263 reg = <MT8188_POWER_DOMAIN_PEXTP_PHY_TOP>;
1264 #power-domain-cells = <0>;
1267 power-domain@MT8188_POWER_DOMAIN_ADSP_AO {
1268 reg = <MT8188_POWER_DOMAIN_ADSP_AO>;
1271 clock-names = "bus", "main";
1273 #address-cells = <1>;
1274 #size-cells = <0>;
1275 #power-domain-cells = <1>;
1277 power-domain@MT8188_POWER_DOMAIN_ADSP_INFRA {
1278 reg = <MT8188_POWER_DOMAIN_ADSP_INFRA>;
1280 #address-cells = <1>;
1281 #size-cells = <0>;
1282 #power-domain-cells = <1>;
1284 power-domain@MT8188_POWER_DOMAIN_AUDIO_ASRC {
1285 reg = <MT8188_POWER_DOMAIN_AUDIO_ASRC>;
1287 clock-names = "asm";
1289 #power-domain-cells = <0>;
1292 power-domain@MT8188_POWER_DOMAIN_AUDIO {
1293 reg = <MT8188_POWER_DOMAIN_AUDIO>;
1297 clock-names = "a1sys", "intbus", "adspck";
1299 #power-domain-cells = <0>;
1302 power-domain@MT8188_POWER_DOMAIN_ADSP {
1303 reg = <MT8188_POWER_DOMAIN_ADSP>;
1305 #power-domain-cells = <0>;
1310 power-domain@MT8188_POWER_DOMAIN_ETHER {
1311 reg = <MT8188_POWER_DOMAIN_ETHER>;
1313 clock-names = "ethermac";
1315 #power-domain-cells = <0>;
1321 compatible = "mediatek,mt8188-wdt";
1322 reg = <0 0x10007000 0 0x100>;
1323 mediatek,disable-extrst;
1324 #reset-cells = <1>;
1328 compatible = "mediatek,mt8188-apmixedsys", "syscon";
1329 reg = <0 0x1000c000 0 0x1000>;
1330 #clock-cells = <1>;
1334 compatible = "mediatek,mt8188-timer", "mediatek,mt6765-timer";
1335 reg = <0 0x10017000 0 0x1000>;
1341 compatible = "mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap", "syscon";
1342 reg = <0 0x10024000 0 0x1000>;
1343 reg-names = "pwrap";
1347 clock-names = "spi", "wrap";
1351 compatible = "mediatek,mt8188-spmi", "mediatek,mt8195-spmi";
1352 reg = <0 0x10027000 0 0xe00>, <0 0x10029000 0 0x100>;
1353 reg-names = "pmif", "spmimst";
1354 assigned-clocks = <&topckgen CLK_TOP_SPMI_M_MST>;
1355 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
1359 clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux";
1363 compatible = "mediatek,mt8188-iommu-infra";
1364 reg = <0 0x10315000 0 0x1000>;
1366 #iommu-cells = <1>;
1370 compatible = "mediatek,mt8188-gce";
1371 reg = <0 0x10320000 0 0x4000>;
1373 #mbox-cells = <2>;
1378 compatible = "mediatek,mt8188-gce";
1379 reg = <0 0x10330000 0 0x4000>;
1381 #mbox-cells = <2>;
1386 compatible = "mediatek,mt8188-scp-dual";
1387 reg = <0 0x10720000 0 0xe0000>;
1388 reg-names = "cfg";
1389 #address-cells = <1>;
1390 #size-cells = <1>;
1395 compatible = "mediatek,scp-core";
1396 reg = <0x0 0xd0000>;
1397 reg-names = "sram";
1403 compatible = "mediatek,scp-core";
1404 reg = <0xd0000 0x2f000>;
1405 reg-names = "sram";
1411 afe: audio-controller@10b10000 {
1412 compatible = "mediatek,mt8188-afe";
1413 reg = <0 0x10b10000 0 0x10000>;
1414 assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP>;
1415 assigned-clock-parents = <&topckgen CLK_TOP_APLL1_D4>;
1439 clock-names = "clk26m",
1463 power-domains = <&spm MT8188_POWER_DOMAIN_AUDIO>;
1465 reset-names = "audiosys";
1472 compatible = "mediatek,mt8188-dsp";
1473 reg = <0 0x10b80000 0 0x2000>,
1477 reg-names = "cfg", "sram", "sec", "bus";
1478 assigned-clocks = <&topckgen CLK_TOP_ADSP>;
1481 clock-names = "audiodsp", "adsp_bus";
1483 mbox-names = "rx", "tx";
1484 power-domains = <&spm MT8188_POWER_DOMAIN_ADSP>;
1489 compatible = "mediatek,mt8188-adsp-mbox", "mediatek,mt8186-adsp-mbox";
1490 reg = <0 0x10b86100 0 0x1000>;
1492 #mbox-cells = <0>;
1496 compatible = "mediatek,mt8188-adsp-mbox", "mediatek,mt8186-adsp-mbox";
1497 reg = <0 0x10b87100 0 0x1000>;
1499 #mbox-cells = <0>;
1502 adsp_audio26m: clock-controller@10b91100 {
1503 compatible = "mediatek,mt8188-adsp-audio26m";
1504 reg = <0 0x10b91100 0 0x100>;
1505 #clock-cells = <1>;
1509 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
1510 reg = <0 0x11001100 0 0x100>;
1513 clock-names = "baud", "bus";
1518 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
1519 reg = <0 0x11001200 0 0x100>;
1522 clock-names = "baud", "bus";
1527 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
1528 reg = <0 0x11001300 0 0x100>;
1531 clock-names = "baud", "bus";
1536 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
1537 reg = <0 0x11001400 0 0x100>;
1540 clock-names = "baud", "bus";
1545 compatible = "mediatek,mt8188-auxadc", "mediatek,mt8173-auxadc";
1546 reg = <0 0x11002000 0 0x1000>;
1548 clock-names = "main";
1549 #io-channel-cells = <1>;
1554 compatible = "mediatek,mt8188-pericfg-ao", "syscon";
1555 reg = <0 0x11003000 0 0x1000>;
1556 #clock-cells = <1>;
1560 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1561 #address-cells = <1>;
1562 #size-cells = <0>;
1563 reg = <0 0x1100a000 0 0x1000>;
1568 clock-names = "parent-clk", "sel-clk", "spi-clk";
1572 lvts_ap: thermal-sensor@1100b000 {
1573 compatible = "mediatek,mt8188-lvts-ap";
1574 reg = <0 0x1100b000 0 0xc00>;
1578 nvmem-cells = <&lvts_efuse_data1>;
1579 nvmem-cell-names = "lvts-calib-data-1";
1580 #thermal-sensor-cells = <1>;
1584 compatible = "mediatek,mt8188-disp-pwm", "mediatek,mt8183-disp-pwm";
1585 reg = <0 0x1100e000 0 0x1000>;
1588 clock-names = "main", "mm";
1590 #pwm-cells = <2>;
1595 compatible = "mediatek,mt8188-disp-pwm", "mediatek,mt8183-disp-pwm";
1596 reg = <0 0x1100f000 0 0x1000>;
1599 clock-names = "main", "mm";
1601 #pwm-cells = <2>;
1606 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1607 #address-cells = <1>;
1608 #size-cells = <0>;
1609 reg = <0 0x11010000 0 0x1000>;
1614 clock-names = "parent-clk", "sel-clk", "spi-clk";
1619 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1620 #address-cells = <1>;
1621 #size-cells = <0>;
1622 reg = <0 0x11012000 0 0x1000>;
1627 clock-names = "parent-clk", "sel-clk", "spi-clk";
1632 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1633 #address-cells = <1>;
1634 #size-cells = <0>;
1635 reg = <0 0x11013000 0 0x1000>;
1640 clock-names = "parent-clk", "sel-clk", "spi-clk";
1645 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1646 #address-cells = <1>;
1647 #size-cells = <0>;
1648 reg = <0 0x11018000 0 0x1000>;
1653 clock-names = "parent-clk", "sel-clk", "spi-clk";
1658 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1659 #address-cells = <1>;
1660 #size-cells = <0>;
1661 reg = <0 0x11019000 0 0x1000>;
1666 clock-names = "parent-clk", "sel-clk", "spi-clk";
1671 compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3";
1672 reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>;
1673 reg-names = "mac", "ippc";
1675 #address-cells = <2>;
1676 #size-cells = <2>;
1678 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>;
1679 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1683 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1685 wakeup-source;
1686 mediatek,syscon-wakeup = <&pericfg 0x468 2>;
1690 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
1691 reg = <0 0 0 0x1000>;
1692 reg-names = "mac";
1694 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI>;
1695 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1697 clock-names = "sys_ck";
1703 compatible = "mediatek,mt8188-gmac", "mediatek,mt8195-gmac",
1704 "snps,dwmac-5.10a";
1705 reg = <0 0x11021000 0 0x4000>;
1707 interrupt-names = "macirq";
1714 clock-names = "axi", "apb", "mac_main", "ptp_ref",
1716 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
1719 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
1722 power-domains = <&spm MT8188_POWER_DOMAIN_ETHER>;
1724 snps,axi-config = <&stmmac_axi_setup>;
1725 snps,mtl-rx-config = <&mtl_rx_setup>;
1726 snps,mtl-tx-config = <&mtl_tx_setup>;
1729 snps,clk-csr = <0>;
1733 compatible = "snps,dwmac-mdio";
1734 #address-cells = <1>;
1735 #size-cells = <0>;
1738 stmmac_axi_setup: stmmac-axi-config {
1744 mtl_rx_setup: rx-queues-config {
1745 snps,rx-queues-to-use = <4>;
1746 snps,rx-sched-sp;
1749 snps,dcb-algorithm;
1750 snps,map-to-dma-channel = <0x0>;
1754 snps,dcb-algorithm;
1755 snps,map-to-dma-channel = <0x0>;
1759 snps,dcb-algorithm;
1760 snps,map-to-dma-channel = <0x0>;
1764 snps,dcb-algorithm;
1765 snps,map-to-dma-channel = <0x0>;
1769 mtl_tx_setup: tx-queues-config {
1770 snps,tx-queues-to-use = <4>;
1771 snps,tx-sched-wrr;
1774 snps,dcb-algorithm;
1780 snps,dcb-algorithm;
1786 snps,dcb-algorithm;
1792 snps,dcb-algorithm;
1800 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
1801 reg = <0 0x11230000 0 0x10000>,
1808 clock-names = "source", "hclk", "source_cg", "crypto_clk";
1813 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
1814 reg = <0 0x11240000 0 0x1000>,
1820 clock-names = "source", "hclk", "source_cg";
1821 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1822 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1827 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
1828 reg = <0 0x11250000 0 0x1000>,
1834 clock-names = "source", "hclk", "source_cg";
1835 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
1836 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1840 lvts_mcu: thermal-sensor@11278000 {
1841 compatible = "mediatek,mt8188-lvts-mcu";
1842 reg = <0 0x11278000 0 0x1000>;
1846 nvmem-cells = <&lvts_efuse_data1>;
1847 nvmem-cell-names = "lvts-calib-data-1";
1848 #thermal-sensor-cells = <1>;
1852 compatible = "mediatek,mt8188-i2c";
1853 reg = <0 0x11280000 0 0x1000>,
1856 clock-div = <1>;
1859 clock-names = "main", "dma";
1860 #address-cells = <1>;
1861 #size-cells = <0>;
1866 compatible = "mediatek,mt8188-i2c";
1867 reg = <0 0x11281000 0 0x1000>,
1870 clock-div = <1>;
1873 clock-names = "main", "dma";
1874 #address-cells = <1>;
1875 #size-cells = <0>;
1880 compatible = "mediatek,mt8188-i2c";
1881 reg = <0 0x11282000 0 0x1000>,
1884 clock-div = <1>;
1887 clock-names = "main", "dma";
1888 #address-cells = <1>;
1889 #size-cells = <0>;
1893 imp_iic_wrap_c: clock-controller@11283000 {
1894 compatible = "mediatek,mt8188-imp-iic-wrap-c";
1895 reg = <0 0x11283000 0 0x1000>;
1896 #clock-cells = <1>;
1900 compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3";
1901 reg = <0 0x112a1000 0 0x2dff>, <0 0x112a3e00 0 0x0100>;
1902 reg-names = "mac", "ippc";
1904 #address-cells = <2>;
1905 #size-cells = <2>;
1907 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>;
1908 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1912 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1914 wakeup-source;
1915 mediatek,syscon-wakeup = <&pericfg 0x470 2>;
1919 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
1920 reg = <0 0 0 0x1000>;
1921 reg-names = "mac";
1923 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
1924 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1926 clock-names = "sys_ck";
1932 compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3";
1933 reg = <0 0x112b1000 0 0x2dff>, <0 0x112b3e00 0 0x0100>;
1934 reg-names = "mac", "ippc";
1936 #address-cells = <2>;
1937 #size-cells = <2>;
1939 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
1940 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1944 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1946 wakeup-source;
1947 mediatek,syscon-wakeup = <&pericfg 0x460 2>;
1951 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
1952 reg = <0 0 0 0x1000>;
1953 reg-names = "mac";
1955 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>;
1956 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1958 clock-names = "sys_ck";
1964 compatible = "mediatek,mt8188-pcie", "mediatek,mt8192-pcie";
1965 reg = <0 0x112f0000 0 0x2000>;
1966 reg-names = "pcie-mac";
1968 bus-range = <0 0xff>;
1970 linux,pci-domain = <0>;
1971 #address-cells = <3>;
1972 #size-cells = <2>;
1980 clock-names = "pl_250m", "tl_26m", "tl_96m", "tl_32k",
1983 #interrupt-cells = <1>;
1985 interrupt-map = <0 0 0 1 &pcie_intc 0>,
1989 interrupt-map-mask = <0 0 0 7>;
1991 iommu-map = <0 &infra_iommu IFR_IOMMU_PORT_PCIE_0 0xffff>;
1992 iommu-map-mask = <0>;
1995 phy-names = "pcie-phy";
1997 power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_MAC_P0>;
2000 reset-names = "mac";
2004 pcie_intc: interrupt-controller {
2005 #address-cells = <0>;
2006 #interrupt-cells = <1>;
2007 interrupt-controller;
2012 compatible = "mediatek,mt8188-nor", "mediatek,mt8186-nor";
2013 reg = <0 0x1132c000 0 0x1000>;
2017 clock-names = "spi", "sf", "axi";
2018 assigned-clocks = <&topckgen CLK_TOP_SPINOR>;
2020 #address-cells = <1>;
2021 #size-cells = <0>;
2025 pciephy: t-phy@11c20700 {
2026 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
2028 #address-cells = <1>;
2029 #size-cells = <1>;
2030 power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_PHY_TOP>;
2033 pcieport: pcie-phy@0 {
2034 reg = <0 0x700>;
2036 clock-names = "ref";
2037 #phy-cells = <1>;
2041 mipi_tx_config0: dsi-phy@11c80000 {
2042 compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx";
2043 reg = <0 0x11c80000 0 0x1000>;
2045 clock-output-names = "mipi_tx0_pll";
2046 #clock-cells = <0>;
2047 #phy-cells = <0>;
2051 mipi_tx_config1: dsi-phy@11c90000 {
2052 compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx";
2053 reg = <0 0x11c90000 0 0x1000>;
2055 clock-output-names = "mipi_tx0_pll";
2056 #clock-cells = <0>;
2057 #phy-cells = <0>;
2062 compatible = "mediatek,mt8188-i2c";
2063 reg = <0 0x11e00000 0 0x1000>,
2066 clock-div = <1>;
2069 clock-names = "main", "dma";
2070 #address-cells = <1>;
2071 #size-cells = <0>;
2076 compatible = "mediatek,mt8188-i2c";
2077 reg = <0 0x11e01000 0 0x1000>,
2080 clock-div = <1>;
2083 clock-names = "main", "dma";
2084 #address-cells = <1>;
2085 #size-cells = <0>;
2089 imp_iic_wrap_w: clock-controller@11e02000 {
2090 compatible = "mediatek,mt8188-imp-iic-wrap-w";
2091 reg = <0 0x11e02000 0 0x1000>;
2092 #clock-cells = <1>;
2095 u3phy0: t-phy@11e30000 {
2096 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
2097 #address-cells = <1>;
2098 #size-cells = <1>;
2102 u2port0: usb-phy@0 {
2103 reg = <0x0 0x700>;
2106 clock-names = "ref", "da_ref";
2107 #phy-cells = <1>;
2111 u3phy1: t-phy@11e40000 {
2112 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
2113 #address-cells = <1>;
2114 #size-cells = <1>;
2118 u2port1: usb-phy@0 {
2119 reg = <0x0 0x700>;
2122 clock-names = "ref", "da_ref";
2123 #phy-cells = <1>;
2126 u3port1: usb-phy@700 {
2127 reg = <0x700 0x700>;
2130 clock-names = "ref", "da_ref";
2131 #phy-cells = <1>;
2135 u3phy2: t-phy@11e80000 {
2136 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
2137 #address-cells = <1>;
2138 #size-cells = <1>;
2142 u2port2: usb-phy@0 {
2143 reg = <0x0 0x700>;
2146 clock-names = "ref", "da_ref";
2147 #phy-cells = <1>;
2152 compatible = "mediatek,mt8188-i2c";
2153 reg = <0 0x11ec0000 0 0x1000>,
2156 clock-div = <1>;
2159 clock-names = "main", "dma";
2160 #address-cells = <1>;
2161 #size-cells = <0>;
2166 compatible = "mediatek,mt8188-i2c";
2167 reg = <0 0x11ec1000 0 0x1000>,
2170 clock-div = <1>;
2173 clock-names = "main", "dma";
2174 #address-cells = <1>;
2175 #size-cells = <0>;
2179 imp_iic_wrap_en: clock-controller@11ec2000 {
2180 compatible = "mediatek,mt8188-imp-iic-wrap-en";
2181 reg = <0 0x11ec2000 0 0x1000>;
2182 #clock-cells = <1>;
2186 compatible = "mediatek,mt8188-efuse", "mediatek,efuse";
2187 reg = <0 0x11f20000 0 0x1000>;
2188 #address-cells = <1>;
2189 #size-cells = <1>;
2191 dp_calib_data: dp-calib@1a0 {
2192 reg = <0x1a0 0xc>;
2195 lvts_efuse_data1: lvts1-calib@1ac {
2196 reg = <0x1ac 0x40>;
2199 gpu_speedbin: gpu-speedbin@581 {
2200 reg = <0x581 0x1>;
2204 socinfo-data1@7a0 {
2205 reg = <0x7a0 0x4>;
2208 socinfo-data2@7e0 {
2209 reg = <0x7e0 0x4>;
2214 compatible = "mediatek,mt8188-mali", "arm,mali-valhall-jm";
2215 reg = <0 0x13000000 0 0x4000>;
2221 interrupt-names = "job", "mmu", "gpu";
2222 nvmem-cells = <&gpu_speedbin>;
2223 nvmem-cell-names = "speed-bin";
2224 operating-points-v2 = <&gpu_opp_table>;
2225 power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>,
2228 power-domain-names = "core0", "core1", "core2";
2229 #cooling-cells = <2>;
2233 mfgcfg: clock-controller@13fbf000 {
2234 compatible = "mediatek,mt8188-mfgcfg";
2235 reg = <0 0x13fbf000 0 0x1000>;
2236 #clock-cells = <1>;
2240 compatible = "mediatek,mt8188-vppsys0", "syscon";
2241 reg = <0 0x14000000 0 0x1000>;
2242 #clock-cells = <1>;
2245 dma-controller@14001000 {
2246 compatible = "mediatek,mt8188-mdp3-rdma";
2247 reg = <0 0x14001000 0 0x1000>;
2248 #dma-cells = <1>;
2256 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
2257 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
2258 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
2264 compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg";
2265 reg = <0 0x14002000 0 0x1000>;
2267 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
2271 compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr";
2272 reg = <0 0x14004000 0 0x1000>;
2274 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
2278 compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal";
2279 reg = <0 0x14005000 0 0x1000>;
2282 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
2283 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>;
2287 compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2288 reg = <0 0x14006000 0 0x1000>;
2290 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>;
2291 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>,
2296 compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp";
2297 reg = <0 0x14007000 0 0x1000>;
2299 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
2303 compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color";
2304 reg = <0 0x14008000 0 0x1000>;
2307 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
2308 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>;
2312 compatible = "mediatek,mt8188-mdp3-ovl", "mediatek,mt8195-mdp3-ovl";
2313 reg = <0 0x14009000 0 0x1000>;
2316 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
2317 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>;
2322 compatible = "mediatek,mt8188-mdp3-padding", "mediatek,mt8195-mdp3-padding";
2323 reg = <0 0x1400a000 0 0x1000>;
2325 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
2326 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>;
2330 compatible = "mediatek,mt8188-mdp3-tcc", "mediatek,mt8195-mdp3-tcc";
2331 reg = <0 0x1400b000 0 0x1000>;
2333 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
2337 compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2338 reg = <0 0x1400c000 0 0x1000>;
2339 #dma-cells = <1>;
2342 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
2343 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>;
2344 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>,
2349 compatible = "mediatek,mt8188-vpp-mutex";
2350 reg = <0 0x1400f000 0 0x1000>;
2353 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
2354 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>;
2358 compatible = "mediatek,mt8188-smi-common-vpp";
2359 reg = <0 0x14012000 0 0x1000>;
2362 clock-names = "apb", "smi";
2363 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
2367 compatible = "mediatek,mt8188-smi-larb";
2368 reg = <0 0x14013000 0 0x1000>;
2371 clock-names = "apb", "smi";
2372 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
2373 mediatek,larb-id = <SMI_L4_ID>;
2378 compatible = "mediatek,mt8188-iommu-vpp";
2379 reg = <0 0x14018000 0 0x5000>;
2381 clock-names = "bclk";
2383 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
2384 #iommu-cells = <1>;
2388 dma-controller@14f09000 {
2389 compatible = "mediatek,mt8188-mdp3-rdma";
2390 reg = <0 0x14f09000 0 0x1000>;
2391 #dma-cells = <1>;
2394 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
2395 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>;
2396 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>,
2400 dma-controller@14f0a000 {
2401 compatible = "mediatek,mt8188-mdp3-rdma";
2402 reg = <0 0x14f0a000 0 0x1000>;
2403 #dma-cells = <1>;
2406 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
2407 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>;
2408 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>,
2413 compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg";
2414 reg = <0 0x14f0c000 0 0x1000>;
2416 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>;
2420 compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg";
2421 reg = <0 0x14f0d000 0 0x1000>;
2423 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>;
2427 compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr";
2428 reg = <0 0x14f0f000 0 0x1000>;
2430 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>;
2434 compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr";
2435 reg = <0 0x14f10000 0 0x1000>;
2437 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>;
2441 compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal";
2442 reg = <0 0x14f12000 0 0x1000>;
2445 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
2446 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>;
2450 compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal";
2451 reg = <0 0x14f13000 0 0x1000>;
2454 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
2455 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>;
2459 compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2460 reg = <0 0x14f15000 0 0x1000>;
2462 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>;
2463 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>,
2468 compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2469 reg = <0 0x14f16000 0 0x1000>;
2471 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>;
2472 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>,
2477 compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp";
2478 reg = <0 0x14f18000 0 0x1000>;
2480 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>;
2484 compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp";
2485 reg = <0 0x14f19000 0 0x1000>;
2487 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>;
2491 compatible = "mediatek,mt8188-mdp3-merge", "mediatek,mt8195-mdp3-merge";
2492 reg = <0 0x14f1a000 0 0x1000>;
2494 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
2495 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>;
2499 compatible = "mediatek,mt8188-mdp3-merge", "mediatek,mt8195-mdp3-merge";
2500 reg = <0 0x14f1b000 0 0x1000>;
2502 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
2503 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>;
2507 compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color";
2508 reg = <0 0x14f1d000 0 0x1000>;
2511 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
2512 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>;
2516 compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color";
2517 reg = <0 0x14f1e000 0 0x1000>;
2520 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
2521 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>;
2525 compatible = "mediatek,mt8188-mdp3-padding",
2526 "mediatek,mt8195-mdp3-padding";
2527 reg = <0 0x14f21000 0 0x1000>;
2529 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
2530 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>;
2534 compatible = "mediatek,mt8188-mdp3-padding",
2535 "mediatek,mt8195-mdp3-padding";
2536 reg = <0 0x14f22000 0 0x1000>;
2538 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
2539 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>;
2543 compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2544 reg = <0 0x14f24000 0 0x1000>;
2545 #dma-cells = <1>;
2548 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
2549 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>;
2550 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>,
2555 compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2556 reg = <0 0x14f25000 0 0x1000>;
2557 #dma-cells = <1>;
2560 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
2561 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>;
2562 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>,
2566 wpesys: clock-controller@14e00000 {
2567 compatible = "mediatek,mt8188-wpesys";
2568 reg = <0 0x14e00000 0 0x1000>;
2569 #clock-cells = <1>;
2572 wpesys_vpp0: clock-controller@14e02000 {
2573 compatible = "mediatek,mt8188-wpesys-vpp0";
2574 reg = <0 0x14e02000 0 0x1000>;
2575 #clock-cells = <1>;
2579 compatible = "mediatek,mt8188-smi-larb";
2580 reg = <0 0x14e04000 0 0x1000>;
2583 clock-names = "apb", "smi";
2584 power-domains = <&spm MT8188_POWER_DOMAIN_WPE>;
2585 mediatek,larb-id = <SMI_L7_ID>;
2590 compatible = "mediatek,mt8188-vppsys1", "syscon";
2591 reg = <0 0x14f00000 0 0x1000>;
2592 #clock-cells = <1>;
2596 compatible = "mediatek,mt8188-vpp-mutex";
2597 reg = <0 0x14f01000 0 0x1000>;
2600 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
2601 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>;
2605 compatible = "mediatek,mt8188-smi-larb";
2606 reg = <0 0x14f02000 0 0x1000>;
2609 clock-names = "apb", "smi";
2610 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
2611 mediatek,larb-id = <SMI_L5_ID>;
2616 compatible = "mediatek,mt8188-smi-larb";
2617 reg = <0 0x14f03000 0 0x1000>;
2620 clock-names = "apb", "smi";
2621 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
2622 mediatek,larb-id = <SMI_L6_ID>;
2626 imgsys: clock-controller@15000000 {
2627 compatible = "mediatek,mt8188-imgsys";
2628 reg = <0 0x15000000 0 0x1000>;
2629 #clock-cells = <1>;
2632 imgsys1_dip_top: clock-controller@15110000 {
2633 compatible = "mediatek,mt8188-imgsys1-dip-top";
2634 reg = <0 0x15110000 0 0x1000>;
2635 #clock-cells = <1>;
2636 #reset-cells = <1>;
2639 imgsys1_dip_nr: clock-controller@15130000 {
2640 compatible = "mediatek,mt8188-imgsys1-dip-nr";
2641 reg = <0 0x15130000 0 0x1000>;
2642 #clock-cells = <1>;
2643 #reset-cells = <1>;
2646 imgsys_wpe1: clock-controller@15220000 {
2647 compatible = "mediatek,mt8188-imgsys-wpe1";
2648 reg = <0 0x15220000 0 0x1000>;
2649 #clock-cells = <1>;
2650 #reset-cells = <1>;
2653 ipesys: clock-controller@15330000 {
2654 compatible = "mediatek,mt8188-ipesys";
2655 reg = <0 0x15330000 0 0x1000>;
2656 #clock-cells = <1>;
2657 #reset-cells = <1>;
2660 imgsys_wpe2: clock-controller@15520000 {
2661 compatible = "mediatek,mt8188-imgsys-wpe2";
2662 reg = <0 0x15520000 0 0x1000>;
2663 #clock-cells = <1>;
2664 #reset-cells = <1>;
2667 imgsys_wpe3: clock-controller@15620000 {
2668 compatible = "mediatek,mt8188-imgsys-wpe3";
2669 reg = <0 0x15620000 0 0x1000>;
2670 #clock-cells = <1>;
2671 #reset-cells = <1>;
2674 camsys: clock-controller@16000000 {
2675 compatible = "mediatek,mt8188-camsys";
2676 reg = <0 0x16000000 0 0x1000>;
2677 #clock-cells = <1>;
2680 camsys_rawa: clock-controller@1604f000 {
2681 compatible = "mediatek,mt8188-camsys-rawa";
2682 reg = <0 0x1604f000 0 0x1000>;
2683 #clock-cells = <1>;
2684 #reset-cells = <1>;
2687 camsys_yuva: clock-controller@1606f000 {
2688 compatible = "mediatek,mt8188-camsys-yuva";
2689 reg = <0 0x1606f000 0 0x1000>;
2690 #clock-cells = <1>;
2691 #reset-cells = <1>;
2694 camsys_rawb: clock-controller@1608f000 {
2695 compatible = "mediatek,mt8188-camsys-rawb";
2696 reg = <0 0x1608f000 0 0x1000>;
2697 #clock-cells = <1>;
2698 #reset-cells = <1>;
2701 camsys_yuvb: clock-controller@160af000 {
2702 compatible = "mediatek,mt8188-camsys-yuvb";
2703 reg = <0 0x160af000 0 0x1000>;
2704 #clock-cells = <1>;
2705 #reset-cells = <1>;
2708 ccusys: clock-controller@17200000 {
2709 compatible = "mediatek,mt8188-ccusys";
2710 reg = <0 0x17200000 0 0x1000>;
2711 #clock-cells = <1>;
2714 video_decoder: video-decoder@18000000 {
2715 compatible = "mediatek,mt8188-vcodec-dec";
2716 reg = <0 0x18000000 0 0x1000>, <0 0x18004000 0 0x1000>;
2719 #address-cells = <2>;
2720 #size-cells = <2>;
2723 video-codec@10000 {
2724 compatible = "mediatek,mtk-vcodec-lat";
2725 reg = <0 0x10000 0 0x800>;
2726 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2727 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
2732 clock-names = "sel", "vdec", "lat", "top";
2743 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>;
2746 video-codec@25000 {
2747 compatible = "mediatek,mtk-vcodec-core";
2748 reg = <0 0x25000 0 0x1000>;
2749 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2750 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
2755 clock-names = "sel", "vdec", "lat", "top";
2768 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC1>;
2773 compatible = "mediatek,mt8188-smi-larb";
2774 reg = <0 0x1800d000 0 0x1000>;
2777 clock-names = "apb", "smi";
2778 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>;
2779 mediatek,larb-id = <SMI_L23_ID>;
2783 vdecsys_soc: clock-controller@1800f000 {
2784 compatible = "mediatek,mt8188-vdecsys-soc";
2785 reg = <0 0x1800f000 0 0x1000>;
2786 #clock-cells = <1>;
2790 compatible = "mediatek,mt8188-smi-larb";
2791 reg = <0 0x1802e000 0 0x1000>;
2794 clock-names = "apb", "smi";
2795 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC1>;
2796 mediatek,larb-id = <SMI_L21_ID>;
2800 vdecsys: clock-controller@1802f000 {
2801 compatible = "mediatek,mt8188-vdecsys";
2802 reg = <0 0x1802f000 0 0x1000>;
2803 #clock-cells = <1>;
2806 vencsys: clock-controller@1a000000 {
2807 compatible = "mediatek,mt8188-vencsys";
2808 reg = <0 0x1a000000 0 0x1000>;
2809 #clock-cells = <1>;
2813 compatible = "mediatek,mt8188-smi-larb";
2814 reg = <0 0x1a010000 0 0x1000>;
2817 clock-names = "apb", "smi";
2818 power-domains = <&spm MT8188_POWER_DOMAIN_VENC>;
2819 mediatek,larb-id = <SMI_L19_ID>;
2823 video_encoder: video-encoder@1a020000 {
2824 compatible = "mediatek,mt8188-vcodec-enc";
2825 reg = <0 0x1a020000 0 0x10000>;
2826 #address-cells = <2>;
2827 #size-cells = <2>;
2828 assigned-clocks = <&topckgen CLK_TOP_VENC>;
2829 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2831 clock-names = "venc_sel";
2844 power-domains = <&spm MT8188_POWER_DOMAIN_VENC>;
2848 jpeg_encoder: jpeg-encoder@1a030000 {
2849 compatible = "mediatek,mt8188-jpgenc", "mediatek,mtk-jpgenc";
2850 reg = <0 0x1a030000 0 0x10000>;
2852 clock-names = "jpgenc";
2858 power-domains = <&spm MT8188_POWER_DOMAIN_VENC>;
2861 jpeg_decoder: jpeg-decoder@1a040000 {
2862 compatible = "mediatek,mt8188-jpgdec", "mediatek,mt2701-jpgdec";
2863 reg = <0 0x1a040000 0 0x10000>;
2866 clock-names = "jpgdec-smi", "jpgdec";
2874 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>;
2878 compatible = "mediatek,mt8188-disp-ovl", "mediatek,mt8195-disp-ovl";
2879 reg = <0 0x1c000000 0 0x1000>;
2883 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2884 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
2887 #address-cells = <1>;
2888 #size-cells = <0>;
2891 reg = <0>;
2896 reg = <1>;
2898 remote-endpoint = <&rdma0_in>;
2905 compatible = "mediatek,mt8188-disp-rdma", "mediatek,mt8195-disp-rdma";
2906 reg = <0 0x1c002000 0 0x1000>;
2910 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2911 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
2914 #address-cells = <1>;
2915 #size-cells = <0>;
2918 reg = <0>;
2920 remote-endpoint = <&ovl0_out>;
2925 reg = <1>;
2927 remote-endpoint = <&color0_in>;
2934 compatible = "mediatek,mt8188-disp-color", "mediatek,mt8173-disp-color";
2935 reg = <0 0x1c003000 0 0x1000>;
2938 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2939 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
2942 #address-cells = <1>;
2943 #size-cells = <0>;
2946 reg = <0>;
2948 remote-endpoint = <&rdma0_out>;
2953 reg = <1>;
2955 remote-endpoint = <&ccorr0_in>;
2962 compatible = "mediatek,mt8188-disp-ccorr", "mediatek,mt8192-disp-ccorr";
2963 reg = <0 0x1c004000 0 0x1000>;
2966 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2967 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
2970 #address-cells = <1>;
2971 #size-cells = <0>;
2974 reg = <0>;
2976 remote-endpoint = <&color0_out>;
2981 reg = <1>;
2983 remote-endpoint = <&aal0_in>;
2990 compatible = "mediatek,mt8188-disp-aal", "mediatek,mt8183-disp-aal";
2991 reg = <0 0x1c005000 0 0x1000>;
2994 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2995 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
2998 #address-cells = <1>;
2999 #size-cells = <0>;
3002 reg = <0>;
3004 remote-endpoint = <&ccorr0_out>;
3009 reg = <1>;
3011 remote-endpoint = <&gamma0_in>;
3018 compatible = "mediatek,mt8188-disp-gamma", "mediatek,mt8195-disp-gamma";
3019 reg = <0 0x1c006000 0 0x1000>;
3022 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
3023 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
3026 #address-cells = <1>;
3027 #size-cells = <0>;
3030 reg = <0>;
3032 remote-endpoint = <&aal0_out>;
3037 reg = <1>;
3044 compatible = "mediatek,mt8188-disp-dither", "mediatek,mt8183-disp-dither";
3045 reg = <0 0x1c007000 0 0x1000>;
3048 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
3049 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
3052 #address-cells = <1>;
3053 #size-cells = <0>;
3056 reg = <0>;
3061 reg = <1>;
3068 compatible = "mediatek,mt8188-dsi";
3069 reg = <0 0x1c008000 0 0x1000>;
3073 clock-names = "engine", "digital", "hs";
3076 phy-names = "dphy";
3077 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
3083 compatible = "mediatek,mt8188-disp-dsc", "mediatek,mt8195-disp-dsc";
3084 reg = <0 0x1c009000 0 0x1000>;
3087 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
3088 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;
3092 compatible = "mediatek,mt8188-dsi";
3093 reg = <0 0x1c012000 0 0x1000>;
3097 clock-names = "engine", "digital", "hs";
3100 phy-names = "dphy";
3101 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
3107 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";
3108 reg = <0 0x1c014000 0 0x1000>;
3111 clock-names = "merge", "merge_async";
3113 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
3114 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
3117 dp_intf0: dp-intf@1c015000 {
3118 compatible = "mediatek,mt8188-dp-intf";
3119 reg = <0 0x1c015000 0 0x1000>;
3123 clock-names = "pixel", "engine", "pll";
3125 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
3130 compatible = "mediatek,mt8188-disp-mutex";
3131 reg = <0 0x1c016000 0 0x1000>;
3134 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
3135 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>;
3136 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
3140 compatible = "mediatek,mt8188-disp-postmask",
3141 "mediatek,mt8192-disp-postmask";
3142 reg = <0 0x1c01a000 0 0x1000>;
3145 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
3146 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>;
3149 #address-cells = <1>;
3150 #size-cells = <0>;
3153 reg = <0>;
3158 reg = <1>;
3165 compatible = "mediatek,mt8188-vdosys0", "syscon";
3166 reg = <0 0x1c01d000 0 0x1000>;
3167 #clock-cells = <1>;
3168 #reset-cells = <1>;
3170 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xd000 0x1000>;
3174 compatible = "mediatek,mt8188-smi-larb";
3175 reg = <0 0x1c022000 0 0x1000>;
3178 clock-names = "apb", "smi";
3179 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
3180 mediatek,larb-id = <SMI_L0_ID>;
3185 compatible = "mediatek,mt8188-smi-larb";
3186 reg = <0 0x1c023000 0 0x1000>;
3189 clock-names = "apb", "smi";
3190 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
3191 mediatek,larb-id = <SMI_L1_ID>;
3196 compatible = "mediatek,mt8188-smi-common-vdo";
3197 reg = <0 0x1c024000 0 0x1000>;
3200 clock-names = "apb", "smi";
3201 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
3205 compatible = "mediatek,mt8188-iommu-vdo";
3206 reg = <0 0x1c028000 0 0x5000>;
3208 clock-names = "bclk";
3210 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
3211 #iommu-cells = <1>;
3216 compatible = "mediatek,mt8188-vdosys1", "syscon";
3217 reg = <0 0x1c100000 0 0x1000>;
3218 #clock-cells = <1>;
3219 #reset-cells = <1>;
3221 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0 0x1000>;
3225 compatible = "mediatek,mt8188-disp-mutex";
3226 reg = <0 0x1c101000 0 0x1000>;
3229 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3230 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>;
3231 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
3235 compatible = "mediatek,mt8188-smi-larb";
3236 reg = <0 0x1c102000 0 0x1000>;
3239 clock-names = "apb", "smi";
3240 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3241 mediatek,larb-id = <SMI_L2_ID>;
3246 compatible = "mediatek,mt8188-smi-larb";
3247 reg = <0 0x1c103000 0 0x1000>;
3250 clock-names = "apb", "smi";
3251 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3252 mediatek,larb-id = <SMI_L3_ID>;
3257 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
3258 reg = <0 0x1c104000 0 0x1000>;
3262 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3263 #dma-cells = <1>;
3264 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
3268 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
3269 reg = <0 0x1c105000 0 0x1000>;
3273 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3274 #dma-cells = <1>;
3275 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>;
3279 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
3280 reg = <0 0x1c106000 0 0x1000>;
3284 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3285 #dma-cells = <1>;
3286 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>;
3290 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
3291 reg = <0 0x1c107000 0 0x1000>;
3295 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3296 #dma-cells = <1>;
3297 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>;
3301 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
3302 reg = <0 0x1c108000 0 0x1000>;
3306 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3307 #dma-cells = <1>;
3308 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>;
3312 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
3313 reg = <0 0x1c109000 0 0x1000>;
3317 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3318 #dma-cells = <1>;
3319 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>;
3323 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
3324 reg = <0 0x1c10a000 0 0x1000>;
3328 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3329 #dma-cells = <1>;
3330 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>;
3334 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
3335 reg = <0 0x1c10b000 0 0x1000>;
3339 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3340 #dma-cells = <1>;
3341 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>;
3345 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";
3346 reg = <0 0x1c10c000 0 0x1000>;
3349 clock-names = "merge", "merge_async";
3351 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3353 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>;
3354 mediatek,merge-mute;
3358 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";
3359 reg = <0 0x1c10d000 0 0x1000>;
3362 clock-names = "merge", "merge_async";
3364 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3366 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>;
3367 mediatek,merge-mute;
3371 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";
3372 reg = <0 0x1c10e000 0 0x1000>;
3375 clock-names = "merge", "merge_async";
3377 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3379 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>;
3380 mediatek,merge-mute;
3384 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";
3385 reg = <0 0x1c10f000 0 0x1000>;
3388 clock-names = "merge", "merge_async";
3390 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3392 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>;
3393 mediatek,merge-mute;
3397 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";
3398 reg = <0 0x1c110000 0 0x1000>;
3401 clock-names = "merge", "merge_async";
3403 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3405 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>;
3406 mediatek,merge-fifo-en;
3409 dp_intf1: dp-intf@1c113000 {
3410 compatible = "mediatek,mt8188-dp-intf";
3411 reg = <0 0x1c113000 0 0x1000>;
3415 clock-names = "pixel", "engine", "pll";
3417 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3422 compatible = "mediatek,mt8188-disp-ethdr", "mediatek,mt8195-disp-ethdr";
3423 reg = <0 0x1c114000 0 0x1000>,
3430 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3446 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3453 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3460 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
3470 compatible = "mediatek,mt8188-disp-padding";
3471 reg = <0 0x1c11d000 0 0x1000>;
3473 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3474 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>;
3478 compatible = "mediatek,mt8188-disp-padding";
3479 reg = <0 0x1c11e000 0 0x1000>;
3481 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3482 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xe000 0x1000>;
3486 compatible = "mediatek,mt8188-disp-padding";
3487 reg = <0 0x1c11f000 0 0x1000>;
3489 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3490 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xf000 0x1000>;
3494 compatible = "mediatek,mt8188-disp-padding";
3495 reg = <0 0x1c120000 0 0x1000>;
3497 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3498 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x0000 0x1000>;
3502 compatible = "mediatek,mt8188-disp-padding";
3503 reg = <0 0x1c121000 0 0x1000>;
3505 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3506 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x1000 0x1000>;
3510 compatible = "mediatek,mt8188-disp-padding";
3511 reg = <0 0x1c122000 0 0x1000>;
3513 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3514 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x2000 0x1000>;
3518 compatible = "mediatek,mt8188-disp-padding";
3519 reg = <0 0x1c123000 0 0x1000>;
3521 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3522 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x3000 0x1000>;
3526 compatible = "mediatek,mt8188-disp-padding";
3527 reg = <0 0x1c124000 0 0x1000>;
3529 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3530 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x4000 0x1000>;
3533 edp_tx: edp-tx@1c500000 {
3534 compatible = "mediatek,mt8188-edp-tx";
3535 reg = <0 0x1c500000 0 0x8000>;
3537 nvmem-cells = <&dp_calib_data>;
3538 nvmem-cell-names = "dp_calibration_data";
3539 power-domains = <&spm MT8188_POWER_DOMAIN_EDP_TX>;
3540 max-linkrate-mhz = <8100>;
3544 dp_tx: dp-tx@1c600000 {
3545 compatible = "mediatek,mt8188-dp-tx";
3546 reg = <0 0x1c600000 0 0x8000>;
3548 nvmem-cells = <&dp_calib_data>;
3549 nvmem-cell-names = "dp_calibration_data";
3550 power-domains = <&spm MT8188_POWER_DOMAIN_DP_TX>;
3551 max-linkrate-mhz = <5400>;