Lines Matching +full:mt8195 +full:- +full:scpsys
1 // SPDX-License-Identifier: GPL-2.0+
7 /dts-v1/;
8 #include <dt-bindings/clock/mediatek,mt8188-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/mailbox/mediatek,mt8188-gce.h>
12 #include <dt-bindings/memory/mediatek,mt8188-memory-port.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
15 #include <dt-bindings/power/mediatek,mt8188-power.h>
16 #include <dt-bindings/reset/mt8188-resets.h>
17 #include <dt-bindings/thermal/thermal.h>
18 #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
27 dp-intf0 = &dp_intf0;
28 dp-intf1 = &dp_intf1;
47 vdo1-rdma0 = &vdo1_rdma0;
48 vdo1-rdma1 = &vdo1_rdma1;
49 vdo1-rdma2 = &vdo1_rdma2;
50 vdo1-rdma3 = &vdo1_rdma3;
51 vdo1-rdma4 = &vdo1_rdma4;
52 vdo1-rdma5 = &vdo1_rdma5;
53 vdo1-rdma6 = &vdo1_rdma6;
54 vdo1-rdma7 = &vdo1_rdma7;
58 #address-cells = <1>;
59 #size-cells = <0>;
63 compatible = "arm,cortex-a55";
65 enable-method = "psci";
66 clock-frequency = <2000000000>;
67 capacity-dmips-mhz = <282>;
68 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
69 i-cache-size = <32768>;
70 i-cache-line-size = <64>;
71 i-cache-sets = <128>;
72 d-cache-size = <32768>;
73 d-cache-line-size = <64>;
74 d-cache-sets = <128>;
75 next-level-cache = <&l2_0>;
76 performance-domains = <&performance 0>;
77 #cooling-cells = <2>;
82 compatible = "arm,cortex-a55";
84 enable-method = "psci";
85 clock-frequency = <2000000000>;
86 capacity-dmips-mhz = <282>;
87 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
88 i-cache-size = <32768>;
89 i-cache-line-size = <64>;
90 i-cache-sets = <128>;
91 d-cache-size = <32768>;
92 d-cache-line-size = <64>;
93 d-cache-sets = <128>;
94 next-level-cache = <&l2_0>;
95 performance-domains = <&performance 0>;
96 #cooling-cells = <2>;
101 compatible = "arm,cortex-a55";
103 enable-method = "psci";
104 clock-frequency = <2000000000>;
105 capacity-dmips-mhz = <282>;
106 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
107 i-cache-size = <32768>;
108 i-cache-line-size = <64>;
109 i-cache-sets = <128>;
110 d-cache-size = <32768>;
111 d-cache-line-size = <64>;
112 d-cache-sets = <128>;
113 next-level-cache = <&l2_0>;
114 performance-domains = <&performance 0>;
115 #cooling-cells = <2>;
120 compatible = "arm,cortex-a55";
122 enable-method = "psci";
123 clock-frequency = <2000000000>;
124 capacity-dmips-mhz = <282>;
125 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
126 i-cache-size = <32768>;
127 i-cache-line-size = <64>;
128 i-cache-sets = <128>;
129 d-cache-size = <32768>;
130 d-cache-line-size = <64>;
131 d-cache-sets = <128>;
132 next-level-cache = <&l2_0>;
133 performance-domains = <&performance 0>;
134 #cooling-cells = <2>;
139 compatible = "arm,cortex-a55";
141 enable-method = "psci";
142 clock-frequency = <2000000000>;
143 capacity-dmips-mhz = <282>;
144 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
145 i-cache-size = <32768>;
146 i-cache-line-size = <64>;
147 i-cache-sets = <128>;
148 d-cache-size = <32768>;
149 d-cache-line-size = <64>;
150 d-cache-sets = <128>;
151 next-level-cache = <&l2_0>;
152 performance-domains = <&performance 0>;
153 #cooling-cells = <2>;
158 compatible = "arm,cortex-a55";
160 enable-method = "psci";
161 clock-frequency = <2000000000>;
162 capacity-dmips-mhz = <282>;
163 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
164 i-cache-size = <32768>;
165 i-cache-line-size = <64>;
166 i-cache-sets = <128>;
167 d-cache-size = <32768>;
168 d-cache-line-size = <64>;
169 d-cache-sets = <128>;
170 next-level-cache = <&l2_0>;
171 performance-domains = <&performance 0>;
172 #cooling-cells = <2>;
177 compatible = "arm,cortex-a78";
179 enable-method = "psci";
180 clock-frequency = <2600000000>;
181 capacity-dmips-mhz = <1024>;
182 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
183 i-cache-size = <65536>;
184 i-cache-line-size = <64>;
185 i-cache-sets = <256>;
186 d-cache-size = <65536>;
187 d-cache-line-size = <64>;
188 d-cache-sets = <256>;
189 next-level-cache = <&l2_1>;
190 performance-domains = <&performance 1>;
191 #cooling-cells = <2>;
196 compatible = "arm,cortex-a78";
198 enable-method = "psci";
199 clock-frequency = <2600000000>;
200 capacity-dmips-mhz = <1024>;
201 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
202 i-cache-size = <65536>;
203 i-cache-line-size = <64>;
204 i-cache-sets = <256>;
205 d-cache-size = <65536>;
206 d-cache-line-size = <64>;
207 d-cache-sets = <256>;
208 next-level-cache = <&l2_1>;
209 performance-domains = <&performance 1>;
210 #cooling-cells = <2>;
213 cpu-map {
249 idle-states {
250 entry-method = "psci";
252 cpu_off_l: cpu-off-l {
253 compatible = "arm,idle-state";
254 arm,psci-suspend-param = <0x00010000>;
255 local-timer-stop;
256 entry-latency-us = <50>;
257 exit-latency-us = <95>;
258 min-residency-us = <580>;
261 cpu_off_b: cpu-off-b {
262 compatible = "arm,idle-state";
263 arm,psci-suspend-param = <0x00010000>;
264 local-timer-stop;
265 entry-latency-us = <45>;
266 exit-latency-us = <140>;
267 min-residency-us = <740>;
270 cluster_off_l: cluster-off-l {
271 compatible = "arm,idle-state";
272 arm,psci-suspend-param = <0x01010010>;
273 local-timer-stop;
274 entry-latency-us = <55>;
275 exit-latency-us = <155>;
276 min-residency-us = <840>;
279 cluster_off_b: cluster-off-b {
280 compatible = "arm,idle-state";
281 arm,psci-suspend-param = <0x01010010>;
282 local-timer-stop;
283 entry-latency-us = <50>;
284 exit-latency-us = <200>;
285 min-residency-us = <1000>;
289 l2_0: l2-cache0 {
291 cache-level = <2>;
292 cache-size = <131072>;
293 cache-line-size = <64>;
294 cache-sets = <512>;
295 next-level-cache = <&l3_0>;
296 cache-unified;
299 l2_1: l2-cache1 {
301 cache-level = <2>;
302 cache-size = <262144>;
303 cache-line-size = <64>;
304 cache-sets = <512>;
305 next-level-cache = <&l3_0>;
306 cache-unified;
309 l3_0: l3-cache {
311 cache-level = <3>;
312 cache-size = <2097152>;
313 cache-line-size = <64>;
314 cache-sets = <2048>;
315 cache-unified;
319 clk13m: oscillator-13m {
320 compatible = "fixed-clock";
321 #clock-cells = <0>;
322 clock-frequency = <13000000>;
323 clock-output-names = "clk13m";
326 clk26m: oscillator-26m {
327 compatible = "fixed-clock";
328 #clock-cells = <0>;
329 clock-frequency = <26000000>;
330 clock-output-names = "clk26m";
333 clk32k: oscillator-32k {
334 compatible = "fixed-clock";
335 #clock-cells = <0>;
336 clock-frequency = <32768>;
337 clock-output-names = "clk32k";
340 gpu_opp_table: opp-table-gpu {
341 compatible = "operating-points-v2";
342 opp-shared;
344 opp-390000000 {
345 opp-hz = /bits/ 64 <390000000>;
346 opp-microvolt = <575000>;
347 opp-supported-hw = <0xff>;
349 opp-431000000 {
350 opp-hz = /bits/ 64 <431000000>;
351 opp-microvolt = <587500>;
352 opp-supported-hw = <0xff>;
354 opp-473000000 {
355 opp-hz = /bits/ 64 <473000000>;
356 opp-microvolt = <600000>;
357 opp-supported-hw = <0xff>;
359 opp-515000000 {
360 opp-hz = /bits/ 64 <515000000>;
361 opp-microvolt = <612500>;
362 opp-supported-hw = <0xff>;
364 opp-556000000 {
365 opp-hz = /bits/ 64 <556000000>;
366 opp-microvolt = <625000>;
367 opp-supported-hw = <0xff>;
369 opp-598000000 {
370 opp-hz = /bits/ 64 <598000000>;
371 opp-microvolt = <637500>;
372 opp-supported-hw = <0xff>;
374 opp-640000000 {
375 opp-hz = /bits/ 64 <640000000>;
376 opp-microvolt = <650000>;
377 opp-supported-hw = <0xff>;
379 opp-670000000 {
380 opp-hz = /bits/ 64 <670000000>;
381 opp-microvolt = <662500>;
382 opp-supported-hw = <0xff>;
384 opp-700000000 {
385 opp-hz = /bits/ 64 <700000000>;
386 opp-microvolt = <675000>;
387 opp-supported-hw = <0xff>;
389 opp-730000000 {
390 opp-hz = /bits/ 64 <730000000>;
391 opp-microvolt = <687500>;
392 opp-supported-hw = <0xff>;
394 opp-760000000 {
395 opp-hz = /bits/ 64 <760000000>;
396 opp-microvolt = <700000>;
397 opp-supported-hw = <0xff>;
399 opp-790000000 {
400 opp-hz = /bits/ 64 <790000000>;
401 opp-microvolt = <712500>;
402 opp-supported-hw = <0xff>;
404 opp-835000000 {
405 opp-hz = /bits/ 64 <835000000>;
406 opp-microvolt = <731250>;
407 opp-supported-hw = <0xff>;
409 opp-880000000 {
410 opp-hz = /bits/ 64 <880000000>;
411 opp-microvolt = <750000>;
412 opp-supported-hw = <0xff>;
414 opp-915000000 {
415 opp-hz = /bits/ 64 <915000000>;
416 opp-microvolt = <775000>;
417 opp-supported-hw = <0x8f>;
419 opp-915000000-5 {
420 opp-hz = /bits/ 64 <915000000>;
421 opp-microvolt = <762500>;
422 opp-supported-hw = <0x30>;
424 opp-915000000-6 {
425 opp-hz = /bits/ 64 <915000000>;
426 opp-microvolt = <750000>;
427 opp-supported-hw = <0x70>;
429 opp-950000000 {
430 opp-hz = /bits/ 64 <950000000>;
431 opp-microvolt = <800000>;
432 opp-supported-hw = <0x8f>;
434 opp-950000000-5 {
435 opp-hz = /bits/ 64 <950000000>;
436 opp-microvolt = <775000>;
437 opp-supported-hw = <0x30>;
439 opp-950000000-6 {
440 opp-hz = /bits/ 64 <950000000>;
441 opp-microvolt = <750000>;
442 opp-supported-hw = <0x70>;
446 pmu-a55 {
447 compatible = "arm,cortex-a55-pmu";
448 interrupt-parent = <&gic>;
452 pmu-a78 {
453 compatible = "arm,cortex-a78-pmu";
454 interrupt-parent = <&gic>;
459 compatible = "arm,psci-1.0";
468 thermal_zones: thermal-zones {
469 cpu-little0-thermal {
470 polling-delay = <1000>;
471 polling-delay-passive = <150>;
472 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU0>;
475 cpu_little0_alert0: trip-alert0 {
481 cpu_little0_alert1: trip-alert1 {
487 cpu_little0_crit: trip-crit {
494 cooling-maps {
497 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
507 cpu-little1-thermal {
508 polling-delay = <1000>;
509 polling-delay-passive = <150>;
510 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU1>;
513 cpu_little1_alert0: trip-alert0 {
519 cpu_little1_alert1: trip-alert1 {
525 cpu_little1_crit: trip-crit {
532 cooling-maps {
535 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
545 cpu-little2-thermal {
546 polling-delay = <1000>;
547 polling-delay-passive = <150>;
548 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU2>;
551 cpu_little2_alert0: trip-alert0 {
557 cpu_little2_alert1: trip-alert1 {
563 cpu_little2_crit: trip-crit {
570 cooling-maps {
573 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
583 cpu-little3-thermal {
584 polling-delay = <1000>;
585 polling-delay-passive = <150>;
586 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU3>;
589 cpu_little3_alert0: trip-alert0 {
595 cpu_little3_alert1: trip-alert1 {
601 cpu_little3_crit: trip-crit {
608 cooling-maps {
611 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
621 cpu-big0-thermal {
622 polling-delay = <1000>;
623 polling-delay-passive = <100>;
624 thermal-sensors = <&lvts_mcu MT8188_MCU_BIG_CPU0>;
627 cpu_big0_alert0: trip-alert0 {
633 cpu_big0_alert1: trip-alert1 {
639 cpu_big0_crit: trip-crit {
646 cooling-maps {
649 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
655 cpu-big1-thermal {
656 polling-delay = <1000>;
657 polling-delay-passive = <100>;
658 thermal-sensors = <&lvts_mcu MT8188_MCU_BIG_CPU1>;
661 cpu_big1_alert0: trip-alert0 {
667 cpu_big1_alert1: trip-alert1 {
673 cpu_big1_crit: trip-crit {
680 cooling-maps {
683 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
689 apu-thermal {
690 polling-delay = <1000>;
691 polling-delay-passive = <250>;
692 thermal-sensors = <&lvts_ap MT8188_AP_APU>;
695 apu_alert0: trip-alert0 {
701 apu_alert1: trip-alert1 {
707 apu_crit: trip-crit {
715 gpu-thermal {
716 polling-delay = <1000>;
717 polling-delay-passive = <250>;
718 thermal-sensors = <&lvts_ap MT8188_AP_GPU0>;
721 gpu_alert0: trip-alert0 {
727 gpu_alert1: trip-alert1 {
733 gpu_crit: trip-crit {
740 cooling-maps {
743 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
748 gpu1-thermal {
749 polling-delay = <1000>;
750 polling-delay-passive = <250>;
751 thermal-sensors = <&lvts_ap MT8188_AP_GPU1>;
754 gpu1_alert0: trip-alert0 {
760 gpu1_alert1: trip-alert1 {
766 gpu1_crit: trip-crit {
773 cooling-maps {
776 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
781 adsp-thermal {
782 polling-delay = <1000>;
783 polling-delay-passive = <250>;
784 thermal-sensors = <&lvts_ap MT8188_AP_ADSP>;
787 soc_alert0: trip-alert0 {
793 soc_alert1: trip-alert1 {
799 soc_crit: trip-crit {
807 vdo-thermal {
808 polling-delay = <1000>;
809 polling-delay-passive = <250>;
810 thermal-sensors = <&lvts_ap MT8188_AP_VDO>;
813 soc1_alert0: trip-alert0 {
819 soc1_alert1: trip-alert1 {
825 soc1_crit: trip-crit {
833 infra-thermal {
834 polling-delay = <1000>;
835 polling-delay-passive = <250>;
836 thermal-sensors = <&lvts_ap MT8188_AP_INFRA>;
839 soc2_alert0: trip-alert0 {
845 soc2_alert1: trip-alert1 {
851 soc2_crit: trip-crit {
859 cam1-thermal {
860 polling-delay = <1000>;
861 polling-delay-passive = <250>;
862 thermal-sensors = <&lvts_ap MT8188_AP_CAM1>;
865 cam1_alert0: trip-alert0 {
871 cam1_alert1: trip-alert1 {
877 cam1_crit: trip-crit {
885 cam2-thermal {
886 polling-delay = <1000>;
887 polling-delay-passive = <250>;
888 thermal-sensors = <&lvts_ap MT8188_AP_CAM2>;
891 cam2_alert0: trip-alert0 {
897 cam2_alert1: trip-alert1 {
903 cam2_crit: trip-crit {
913 compatible = "arm,armv8-timer";
914 interrupt-parent = <&gic>;
919 clock-frequency = <13000000>;
923 #address-cells = <2>;
924 #size-cells = <2>;
925 compatible = "simple-bus";
926 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
929 performance: performance-controller@11bc10 {
930 compatible = "mediatek,cpufreq-hw";
932 #performance-domain-cells = <1>;
935 gic: interrupt-controller@c000000 {
936 compatible = "arm,gic-v3";
937 #interrupt-cells = <4>;
938 #redistributor-regions = <1>;
939 interrupt-parent = <&gic>;
940 interrupt-controller;
945 ppi-partitions {
946 ppi_cluster0: interrupt-partition-0 {
950 ppi_cluster1: interrupt-partition-1 {
957 compatible = "mediatek,mt8188-topckgen", "syscon";
959 #clock-cells = <1>;
963 compatible = "mediatek,mt8188-infracfg-ao", "syscon";
965 #clock-cells = <1>;
966 #reset-cells = <1>;
970 compatible = "mediatek,mt8188-pericfg", "syscon";
972 #clock-cells = <1>;
976 compatible = "mediatek,mt8188-pinctrl";
983 reg-names = "iocfg0", "iocfg_rm", "iocfg_lt",
985 gpio-controller;
986 #gpio-cells = <2>;
987 gpio-ranges = <&pio 0 0 176>;
988 interrupt-controller;
990 #interrupt-cells = <2>;
993 scpsys: syscon@10006000 { label
994 compatible = "mediatek,mt8188-scpsys", "syscon", "simple-mfd";
998 spm: power-controller {
999 compatible = "mediatek,mt8188-power-controller";
1000 #address-cells = <1>;
1001 #size-cells = <0>;
1002 #power-domain-cells = <1>;
1005 mfg0: power-domain@MT8188_POWER_DOMAIN_MFG0 {
1007 #address-cells = <1>;
1008 #size-cells = <0>;
1009 #power-domain-cells = <1>;
1011 mfg1: power-domain@MT8188_POWER_DOMAIN_MFG1 {
1015 clock-names = "mfg", "alt";
1017 #address-cells = <1>;
1018 #size-cells = <0>;
1019 #power-domain-cells = <1>;
1021 power-domain@MT8188_POWER_DOMAIN_MFG2 {
1023 #power-domain-cells = <0>;
1026 power-domain@MT8188_POWER_DOMAIN_MFG3 {
1028 #power-domain-cells = <0>;
1031 power-domain@MT8188_POWER_DOMAIN_MFG4 {
1033 #power-domain-cells = <0>;
1038 power-domain@MT8188_POWER_DOMAIN_VPPSYS0 {
1068 clock-names = "top", "cam", "ccu", "img", "venc",
1070 "ss-sram-cmn", "ss-sram-v0l0", "ss-sram-v0l1",
1071 "ss-sram-ve0", "ss-sram-ve1", "ss-sram-ifa",
1072 "ss-sram-cam", "ss-sram-v1l5", "ss-sram-v1l6",
1073 "ss-sram-rdr", "ss-iommu", "ss-imgcam",
1074 "ss-emi", "ss-subcmn-rdr", "ss-rsi",
1075 "ss-cmn-l4", "ss-vdec1", "ss-wpe",
1076 "ss-cvdo-ve1";
1078 #address-cells = <1>;
1079 #size-cells = <0>;
1080 #power-domain-cells = <1>;
1082 power-domain@MT8188_POWER_DOMAIN_VDOSYS0 {
1093 clock-names = "cfgck", "cfgxo", "ss-gals",
1094 "ss-cmn", "ss-emi", "ss-iommu",
1095 "ss-larb", "ss-rsi", "ss-bus";
1097 #address-cells = <1>;
1098 #size-cells = <0>;
1099 #power-domain-cells = <1>;
1101 power-domain@MT8188_POWER_DOMAIN_VPPSYS1 {
1109 clock-names = "cfgck", "cfgxo",
1110 "ss-vpp1-g5", "ss-vpp1-g6",
1111 "ss-vpp1-l5", "ss-vpp1-l6";
1113 #power-domain-cells = <0>;
1116 power-domain@MT8188_POWER_DOMAIN_VDEC0 {
1119 clock-names = "ss-vdec1-soc-l1";
1121 #address-cells = <1>;
1122 #size-cells = <0>;
1123 #power-domain-cells = <1>;
1125 power-domain@MT8188_POWER_DOMAIN_VDEC1 {
1128 clock-names = "ss-vdec2-l1";
1130 #power-domain-cells = <0>;
1134 cam_vcore: power-domain@MT8188_POWER_DOMAIN_CAM_VCORE {
1140 clock-names = "cam", "ccu", "bus", "cfgck";
1142 #address-cells = <1>;
1143 #size-cells = <0>;
1144 #power-domain-cells = <1>;
1146 power-domain@MT8188_POWER_DOMAIN_CAM_MAIN {
1153 clock-names= "ss-cam-l13", "ss-cam-l14",
1154 "ss-cam-mm0", "ss-cam-mm1",
1155 "ss-camsys";
1157 #address-cells = <1>;
1158 #size-cells = <0>;
1159 #power-domain-cells = <1>;
1161 power-domain@MT8188_POWER_DOMAIN_CAM_SUBB {
1166 clock-names = "ss-camb-sub",
1167 "ss-camb-raw",
1168 "ss-camb-yuv";
1169 #power-domain-cells = <0>;
1172 power-domain@MT8188_POWER_DOMAIN_CAM_SUBA {
1177 clock-names = "ss-cama-sub",
1178 "ss-cama-raw",
1179 "ss-cama-yuv";
1180 #power-domain-cells = <0>;
1185 power-domain@MT8188_POWER_DOMAIN_VDOSYS1 {
1192 clock-names = "cfgck", "cfgxo", "ss-larb2",
1193 "ss-larb3", "ss-gals";
1195 #address-cells = <1>;
1196 #size-cells = <0>;
1197 #power-domain-cells = <1>;
1199 power-domain@MT8188_POWER_DOMAIN_HDMI_TX {
1203 clock-names = "bus", "hdcp";
1205 #power-domain-cells = <0>;
1208 power-domain@MT8188_POWER_DOMAIN_DP_TX {
1211 #power-domain-cells = <0>;
1214 power-domain@MT8188_POWER_DOMAIN_EDP_TX {
1217 #power-domain-cells = <0>;
1221 power-domain@MT8188_POWER_DOMAIN_VENC {
1227 clock-names = "ss-ve1-larb", "ss-ve1-core",
1228 "ss-ve1-gals", "ss-ve1-sram";
1230 #power-domain-cells = <0>;
1233 power-domain@MT8188_POWER_DOMAIN_WPE {
1237 clock-names = "ss-wpe-l7", "ss-wpe-l7pce";
1239 #power-domain-cells = <0>;
1244 power-domain@MT8188_POWER_DOMAIN_PEXTP_MAC_P0 {
1248 clock-names = "ss-pextp-fmem";
1249 #power-domain-cells = <0>;
1252 power-domain@MT8188_POWER_DOMAIN_CSIRX_TOP {
1256 clock-names = "seninf0", "seninf1";
1257 #power-domain-cells = <0>;
1260 power-domain@MT8188_POWER_DOMAIN_PEXTP_PHY_TOP {
1262 #power-domain-cells = <0>;
1265 power-domain@MT8188_POWER_DOMAIN_ADSP_AO {
1269 clock-names = "bus", "main";
1271 #address-cells = <1>;
1272 #size-cells = <0>;
1273 #power-domain-cells = <1>;
1275 power-domain@MT8188_POWER_DOMAIN_ADSP_INFRA {
1278 #address-cells = <1>;
1279 #size-cells = <0>;
1280 #power-domain-cells = <1>;
1282 power-domain@MT8188_POWER_DOMAIN_AUDIO_ASRC {
1285 clock-names = "asm";
1287 #power-domain-cells = <0>;
1290 power-domain@MT8188_POWER_DOMAIN_AUDIO {
1295 clock-names = "a1sys", "intbus", "adspck";
1297 #power-domain-cells = <0>;
1300 power-domain@MT8188_POWER_DOMAIN_ADSP {
1303 #power-domain-cells = <0>;
1308 power-domain@MT8188_POWER_DOMAIN_ETHER {
1311 clock-names = "ethermac";
1313 #power-domain-cells = <0>;
1319 compatible = "mediatek,mt8188-wdt";
1321 mediatek,disable-extrst;
1322 #reset-cells = <1>;
1326 compatible = "mediatek,mt8188-apmixedsys", "syscon";
1328 #clock-cells = <1>;
1332 compatible = "mediatek,mt8188-timer", "mediatek,mt6765-timer";
1339 compatible = "mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap", "syscon";
1341 reg-names = "pwrap";
1345 clock-names = "spi", "wrap";
1349 compatible = "mediatek,mt8188-spmi", "mediatek,mt8195-spmi";
1351 reg-names = "pmif", "spmimst";
1352 assigned-clocks = <&topckgen CLK_TOP_SPMI_M_MST>;
1353 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
1357 clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux";
1361 compatible = "mediatek,mt8188-iommu-infra";
1364 #iommu-cells = <1>;
1368 compatible = "mediatek,mt8188-gce";
1371 #mbox-cells = <2>;
1376 compatible = "mediatek,mt8188-gce";
1379 #mbox-cells = <2>;
1384 compatible = "mediatek,mt8188-scp";
1387 reg-names = "sram", "cfg";
1391 afe: audio-controller@10b10000 {
1392 compatible = "mediatek,mt8188-afe";
1394 assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP>;
1395 assigned-clock-parents = <&clk26m>;
1419 clock-names = "clk26m",
1443 power-domains = <&spm MT8188_POWER_DOMAIN_AUDIO>;
1445 reset-names = "audiosys";
1452 compatible = "mediatek,mt8188-dsp";
1457 reg-names = "cfg", "sram", "sec", "bus";
1458 assigned-clocks = <&topckgen CLK_TOP_ADSP>;
1461 clock-names = "audiodsp", "adsp_bus";
1463 mbox-names = "rx", "tx";
1464 power-domains = <&spm MT8188_POWER_DOMAIN_ADSP>;
1469 compatible = "mediatek,mt8188-adsp-mbox", "mediatek,mt8186-adsp-mbox";
1472 #mbox-cells = <0>;
1476 compatible = "mediatek,mt8188-adsp-mbox", "mediatek,mt8186-adsp-mbox";
1479 #mbox-cells = <0>;
1482 adsp_audio26m: clock-controller@10b91100 {
1483 compatible = "mediatek,mt8188-adsp-audio26m";
1485 #clock-cells = <1>;
1489 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
1493 clock-names = "baud", "bus";
1498 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
1502 clock-names = "baud", "bus";
1507 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
1511 clock-names = "baud", "bus";
1516 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
1520 clock-names = "baud", "bus";
1525 compatible = "mediatek,mt8188-auxadc", "mediatek,mt8173-auxadc";
1528 clock-names = "main";
1529 #io-channel-cells = <1>;
1534 compatible = "mediatek,mt8188-pericfg-ao", "syscon";
1536 #clock-cells = <1>;
1540 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1541 #address-cells = <1>;
1542 #size-cells = <0>;
1548 clock-names = "parent-clk", "sel-clk", "spi-clk";
1552 lvts_ap: thermal-sensor@1100b000 {
1553 compatible = "mediatek,mt8188-lvts-ap";
1558 nvmem-cells = <&lvts_efuse_data1>;
1559 nvmem-cell-names = "lvts-calib-data-1";
1560 #thermal-sensor-cells = <1>;
1564 compatible = "mediatek,mt8188-disp-pwm", "mediatek,mt8183-disp-pwm";
1568 clock-names = "main", "mm";
1570 #pwm-cells = <2>;
1575 compatible = "mediatek,mt8188-disp-pwm", "mediatek,mt8183-disp-pwm";
1579 clock-names = "main", "mm";
1581 #pwm-cells = <2>;
1586 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1587 #address-cells = <1>;
1588 #size-cells = <0>;
1594 clock-names = "parent-clk", "sel-clk", "spi-clk";
1599 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1600 #address-cells = <1>;
1601 #size-cells = <0>;
1607 clock-names = "parent-clk", "sel-clk", "spi-clk";
1612 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1613 #address-cells = <1>;
1614 #size-cells = <0>;
1620 clock-names = "parent-clk", "sel-clk", "spi-clk";
1625 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1626 #address-cells = <1>;
1627 #size-cells = <0>;
1633 clock-names = "parent-clk", "sel-clk", "spi-clk";
1638 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1639 #address-cells = <1>;
1640 #size-cells = <0>;
1646 clock-names = "parent-clk", "sel-clk", "spi-clk";
1651 compatible = "mediatek,mt8188-gmac", "mediatek,mt8195-gmac",
1652 "snps,dwmac-5.10a";
1655 interrupt-names = "macirq";
1662 clock-names = "axi", "apb", "mac_main", "ptp_ref",
1664 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
1667 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
1670 power-domains = <&spm MT8188_POWER_DOMAIN_ETHER>;
1672 snps,axi-config = <&stmmac_axi_setup>;
1673 snps,mtl-rx-config = <&mtl_rx_setup>;
1674 snps,mtl-tx-config = <&mtl_tx_setup>;
1677 snps,clk-csr = <0>;
1681 compatible = "snps,dwmac-mdio";
1682 #address-cells = <1>;
1683 #size-cells = <0>;
1686 stmmac_axi_setup: stmmac-axi-config {
1692 mtl_rx_setup: rx-queues-config {
1693 snps,rx-queues-to-use = <4>;
1694 snps,rx-sched-sp;
1697 snps,dcb-algorithm;
1698 snps,map-to-dma-channel = <0x0>;
1702 snps,dcb-algorithm;
1703 snps,map-to-dma-channel = <0x0>;
1707 snps,dcb-algorithm;
1708 snps,map-to-dma-channel = <0x0>;
1712 snps,dcb-algorithm;
1713 snps,map-to-dma-channel = <0x0>;
1717 mtl_tx_setup: tx-queues-config {
1718 snps,tx-queues-to-use = <4>;
1719 snps,tx-sched-wrr;
1722 snps,dcb-algorithm;
1728 snps,dcb-algorithm;
1734 snps,dcb-algorithm;
1740 snps,dcb-algorithm;
1748 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
1751 reg-names = "mac", "ippc";
1755 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
1757 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1762 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1763 mediatek,syscon-wakeup = <&pericfg 0x468 2>;
1764 wakeup-source;
1769 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
1777 clock-names = "source", "hclk", "source_cg", "crypto_clk";
1782 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
1789 clock-names = "source", "hclk", "source_cg";
1790 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1791 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1795 lvts_mcu: thermal-sensor@11278000 {
1796 compatible = "mediatek,mt8188-lvts-mcu";
1801 nvmem-cells = <&lvts_efuse_data1>;
1802 nvmem-cell-names = "lvts-calib-data-1";
1803 #thermal-sensor-cells = <1>;
1807 compatible = "mediatek,mt8188-i2c";
1811 clock-div = <1>;
1814 clock-names = "main", "dma";
1815 #address-cells = <1>;
1816 #size-cells = <0>;
1821 compatible = "mediatek,mt8188-i2c";
1825 clock-div = <1>;
1828 clock-names = "main", "dma";
1829 #address-cells = <1>;
1830 #size-cells = <0>;
1835 compatible = "mediatek,mt8188-i2c";
1839 clock-div = <1>;
1842 clock-names = "main", "dma";
1843 #address-cells = <1>;
1844 #size-cells = <0>;
1848 imp_iic_wrap_c: clock-controller@11283000 {
1849 compatible = "mediatek,mt8188-imp-iic-wrap-c";
1851 #clock-cells = <1>;
1855 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
1858 reg-names = "mac", "ippc";
1861 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>,
1863 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1868 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1873 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
1876 reg-names = "mac", "ippc";
1879 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>,
1881 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1886 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1887 mediatek,syscon-wakeup = <&pericfg 0x460 2>;
1888 wakeup-source;
1893 compatible = "mediatek,mt8188-pcie", "mediatek,mt8192-pcie";
1895 reg-names = "pcie-mac";
1897 bus-range = <0 0xff>;
1899 linux,pci-domain = <0>;
1900 #address-cells = <3>;
1901 #size-cells = <2>;
1909 clock-names = "pl_250m", "tl_26m", "tl_96m", "tl_32k",
1912 #interrupt-cells = <1>;
1914 interrupt-map = <0 0 0 1 &pcie_intc 0>,
1918 interrupt-map-mask = <0 0 0 7>;
1920 iommu-map = <0 &infra_iommu IFR_IOMMU_PORT_PCIE_0 0xffff>;
1921 iommu-map-mask = <0>;
1924 phy-names = "pcie-phy";
1926 power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_MAC_P0>;
1929 reset-names = "mac";
1933 pcie_intc: interrupt-controller {
1934 #address-cells = <0>;
1935 #interrupt-cells = <1>;
1936 interrupt-controller;
1941 compatible = "mediatek,mt8188-nor", "mediatek,mt8186-nor";
1946 clock-names = "spi", "sf", "axi";
1947 assigned-clocks = <&topckgen CLK_TOP_SPINOR>;
1949 #address-cells = <1>;
1950 #size-cells = <0>;
1954 pciephy: t-phy@11c20700 {
1955 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
1957 #address-cells = <1>;
1958 #size-cells = <1>;
1959 power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_PHY_TOP>;
1962 pcieport: pcie-phy@0 {
1965 clock-names = "ref";
1966 #phy-cells = <1>;
1970 mipi_tx_config0: dsi-phy@11c80000 {
1971 compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx";
1974 clock-output-names = "mipi_tx0_pll";
1975 #clock-cells = <0>;
1976 #phy-cells = <0>;
1980 mipi_tx_config1: dsi-phy@11c90000 {
1981 compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx";
1984 clock-output-names = "mipi_tx0_pll";
1985 #clock-cells = <0>;
1986 #phy-cells = <0>;
1991 compatible = "mediatek,mt8188-i2c";
1995 clock-div = <1>;
1998 clock-names = "main", "dma";
1999 #address-cells = <1>;
2000 #size-cells = <0>;
2005 compatible = "mediatek,mt8188-i2c";
2009 clock-div = <1>;
2012 clock-names = "main", "dma";
2013 #address-cells = <1>;
2014 #size-cells = <0>;
2018 imp_iic_wrap_w: clock-controller@11e02000 {
2019 compatible = "mediatek,mt8188-imp-iic-wrap-w";
2021 #clock-cells = <1>;
2024 u3phy0: t-phy@11e30000 {
2025 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
2026 #address-cells = <1>;
2027 #size-cells = <1>;
2031 u2port0: usb-phy@0 {
2035 clock-names = "ref", "da_ref";
2036 #phy-cells = <1>;
2040 u3phy1: t-phy@11e40000 {
2041 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
2042 #address-cells = <1>;
2043 #size-cells = <1>;
2047 u2port1: usb-phy@0 {
2051 clock-names = "ref", "da_ref";
2052 #phy-cells = <1>;
2055 u3port1: usb-phy@700 {
2059 clock-names = "ref", "da_ref";
2060 #phy-cells = <1>;
2064 u3phy2: t-phy@11e80000 {
2065 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
2066 #address-cells = <1>;
2067 #size-cells = <1>;
2071 u2port2: usb-phy@0 {
2075 clock-names = "ref", "da_ref";
2076 #phy-cells = <1>;
2081 compatible = "mediatek,mt8188-i2c";
2085 clock-div = <1>;
2088 clock-names = "main", "dma";
2089 #address-cells = <1>;
2090 #size-cells = <0>;
2095 compatible = "mediatek,mt8188-i2c";
2099 clock-div = <1>;
2102 clock-names = "main", "dma";
2103 #address-cells = <1>;
2104 #size-cells = <0>;
2108 imp_iic_wrap_en: clock-controller@11ec2000 {
2109 compatible = "mediatek,mt8188-imp-iic-wrap-en";
2111 #clock-cells = <1>;
2115 compatible = "mediatek,mt8188-efuse", "mediatek,efuse";
2117 #address-cells = <1>;
2118 #size-cells = <1>;
2120 dp_calib_data: dp-calib@1a0 {
2124 lvts_efuse_data1: lvts1-calib@1ac {
2128 socinfo-data1@7a0 {
2132 socinfo-data2@7e0 {
2138 compatible = "mediatek,mt8188-mali", "arm,mali-valhall-jm";
2145 interrupt-names = "job", "mmu", "gpu";
2146 operating-points-v2 = <&gpu_opp_table>;
2147 power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>,
2150 power-domain-names = "core0", "core1", "core2";
2151 #cooling-cells = <2>;
2155 mfgcfg: clock-controller@13fbf000 {
2156 compatible = "mediatek,mt8188-mfgcfg";
2158 #clock-cells = <1>;
2162 compatible = "mediatek,mt8188-vppsys0", "syscon";
2164 #clock-cells = <1>;
2168 compatible = "mediatek,mt8188-smi-common-vpp";
2172 clock-names = "apb", "smi";
2173 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
2177 compatible = "mediatek,mt8188-smi-larb";
2181 clock-names = "apb", "smi";
2182 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
2183 mediatek,larb-id = <SMI_L4_ID>;
2188 compatible = "mediatek,mt8188-iommu-vpp";
2191 clock-names = "bclk";
2193 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
2194 #iommu-cells = <1>;
2198 wpesys: clock-controller@14e00000 {
2199 compatible = "mediatek,mt8188-wpesys";
2201 #clock-cells = <1>;
2204 wpesys_vpp0: clock-controller@14e02000 {
2205 compatible = "mediatek,mt8188-wpesys-vpp0";
2207 #clock-cells = <1>;
2211 compatible = "mediatek,mt8188-smi-larb";
2215 clock-names = "apb", "smi";
2216 power-domains = <&spm MT8188_POWER_DOMAIN_WPE>;
2217 mediatek,larb-id = <SMI_L7_ID>;
2222 compatible = "mediatek,mt8188-vppsys1", "syscon";
2224 #clock-cells = <1>;
2228 compatible = "mediatek,mt8188-smi-larb";
2232 clock-names = "apb", "smi";
2233 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
2234 mediatek,larb-id = <SMI_L5_ID>;
2239 compatible = "mediatek,mt8188-smi-larb";
2243 clock-names = "apb", "smi";
2244 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
2245 mediatek,larb-id = <SMI_L6_ID>;
2249 imgsys: clock-controller@15000000 {
2250 compatible = "mediatek,mt8188-imgsys";
2252 #clock-cells = <1>;
2255 imgsys1_dip_top: clock-controller@15110000 {
2256 compatible = "mediatek,mt8188-imgsys1-dip-top";
2258 #clock-cells = <1>;
2261 imgsys1_dip_nr: clock-controller@15130000 {
2262 compatible = "mediatek,mt8188-imgsys1-dip-nr";
2264 #clock-cells = <1>;
2267 imgsys_wpe1: clock-controller@15220000 {
2268 compatible = "mediatek,mt8188-imgsys-wpe1";
2270 #clock-cells = <1>;
2273 ipesys: clock-controller@15330000 {
2274 compatible = "mediatek,mt8188-ipesys";
2276 #clock-cells = <1>;
2279 imgsys_wpe2: clock-controller@15520000 {
2280 compatible = "mediatek,mt8188-imgsys-wpe2";
2282 #clock-cells = <1>;
2285 imgsys_wpe3: clock-controller@15620000 {
2286 compatible = "mediatek,mt8188-imgsys-wpe3";
2288 #clock-cells = <1>;
2291 camsys: clock-controller@16000000 {
2292 compatible = "mediatek,mt8188-camsys";
2294 #clock-cells = <1>;
2297 camsys_rawa: clock-controller@1604f000 {
2298 compatible = "mediatek,mt8188-camsys-rawa";
2300 #clock-cells = <1>;
2303 camsys_yuva: clock-controller@1606f000 {
2304 compatible = "mediatek,mt8188-camsys-yuva";
2306 #clock-cells = <1>;
2309 camsys_rawb: clock-controller@1608f000 {
2310 compatible = "mediatek,mt8188-camsys-rawb";
2312 #clock-cells = <1>;
2315 camsys_yuvb: clock-controller@160af000 {
2316 compatible = "mediatek,mt8188-camsys-yuvb";
2318 #clock-cells = <1>;
2321 ccusys: clock-controller@17200000 {
2322 compatible = "mediatek,mt8188-ccusys";
2324 #clock-cells = <1>;
2327 video_decoder: video-decoder@18000000 {
2328 compatible = "mediatek,mt8188-vcodec-dec";
2332 #address-cells = <2>;
2333 #size-cells = <2>;
2336 video-codec@10000 {
2337 compatible = "mediatek,mtk-vcodec-lat";
2339 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2340 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
2345 clock-names = "sel", "vdec", "lat", "top";
2356 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>;
2359 video-codec@25000 {
2360 compatible = "mediatek,mtk-vcodec-core";
2362 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2363 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
2368 clock-names = "sel", "vdec", "lat", "top";
2381 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC1>;
2386 compatible = "mediatek,mt8188-smi-larb";
2390 clock-names = "apb", "smi";
2391 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>;
2392 mediatek,larb-id = <SMI_L23_ID>;
2396 vdecsys_soc: clock-controller@1800f000 {
2397 compatible = "mediatek,mt8188-vdecsys-soc";
2399 #clock-cells = <1>;
2403 compatible = "mediatek,mt8188-smi-larb";
2407 clock-names = "apb", "smi";
2408 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC1>;
2409 mediatek,larb-id = <SMI_L21_ID>;
2413 vdecsys: clock-controller@1802f000 {
2414 compatible = "mediatek,mt8188-vdecsys";
2416 #clock-cells = <1>;
2419 vencsys: clock-controller@1a000000 {
2420 compatible = "mediatek,mt8188-vencsys";
2422 #clock-cells = <1>;
2426 compatible = "mediatek,mt8188-smi-larb";
2430 clock-names = "apb", "smi";
2431 power-domains = <&spm MT8188_POWER_DOMAIN_VENC>;
2432 mediatek,larb-id = <SMI_L19_ID>;
2436 video_encoder: video-encoder@1a020000 {
2437 compatible = "mediatek,mt8188-vcodec-enc";
2439 #address-cells = <2>;
2440 #size-cells = <2>;
2441 assigned-clocks = <&topckgen CLK_TOP_VENC>;
2442 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2444 clock-names = "venc_sel";
2457 power-domains = <&spm MT8188_POWER_DOMAIN_VENC>;
2461 jpeg_encoder: jpeg-encoder@1a030000 {
2462 compatible = "mediatek,mt8188-jpgenc", "mediatek,mtk-jpgenc";
2465 clock-names = "jpgenc";
2471 power-domains = <&spm MT8188_POWER_DOMAIN_VENC>;
2474 jpeg_decoder: jpeg-decoder@1a040000 {
2475 compatible = "mediatek,mt8188-jpgdec", "mediatek,mt2701-jpgdec";
2479 clock-names = "jpgdec-smi", "jpgdec";
2487 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>;
2491 compatible = "mediatek,mt8188-disp-ovl", "mediatek,mt8183-disp-ovl";
2496 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2497 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
2501 compatible = "mediatek,mt8188-disp-rdma", "mediatek,mt8195-disp-rdma";
2506 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2507 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
2511 compatible = "mediatek,mt8188-disp-color", "mediatek,mt8173-disp-color";
2515 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2516 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
2520 compatible = "mediatek,mt8188-disp-ccorr", "mediatek,mt8192-disp-ccorr";
2524 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2525 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
2529 compatible = "mediatek,mt8188-disp-aal", "mediatek,mt8183-disp-aal";
2533 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2534 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
2538 compatible = "mediatek,mt8188-disp-gamma", "mediatek,mt8195-disp-gamma";
2542 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2543 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
2547 compatible = "mediatek,mt8188-disp-dither", "mediatek,mt8183-disp-dither";
2551 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2552 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
2556 compatible = "mediatek,mt8188-dsi";
2561 clock-names = "engine", "digital", "hs";
2564 phy-names = "dphy";
2565 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2571 compatible = "mediatek,mt8188-dsi";
2576 clock-names = "engine", "digital", "hs";
2579 phy-names = "dphy";
2580 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2585 dp_intf0: dp-intf@1c015000 {
2586 compatible = "mediatek,mt8188-dp-intf";
2591 clock-names = "pixel", "engine", "pll";
2593 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2598 compatible = "mediatek,mt8188-disp-mutex";
2602 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2603 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>;
2604 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
2608 compatible = "mediatek,mt8188-disp-postmask",
2609 "mediatek,mt8192-disp-postmask";
2613 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2614 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>;
2618 compatible = "mediatek,mt8188-vdosys0", "syscon";
2620 #clock-cells = <1>;
2621 #reset-cells = <1>;
2623 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xd000 0x1000>;
2627 compatible = "mediatek,mt8188-smi-larb";
2631 clock-names = "apb", "smi";
2632 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2633 mediatek,larb-id = <SMI_L0_ID>;
2638 compatible = "mediatek,mt8188-smi-larb";
2642 clock-names = "apb", "smi";
2643 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2644 mediatek,larb-id = <SMI_L1_ID>;
2649 compatible = "mediatek,mt8188-smi-common-vdo";
2653 clock-names = "apb", "smi";
2654 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2658 compatible = "mediatek,mt8188-iommu-vdo";
2661 clock-names = "bclk";
2663 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2664 #iommu-cells = <1>;
2669 compatible = "mediatek,mt8188-vdosys1", "syscon";
2671 #clock-cells = <1>;
2672 #reset-cells = <1>;
2674 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0 0x1000>;
2678 compatible = "mediatek,mt8188-disp-mutex";
2682 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2683 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>;
2684 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
2688 compatible = "mediatek,mt8188-smi-larb";
2692 clock-names = "apb", "smi";
2693 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2694 mediatek,larb-id = <SMI_L2_ID>;
2699 compatible = "mediatek,mt8188-smi-larb";
2703 clock-names = "apb", "smi";
2704 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2705 mediatek,larb-id = <SMI_L3_ID>;
2710 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
2715 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2716 #dma-cells = <1>;
2717 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
2721 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
2726 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2727 #dma-cells = <1>;
2728 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>;
2732 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
2737 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2738 #dma-cells = <1>;
2739 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>;
2743 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
2748 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2749 #dma-cells = <1>;
2750 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>;
2754 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
2759 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2760 #dma-cells = <1>;
2761 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>;
2765 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
2770 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2771 #dma-cells = <1>;
2772 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>;
2776 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
2781 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2782 #dma-cells = <1>;
2783 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>;
2787 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
2792 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2793 #dma-cells = <1>;
2794 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>;
2798 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";
2802 clock-names = "merge", "merge_async";
2804 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2806 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>;
2807 mediatek,merge-mute;
2811 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";
2815 clock-names = "merge", "merge_async";
2817 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2819 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>;
2820 mediatek,merge-mute;
2824 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";
2828 clock-names = "merge", "merge_async";
2830 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2832 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>;
2833 mediatek,merge-mute;
2837 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";
2841 clock-names = "merge", "merge_async";
2843 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2845 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>;
2846 mediatek,merge-mute;
2850 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";
2854 clock-names = "merge", "merge_async";
2856 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2858 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>;
2859 mediatek,merge-fifo-en;
2862 dp_intf1: dp-intf@1c113000 {
2863 compatible = "mediatek,mt8188-dp-intf";
2868 clock-names = "pixel", "engine", "pll";
2870 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2875 compatible = "mediatek,mt8188-disp-ethdr", "mediatek,mt8195-disp-ethdr";
2883 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
2899 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
2906 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2913 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
2923 compatible = "mediatek,mt8188-disp-padding";
2926 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2927 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>;
2931 compatible = "mediatek,mt8188-disp-padding";
2934 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2935 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xe000 0x1000>;
2939 compatible = "mediatek,mt8188-disp-padding";
2942 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2943 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xf000 0x1000>;
2947 compatible = "mediatek,mt8188-disp-padding";
2950 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2951 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x0000 0x1000>;
2955 compatible = "mediatek,mt8188-disp-padding";
2958 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2959 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x1000 0x1000>;
2963 compatible = "mediatek,mt8188-disp-padding";
2966 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2967 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x2000 0x1000>;
2971 compatible = "mediatek,mt8188-disp-padding";
2974 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2975 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x3000 0x1000>;
2979 compatible = "mediatek,mt8188-disp-padding";
2982 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2983 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x4000 0x1000>;
2986 edp_tx: edp-tx@1c500000 {
2987 compatible = "mediatek,mt8188-edp-tx";
2990 nvmem-cells = <&dp_calib_data>;
2991 nvmem-cell-names = "dp_calibration_data";
2992 power-domains = <&spm MT8188_POWER_DOMAIN_EDP_TX>;
2993 max-linkrate-mhz = <8100>;
2997 dp_tx: dp-tx@1c600000 {
2998 compatible = "mediatek,mt8188-dp-tx";
3001 nvmem-cells = <&dp_calib_data>;
3002 nvmem-cell-names = "dp_calibration_data";
3003 power-domains = <&spm MT8188_POWER_DOMAIN_DP_TX>;
3004 max-linkrate-mhz = <5400>;