Lines Matching +full:mt8195 +full:- +full:camsys_yuvb
1 // SPDX-License-Identifier: GPL-2.0+
7 /dts-v1/;
8 #include <dt-bindings/clock/mediatek,mt8188-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/mailbox/mediatek,mt8188-gce.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
14 #include <dt-bindings/power/mediatek,mt8188-power.h>
15 #include <dt-bindings/reset/mt8188-resets.h>
16 #include <dt-bindings/thermal/thermal.h>
17 #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
21 interrupt-parent = <&gic>;
22 #address-cells = <2>;
23 #size-cells = <2>;
26 #address-cells = <1>;
27 #size-cells = <0>;
31 compatible = "arm,cortex-a55";
33 enable-method = "psci";
34 clock-frequency = <2000000000>;
35 capacity-dmips-mhz = <282>;
36 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
37 i-cache-size = <32768>;
38 i-cache-line-size = <64>;
39 i-cache-sets = <128>;
40 d-cache-size = <32768>;
41 d-cache-line-size = <64>;
42 d-cache-sets = <128>;
43 next-level-cache = <&l2_0>;
44 #cooling-cells = <2>;
49 compatible = "arm,cortex-a55";
51 enable-method = "psci";
52 clock-frequency = <2000000000>;
53 capacity-dmips-mhz = <282>;
54 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
55 i-cache-size = <32768>;
56 i-cache-line-size = <64>;
57 i-cache-sets = <128>;
58 d-cache-size = <32768>;
59 d-cache-line-size = <64>;
60 d-cache-sets = <128>;
61 next-level-cache = <&l2_0>;
62 #cooling-cells = <2>;
67 compatible = "arm,cortex-a55";
69 enable-method = "psci";
70 clock-frequency = <2000000000>;
71 capacity-dmips-mhz = <282>;
72 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
73 i-cache-size = <32768>;
74 i-cache-line-size = <64>;
75 i-cache-sets = <128>;
76 d-cache-size = <32768>;
77 d-cache-line-size = <64>;
78 d-cache-sets = <128>;
79 next-level-cache = <&l2_0>;
80 #cooling-cells = <2>;
85 compatible = "arm,cortex-a55";
87 enable-method = "psci";
88 clock-frequency = <2000000000>;
89 capacity-dmips-mhz = <282>;
90 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
91 i-cache-size = <32768>;
92 i-cache-line-size = <64>;
93 i-cache-sets = <128>;
94 d-cache-size = <32768>;
95 d-cache-line-size = <64>;
96 d-cache-sets = <128>;
97 next-level-cache = <&l2_0>;
98 #cooling-cells = <2>;
103 compatible = "arm,cortex-a55";
105 enable-method = "psci";
106 clock-frequency = <2000000000>;
107 capacity-dmips-mhz = <282>;
108 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
109 i-cache-size = <32768>;
110 i-cache-line-size = <64>;
111 i-cache-sets = <128>;
112 d-cache-size = <32768>;
113 d-cache-line-size = <64>;
114 d-cache-sets = <128>;
115 next-level-cache = <&l2_0>;
116 #cooling-cells = <2>;
121 compatible = "arm,cortex-a55";
123 enable-method = "psci";
124 clock-frequency = <2000000000>;
125 capacity-dmips-mhz = <282>;
126 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
127 i-cache-size = <32768>;
128 i-cache-line-size = <64>;
129 i-cache-sets = <128>;
130 d-cache-size = <32768>;
131 d-cache-line-size = <64>;
132 d-cache-sets = <128>;
133 next-level-cache = <&l2_0>;
134 #cooling-cells = <2>;
139 compatible = "arm,cortex-a78";
141 enable-method = "psci";
142 clock-frequency = <2600000000>;
143 capacity-dmips-mhz = <1024>;
144 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
145 i-cache-size = <65536>;
146 i-cache-line-size = <64>;
147 i-cache-sets = <256>;
148 d-cache-size = <65536>;
149 d-cache-line-size = <64>;
150 d-cache-sets = <256>;
151 next-level-cache = <&l2_1>;
152 #cooling-cells = <2>;
157 compatible = "arm,cortex-a78";
159 enable-method = "psci";
160 clock-frequency = <2600000000>;
161 capacity-dmips-mhz = <1024>;
162 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
163 i-cache-size = <65536>;
164 i-cache-line-size = <64>;
165 i-cache-sets = <256>;
166 d-cache-size = <65536>;
167 d-cache-line-size = <64>;
168 d-cache-sets = <256>;
169 next-level-cache = <&l2_1>;
170 #cooling-cells = <2>;
173 cpu-map {
209 idle-states {
210 entry-method = "psci";
212 cpu_off_l: cpu-off-l {
213 compatible = "arm,idle-state";
214 arm,psci-suspend-param = <0x00010000>;
215 local-timer-stop;
216 entry-latency-us = <50>;
217 exit-latency-us = <95>;
218 min-residency-us = <580>;
221 cpu_off_b: cpu-off-b {
222 compatible = "arm,idle-state";
223 arm,psci-suspend-param = <0x00010000>;
224 local-timer-stop;
225 entry-latency-us = <45>;
226 exit-latency-us = <140>;
227 min-residency-us = <740>;
230 cluster_off_l: cluster-off-l {
231 compatible = "arm,idle-state";
232 arm,psci-suspend-param = <0x01010010>;
233 local-timer-stop;
234 entry-latency-us = <55>;
235 exit-latency-us = <155>;
236 min-residency-us = <840>;
239 cluster_off_b: cluster-off-b {
240 compatible = "arm,idle-state";
241 arm,psci-suspend-param = <0x01010010>;
242 local-timer-stop;
243 entry-latency-us = <50>;
244 exit-latency-us = <200>;
245 min-residency-us = <1000>;
249 l2_0: l2-cache0 {
251 cache-level = <2>;
252 cache-size = <131072>;
253 cache-line-size = <64>;
254 cache-sets = <512>;
255 next-level-cache = <&l3_0>;
256 cache-unified;
259 l2_1: l2-cache1 {
261 cache-level = <2>;
262 cache-size = <262144>;
263 cache-line-size = <64>;
264 cache-sets = <512>;
265 next-level-cache = <&l3_0>;
266 cache-unified;
269 l3_0: l3-cache {
271 cache-level = <3>;
272 cache-size = <2097152>;
273 cache-line-size = <64>;
274 cache-sets = <2048>;
275 cache-unified;
279 clk13m: oscillator-13m {
280 compatible = "fixed-clock";
281 #clock-cells = <0>;
282 clock-frequency = <13000000>;
283 clock-output-names = "clk13m";
286 clk26m: oscillator-26m {
287 compatible = "fixed-clock";
288 #clock-cells = <0>;
289 clock-frequency = <26000000>;
290 clock-output-names = "clk26m";
293 clk32k: oscillator-32k {
294 compatible = "fixed-clock";
295 #clock-cells = <0>;
296 clock-frequency = <32768>;
297 clock-output-names = "clk32k";
300 gpu_opp_table: opp-table-gpu {
301 compatible = "operating-points-v2";
302 opp-shared;
304 opp-390000000 {
305 opp-hz = /bits/ 64 <390000000>;
306 opp-microvolt = <575000>;
307 opp-supported-hw = <0xff>;
309 opp-431000000 {
310 opp-hz = /bits/ 64 <431000000>;
311 opp-microvolt = <587500>;
312 opp-supported-hw = <0xff>;
314 opp-473000000 {
315 opp-hz = /bits/ 64 <473000000>;
316 opp-microvolt = <600000>;
317 opp-supported-hw = <0xff>;
319 opp-515000000 {
320 opp-hz = /bits/ 64 <515000000>;
321 opp-microvolt = <612500>;
322 opp-supported-hw = <0xff>;
324 opp-556000000 {
325 opp-hz = /bits/ 64 <556000000>;
326 opp-microvolt = <625000>;
327 opp-supported-hw = <0xff>;
329 opp-598000000 {
330 opp-hz = /bits/ 64 <598000000>;
331 opp-microvolt = <637500>;
332 opp-supported-hw = <0xff>;
334 opp-640000000 {
335 opp-hz = /bits/ 64 <640000000>;
336 opp-microvolt = <650000>;
337 opp-supported-hw = <0xff>;
339 opp-670000000 {
340 opp-hz = /bits/ 64 <670000000>;
341 opp-microvolt = <662500>;
342 opp-supported-hw = <0xff>;
344 opp-700000000 {
345 opp-hz = /bits/ 64 <700000000>;
346 opp-microvolt = <675000>;
347 opp-supported-hw = <0xff>;
349 opp-730000000 {
350 opp-hz = /bits/ 64 <730000000>;
351 opp-microvolt = <687500>;
352 opp-supported-hw = <0xff>;
354 opp-760000000 {
355 opp-hz = /bits/ 64 <760000000>;
356 opp-microvolt = <700000>;
357 opp-supported-hw = <0xff>;
359 opp-790000000 {
360 opp-hz = /bits/ 64 <790000000>;
361 opp-microvolt = <712500>;
362 opp-supported-hw = <0xff>;
364 opp-835000000 {
365 opp-hz = /bits/ 64 <835000000>;
366 opp-microvolt = <731250>;
367 opp-supported-hw = <0xff>;
369 opp-880000000 {
370 opp-hz = /bits/ 64 <880000000>;
371 opp-microvolt = <750000>;
372 opp-supported-hw = <0xff>;
374 opp-915000000 {
375 opp-hz = /bits/ 64 <915000000>;
376 opp-microvolt = <775000>;
377 opp-supported-hw = <0x8f>;
379 opp-915000000-5 {
380 opp-hz = /bits/ 64 <915000000>;
381 opp-microvolt = <762500>;
382 opp-supported-hw = <0x30>;
384 opp-915000000-6 {
385 opp-hz = /bits/ 64 <915000000>;
386 opp-microvolt = <750000>;
387 opp-supported-hw = <0x70>;
389 opp-950000000 {
390 opp-hz = /bits/ 64 <950000000>;
391 opp-microvolt = <800000>;
392 opp-supported-hw = <0x8f>;
394 opp-950000000-5 {
395 opp-hz = /bits/ 64 <950000000>;
396 opp-microvolt = <775000>;
397 opp-supported-hw = <0x30>;
399 opp-950000000-6 {
400 opp-hz = /bits/ 64 <950000000>;
401 opp-microvolt = <750000>;
402 opp-supported-hw = <0x70>;
406 pmu-a55 {
407 compatible = "arm,cortex-a55-pmu";
408 interrupt-parent = <&gic>;
412 pmu-a78 {
413 compatible = "arm,cortex-a78-pmu";
414 interrupt-parent = <&gic>;
419 compatible = "arm,psci-1.0";
423 thermal_zones: thermal-zones {
424 cpu-little0-thermal {
425 polling-delay = <1000>;
426 polling-delay-passive = <150>;
427 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU0>;
430 cpu_little0_alert0: trip-alert0 {
436 cpu_little0_alert1: trip-alert1 {
442 cpu_little0_crit: trip-crit {
449 cooling-maps {
452 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
462 cpu-little1-thermal {
463 polling-delay = <1000>;
464 polling-delay-passive = <150>;
465 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU1>;
468 cpu_little1_alert0: trip-alert0 {
474 cpu_little1_alert1: trip-alert1 {
480 cpu_little1_crit: trip-crit {
487 cooling-maps {
490 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
500 cpu-little2-thermal {
501 polling-delay = <1000>;
502 polling-delay-passive = <150>;
503 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU2>;
506 cpu_little2_alert0: trip-alert0 {
512 cpu_little2_alert1: trip-alert1 {
518 cpu_little2_crit: trip-crit {
525 cooling-maps {
528 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
538 cpu-little3-thermal {
539 polling-delay = <1000>;
540 polling-delay-passive = <150>;
541 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU3>;
544 cpu_little3_alert0: trip-alert0 {
550 cpu_little3_alert1: trip-alert1 {
556 cpu_little3_crit: trip-crit {
563 cooling-maps {
566 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
576 cpu-big0-thermal {
577 polling-delay = <1000>;
578 polling-delay-passive = <100>;
579 thermal-sensors = <&lvts_mcu MT8188_MCU_BIG_CPU0>;
582 cpu_big0_alert0: trip-alert0 {
588 cpu_big0_alert1: trip-alert1 {
594 cpu_big0_crit: trip-crit {
601 cooling-maps {
604 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
610 cpu-big1-thermal {
611 polling-delay = <1000>;
612 polling-delay-passive = <100>;
613 thermal-sensors = <&lvts_mcu MT8188_MCU_BIG_CPU1>;
616 cpu_big1_alert0: trip-alert0 {
622 cpu_big1_alert1: trip-alert1 {
628 cpu_big1_crit: trip-crit {
635 cooling-maps {
638 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
644 apu-thermal {
645 polling-delay = <1000>;
646 polling-delay-passive = <250>;
647 thermal-sensors = <&lvts_ap MT8188_AP_APU>;
650 apu_alert0: trip-alert0 {
656 apu_alert1: trip-alert1 {
662 apu_crit: trip-crit {
670 gpu-thermal {
671 polling-delay = <1000>;
672 polling-delay-passive = <250>;
673 thermal-sensors = <&lvts_ap MT8188_AP_GPU0>;
676 gpu_alert0: trip-alert0 {
682 gpu_alert1: trip-alert1 {
688 gpu_crit: trip-crit {
695 cooling-maps {
698 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
703 gpu1-thermal {
704 polling-delay = <1000>;
705 polling-delay-passive = <250>;
706 thermal-sensors = <&lvts_ap MT8188_AP_GPU1>;
709 gpu1_alert0: trip-alert0 {
715 gpu1_alert1: trip-alert1 {
721 gpu1_crit: trip-crit {
728 cooling-maps {
731 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
736 adsp-thermal {
737 polling-delay = <1000>;
738 polling-delay-passive = <250>;
739 thermal-sensors = <&lvts_ap MT8188_AP_ADSP>;
742 soc_alert0: trip-alert0 {
748 soc_alert1: trip-alert1 {
754 soc_crit: trip-crit {
762 vdo-thermal {
763 polling-delay = <1000>;
764 polling-delay-passive = <250>;
765 thermal-sensors = <&lvts_ap MT8188_AP_VDO>;
768 soc1_alert0: trip-alert0 {
774 soc1_alert1: trip-alert1 {
780 soc1_crit: trip-crit {
788 infra-thermal {
789 polling-delay = <1000>;
790 polling-delay-passive = <250>;
791 thermal-sensors = <&lvts_ap MT8188_AP_INFRA>;
794 soc2_alert0: trip-alert0 {
800 soc2_alert1: trip-alert1 {
806 soc2_crit: trip-crit {
814 cam1-thermal {
815 polling-delay = <1000>;
816 polling-delay-passive = <250>;
817 thermal-sensors = <&lvts_ap MT8188_AP_CAM1>;
820 cam1_alert0: trip-alert0 {
826 cam1_alert1: trip-alert1 {
832 cam1_crit: trip-crit {
840 cam2-thermal {
841 polling-delay = <1000>;
842 polling-delay-passive = <250>;
843 thermal-sensors = <&lvts_ap MT8188_AP_CAM2>;
846 cam2_alert0: trip-alert0 {
852 cam2_alert1: trip-alert1 {
858 cam2_crit: trip-crit {
868 compatible = "arm,armv8-timer";
869 interrupt-parent = <&gic>;
874 clock-frequency = <13000000>;
878 #address-cells = <2>;
879 #size-cells = <2>;
880 compatible = "simple-bus";
883 gic: interrupt-controller@c000000 {
884 compatible = "arm,gic-v3";
885 #interrupt-cells = <4>;
886 #redistributor-regions = <1>;
887 interrupt-parent = <&gic>;
888 interrupt-controller;
893 ppi-partitions {
894 ppi_cluster0: interrupt-partition-0 {
898 ppi_cluster1: interrupt-partition-1 {
905 compatible = "mediatek,mt8188-topckgen", "syscon";
907 #clock-cells = <1>;
911 compatible = "mediatek,mt8188-infracfg-ao", "syscon";
913 #clock-cells = <1>;
914 #reset-cells = <1>;
918 compatible = "mediatek,mt8188-pericfg", "syscon";
920 #clock-cells = <1>;
924 compatible = "mediatek,mt8188-pinctrl";
931 reg-names = "iocfg0", "iocfg_rm", "iocfg_lt",
933 gpio-controller;
934 #gpio-cells = <2>;
935 gpio-ranges = <&pio 0 0 176>;
936 interrupt-controller;
938 #interrupt-cells = <2>;
942 compatible = "mediatek,mt8188-scpsys", "syscon", "simple-mfd";
946 spm: power-controller {
947 compatible = "mediatek,mt8188-power-controller";
948 #address-cells = <1>;
949 #size-cells = <0>;
950 #power-domain-cells = <1>;
953 mfg0: power-domain@MT8188_POWER_DOMAIN_MFG0 {
955 #address-cells = <1>;
956 #size-cells = <0>;
957 #power-domain-cells = <1>;
959 power-domain@MT8188_POWER_DOMAIN_MFG1 {
963 clock-names = "mfg", "alt";
965 #address-cells = <1>;
966 #size-cells = <0>;
967 #power-domain-cells = <1>;
969 power-domain@MT8188_POWER_DOMAIN_MFG2 {
971 #power-domain-cells = <0>;
974 power-domain@MT8188_POWER_DOMAIN_MFG3 {
976 #power-domain-cells = <0>;
979 power-domain@MT8188_POWER_DOMAIN_MFG4 {
981 #power-domain-cells = <0>;
986 power-domain@MT8188_POWER_DOMAIN_VPPSYS0 {
1016 clock-names = "top", "cam", "ccu", "img", "venc",
1018 "ss-sram-cmn", "ss-sram-v0l0", "ss-sram-v0l1",
1019 "ss-sram-ve0", "ss-sram-ve1", "ss-sram-ifa",
1020 "ss-sram-cam", "ss-sram-v1l5", "ss-sram-v1l6",
1021 "ss-sram-rdr", "ss-iommu", "ss-imgcam",
1022 "ss-emi", "ss-subcmn-rdr", "ss-rsi",
1023 "ss-cmn-l4", "ss-vdec1", "ss-wpe",
1024 "ss-cvdo-ve1";
1026 #address-cells = <1>;
1027 #size-cells = <0>;
1028 #power-domain-cells = <1>;
1030 power-domain@MT8188_POWER_DOMAIN_VDOSYS0 {
1041 clock-names = "cfgck", "cfgxo", "ss-gals",
1042 "ss-cmn", "ss-emi", "ss-iommu",
1043 "ss-larb", "ss-rsi", "ss-bus";
1045 #address-cells = <1>;
1046 #size-cells = <0>;
1047 #power-domain-cells = <1>;
1049 power-domain@MT8188_POWER_DOMAIN_VPPSYS1 {
1057 clock-names = "cfgck", "cfgxo",
1058 "ss-vpp1-g5", "ss-vpp1-g6",
1059 "ss-vpp1-l5", "ss-vpp1-l6";
1061 #power-domain-cells = <0>;
1064 power-domain@MT8188_POWER_DOMAIN_VDEC1 {
1067 clock-names = "ss-vdec";
1069 #power-domain-cells = <0>;
1072 power-domain@MT8188_POWER_DOMAIN_VDEC0 {
1075 clock-names = "ss-vdec";
1077 #power-domain-cells = <0>;
1080 cam_vcore: power-domain@MT8188_POWER_DOMAIN_CAM_VCORE {
1086 clock-names = "cam", "ccu", "bus", "cfgck";
1088 #address-cells = <1>;
1089 #size-cells = <0>;
1090 #power-domain-cells = <1>;
1092 power-domain@MT8188_POWER_DOMAIN_CAM_MAIN {
1099 clock-names= "ss-cam-l13", "ss-cam-l14",
1100 "ss-cam-mm0", "ss-cam-mm1",
1101 "ss-camsys";
1103 #address-cells = <1>;
1104 #size-cells = <0>;
1105 #power-domain-cells = <1>;
1107 power-domain@MT8188_POWER_DOMAIN_CAM_SUBB {
1111 <&camsys_yuvb CLK_CAM_YUVB_LARBX>;
1112 clock-names = "ss-camb-sub",
1113 "ss-camb-raw",
1114 "ss-camb-yuv";
1115 #power-domain-cells = <0>;
1118 power-domain@MT8188_POWER_DOMAIN_CAM_SUBA {
1123 clock-names = "ss-cama-sub",
1124 "ss-cama-raw",
1125 "ss-cama-yuv";
1126 #power-domain-cells = <0>;
1131 power-domain@MT8188_POWER_DOMAIN_VDOSYS1 {
1138 clock-names = "cfgck", "cfgxo", "ss-larb2",
1139 "ss-larb3", "ss-gals";
1141 #address-cells = <1>;
1142 #size-cells = <0>;
1143 #power-domain-cells = <1>;
1145 power-domain@MT8188_POWER_DOMAIN_HDMI_TX {
1149 clock-names = "bus", "hdcp";
1151 #power-domain-cells = <0>;
1154 power-domain@MT8188_POWER_DOMAIN_DP_TX {
1157 #power-domain-cells = <0>;
1160 power-domain@MT8188_POWER_DOMAIN_EDP_TX {
1163 #power-domain-cells = <0>;
1167 power-domain@MT8188_POWER_DOMAIN_VENC {
1173 clock-names = "ss-ve1-larb", "ss-ve1-core",
1174 "ss-ve1-gals", "ss-ve1-sram";
1176 #power-domain-cells = <0>;
1179 power-domain@MT8188_POWER_DOMAIN_WPE {
1183 clock-names = "ss-wpe-l7", "ss-wpe-l7pce";
1185 #power-domain-cells = <0>;
1190 power-domain@MT8188_POWER_DOMAIN_PEXTP_MAC_P0 {
1194 clock-names = "ss-pextp-fmem";
1195 #power-domain-cells = <0>;
1198 power-domain@MT8188_POWER_DOMAIN_CSIRX_TOP {
1202 clock-names = "seninf0", "seninf1";
1203 #power-domain-cells = <0>;
1206 power-domain@MT8188_POWER_DOMAIN_PEXTP_PHY_TOP {
1208 #power-domain-cells = <0>;
1211 power-domain@MT8188_POWER_DOMAIN_ADSP_AO {
1215 clock-names = "bus", "main";
1217 #address-cells = <1>;
1218 #size-cells = <0>;
1219 #power-domain-cells = <1>;
1221 power-domain@MT8188_POWER_DOMAIN_ADSP_INFRA {
1224 #address-cells = <1>;
1225 #size-cells = <0>;
1226 #power-domain-cells = <1>;
1228 power-domain@MT8188_POWER_DOMAIN_AUDIO_ASRC {
1231 clock-names = "asm";
1233 #power-domain-cells = <0>;
1236 power-domain@MT8188_POWER_DOMAIN_AUDIO {
1241 clock-names = "a1sys", "intbus", "adspck";
1243 #power-domain-cells = <0>;
1246 power-domain@MT8188_POWER_DOMAIN_ADSP {
1249 #power-domain-cells = <0>;
1254 power-domain@MT8188_POWER_DOMAIN_ETHER {
1257 clock-names = "ethermac";
1259 #power-domain-cells = <0>;
1265 compatible = "mediatek,mt8188-wdt";
1267 mediatek,disable-extrst;
1268 #reset-cells = <1>;
1272 compatible = "mediatek,mt8188-apmixedsys", "syscon";
1274 #clock-cells = <1>;
1278 compatible = "mediatek,mt8188-timer", "mediatek,mt6765-timer";
1285 compatible = "mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap", "syscon";
1287 reg-names = "pwrap";
1291 clock-names = "spi", "wrap";
1295 compatible = "mediatek,mt8188-gce";
1298 #mbox-cells = <2>;
1303 compatible = "mediatek,mt8188-gce";
1306 #mbox-cells = <2>;
1311 compatible = "mediatek,mt8188-scp";
1314 reg-names = "sram", "cfg";
1318 adsp_audio26m: clock-controller@10b91100 {
1319 compatible = "mediatek,mt8188-adsp-audio26m";
1321 #clock-cells = <1>;
1325 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
1329 clock-names = "baud", "bus";
1334 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
1338 clock-names = "baud", "bus";
1343 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
1347 clock-names = "baud", "bus";
1352 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
1356 clock-names = "baud", "bus";
1361 compatible = "mediatek,mt8188-auxadc", "mediatek,mt8173-auxadc";
1364 clock-names = "main";
1365 #io-channel-cells = <1>;
1370 compatible = "mediatek,mt8188-pericfg-ao", "syscon";
1372 #clock-cells = <1>;
1376 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1377 #address-cells = <1>;
1378 #size-cells = <0>;
1384 clock-names = "parent-clk", "sel-clk", "spi-clk";
1388 lvts_ap: thermal-sensor@1100b000 {
1389 compatible = "mediatek,mt8188-lvts-ap";
1394 nvmem-cells = <&lvts_efuse_data1>;
1395 nvmem-cell-names = "lvts-calib-data-1";
1396 #thermal-sensor-cells = <1>;
1400 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1401 #address-cells = <1>;
1402 #size-cells = <0>;
1408 clock-names = "parent-clk", "sel-clk", "spi-clk";
1413 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1414 #address-cells = <1>;
1415 #size-cells = <0>;
1421 clock-names = "parent-clk", "sel-clk", "spi-clk";
1426 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1427 #address-cells = <1>;
1428 #size-cells = <0>;
1434 clock-names = "parent-clk", "sel-clk", "spi-clk";
1439 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1440 #address-cells = <1>;
1441 #size-cells = <0>;
1447 clock-names = "parent-clk", "sel-clk", "spi-clk";
1452 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1453 #address-cells = <1>;
1454 #size-cells = <0>;
1460 clock-names = "parent-clk", "sel-clk", "spi-clk";
1465 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
1468 reg-names = "mac", "ippc";
1472 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
1474 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1479 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1480 mediatek,syscon-wakeup = <&pericfg 0x468 2>;
1481 wakeup-source;
1486 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
1494 clock-names = "source", "hclk", "source_cg", "crypto_clk";
1499 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
1506 clock-names = "source", "hclk", "source_cg";
1507 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1508 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1512 lvts_mcu: thermal-sensor@11278000 {
1513 compatible = "mediatek,mt8188-lvts-mcu";
1518 nvmem-cells = <&lvts_efuse_data1>;
1519 nvmem-cell-names = "lvts-calib-data-1";
1520 #thermal-sensor-cells = <1>;
1524 compatible = "mediatek,mt8188-i2c";
1528 clock-div = <1>;
1531 clock-names = "main", "dma";
1532 #address-cells = <1>;
1533 #size-cells = <0>;
1538 compatible = "mediatek,mt8188-i2c";
1542 clock-div = <1>;
1545 clock-names = "main", "dma";
1546 #address-cells = <1>;
1547 #size-cells = <0>;
1552 compatible = "mediatek,mt8188-i2c";
1556 clock-div = <1>;
1559 clock-names = "main", "dma";
1560 #address-cells = <1>;
1561 #size-cells = <0>;
1565 imp_iic_wrap_c: clock-controller@11283000 {
1566 compatible = "mediatek,mt8188-imp-iic-wrap-c";
1568 #clock-cells = <1>;
1572 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
1575 reg-names = "mac", "ippc";
1578 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>,
1580 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1585 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1590 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
1593 reg-names = "mac", "ippc";
1596 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>,
1598 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1603 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1604 mediatek,syscon-wakeup = <&pericfg 0x460 2>;
1605 wakeup-source;
1610 compatible = "mediatek,mt8188-nor", "mediatek,mt8186-nor";
1615 clock-names = "spi", "sf", "axi";
1616 assigned-clocks = <&topckgen CLK_TOP_SPINOR>;
1622 compatible = "mediatek,mt8188-i2c";
1626 clock-div = <1>;
1629 clock-names = "main", "dma";
1630 #address-cells = <1>;
1631 #size-cells = <0>;
1636 compatible = "mediatek,mt8188-i2c";
1640 clock-div = <1>;
1643 clock-names = "main", "dma";
1644 #address-cells = <1>;
1645 #size-cells = <0>;
1649 imp_iic_wrap_w: clock-controller@11e02000 {
1650 compatible = "mediatek,mt8188-imp-iic-wrap-w";
1652 #clock-cells = <1>;
1655 u3phy0: t-phy@11e30000 {
1656 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
1657 #address-cells = <1>;
1658 #size-cells = <1>;
1662 u2port0: usb-phy@0 {
1666 clock-names = "ref", "da_ref";
1667 #phy-cells = <1>;
1671 u3phy1: t-phy@11e40000 {
1672 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
1673 #address-cells = <1>;
1674 #size-cells = <1>;
1678 u2port1: usb-phy@0 {
1682 clock-names = "ref", "da_ref";
1683 #phy-cells = <1>;
1686 u3port1: usb-phy@700 {
1690 clock-names = "ref", "da_ref";
1691 #phy-cells = <1>;
1696 u3phy2: t-phy@11e80000 {
1697 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
1698 #address-cells = <1>;
1699 #size-cells = <1>;
1703 u2port2: usb-phy@0 {
1707 clock-names = "ref", "da_ref";
1708 #phy-cells = <1>;
1713 compatible = "mediatek,mt8188-i2c";
1717 clock-div = <1>;
1720 clock-names = "main", "dma";
1721 #address-cells = <1>;
1722 #size-cells = <0>;
1727 compatible = "mediatek,mt8188-i2c";
1731 clock-div = <1>;
1734 clock-names = "main", "dma";
1735 #address-cells = <1>;
1736 #size-cells = <0>;
1740 imp_iic_wrap_en: clock-controller@11ec2000 {
1741 compatible = "mediatek,mt8188-imp-iic-wrap-en";
1743 #clock-cells = <1>;
1747 compatible = "mediatek,mt8188-efuse", "mediatek,efuse";
1749 #address-cells = <1>;
1750 #size-cells = <1>;
1752 lvts_efuse_data1: lvts1-calib@1ac {
1758 compatible = "mediatek,mt8188-mali", "arm,mali-valhall-jm";
1765 interrupt-names = "job", "mmu", "gpu";
1766 operating-points-v2 = <&gpu_opp_table>;
1767 power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>,
1770 power-domain-names = "core0", "core1", "core2";
1771 #cooling-cells = <2>;
1775 mfgcfg: clock-controller@13fbf000 {
1776 compatible = "mediatek,mt8188-mfgcfg";
1778 #clock-cells = <1>;
1781 vppsys0: clock-controller@14000000 {
1782 compatible = "mediatek,mt8188-vppsys0";
1784 #clock-cells = <1>;
1787 wpesys: clock-controller@14e00000 {
1788 compatible = "mediatek,mt8188-wpesys";
1790 #clock-cells = <1>;
1793 wpesys_vpp0: clock-controller@14e02000 {
1794 compatible = "mediatek,mt8188-wpesys-vpp0";
1796 #clock-cells = <1>;
1799 vppsys1: clock-controller@14f00000 {
1800 compatible = "mediatek,mt8188-vppsys1";
1802 #clock-cells = <1>;
1805 imgsys: clock-controller@15000000 {
1806 compatible = "mediatek,mt8188-imgsys";
1808 #clock-cells = <1>;
1811 imgsys1_dip_top: clock-controller@15110000 {
1812 compatible = "mediatek,mt8188-imgsys1-dip-top";
1814 #clock-cells = <1>;
1817 imgsys1_dip_nr: clock-controller@15130000 {
1818 compatible = "mediatek,mt8188-imgsys1-dip-nr";
1820 #clock-cells = <1>;
1823 imgsys_wpe1: clock-controller@15220000 {
1824 compatible = "mediatek,mt8188-imgsys-wpe1";
1826 #clock-cells = <1>;
1829 ipesys: clock-controller@15330000 {
1830 compatible = "mediatek,mt8188-ipesys";
1832 #clock-cells = <1>;
1835 imgsys_wpe2: clock-controller@15520000 {
1836 compatible = "mediatek,mt8188-imgsys-wpe2";
1838 #clock-cells = <1>;
1841 imgsys_wpe3: clock-controller@15620000 {
1842 compatible = "mediatek,mt8188-imgsys-wpe3";
1844 #clock-cells = <1>;
1847 camsys: clock-controller@16000000 {
1848 compatible = "mediatek,mt8188-camsys";
1850 #clock-cells = <1>;
1853 camsys_rawa: clock-controller@1604f000 {
1854 compatible = "mediatek,mt8188-camsys-rawa";
1856 #clock-cells = <1>;
1859 camsys_yuva: clock-controller@1606f000 {
1860 compatible = "mediatek,mt8188-camsys-yuva";
1862 #clock-cells = <1>;
1865 camsys_rawb: clock-controller@1608f000 {
1866 compatible = "mediatek,mt8188-camsys-rawb";
1868 #clock-cells = <1>;
1871 camsys_yuvb: clock-controller@160af000 { label
1872 compatible = "mediatek,mt8188-camsys-yuvb";
1874 #clock-cells = <1>;
1877 ccusys: clock-controller@17200000 {
1878 compatible = "mediatek,mt8188-ccusys";
1880 #clock-cells = <1>;
1883 vdecsys_soc: clock-controller@1800f000 {
1884 compatible = "mediatek,mt8188-vdecsys-soc";
1886 #clock-cells = <1>;
1889 vdecsys: clock-controller@1802f000 {
1890 compatible = "mediatek,mt8188-vdecsys";
1892 #clock-cells = <1>;
1895 vencsys: clock-controller@1a000000 {
1896 compatible = "mediatek,mt8188-vencsys";
1898 #clock-cells = <1>;
1902 compatible = "mediatek,mt8188-vdosys0", "syscon";
1904 #clock-cells = <1>;
1906 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xd000 0x1000>;
1910 compatible = "mediatek,mt8188-vdosys1", "syscon";
1912 #clock-cells = <1>;
1913 #reset-cells = <1>;
1915 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0 0x1000>;