Lines Matching +full:mt8188 +full:- +full:pinctrl
1 // SPDX-License-Identifier: GPL-2.0+
7 /dts-v1/;
8 #include <dt-bindings/clock/mediatek,mt8188-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/mailbox/mediatek,mt8188-gce.h>
12 #include <dt-bindings/memory/mediatek,mt8188-memory-port.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
15 #include <dt-bindings/power/mediatek,mt8188-power.h>
16 #include <dt-bindings/reset/mt8188-resets.h>
17 #include <dt-bindings/thermal/thermal.h>
18 #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
21 compatible = "mediatek,mt8188";
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
27 dp-intf0 = &dp_intf0;
28 dp-intf1 = &dp_intf1;
49 vdo1-rdma0 = &vdo1_rdma0;
50 vdo1-rdma1 = &vdo1_rdma1;
51 vdo1-rdma2 = &vdo1_rdma2;
52 vdo1-rdma3 = &vdo1_rdma3;
53 vdo1-rdma4 = &vdo1_rdma4;
54 vdo1-rdma5 = &vdo1_rdma5;
55 vdo1-rdma6 = &vdo1_rdma6;
56 vdo1-rdma7 = &vdo1_rdma7;
60 #address-cells = <1>;
61 #size-cells = <0>;
65 compatible = "arm,cortex-a55";
67 enable-method = "psci";
68 clock-frequency = <2000000000>;
69 capacity-dmips-mhz = <282>;
70 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
71 i-cache-size = <32768>;
72 i-cache-line-size = <64>;
73 i-cache-sets = <128>;
74 d-cache-size = <32768>;
75 d-cache-line-size = <64>;
76 d-cache-sets = <128>;
77 next-level-cache = <&l2_0>;
78 performance-domains = <&performance 0>;
79 #cooling-cells = <2>;
84 compatible = "arm,cortex-a55";
86 enable-method = "psci";
87 clock-frequency = <2000000000>;
88 capacity-dmips-mhz = <282>;
89 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
90 i-cache-size = <32768>;
91 i-cache-line-size = <64>;
92 i-cache-sets = <128>;
93 d-cache-size = <32768>;
94 d-cache-line-size = <64>;
95 d-cache-sets = <128>;
96 next-level-cache = <&l2_0>;
97 performance-domains = <&performance 0>;
98 #cooling-cells = <2>;
103 compatible = "arm,cortex-a55";
105 enable-method = "psci";
106 clock-frequency = <2000000000>;
107 capacity-dmips-mhz = <282>;
108 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
109 i-cache-size = <32768>;
110 i-cache-line-size = <64>;
111 i-cache-sets = <128>;
112 d-cache-size = <32768>;
113 d-cache-line-size = <64>;
114 d-cache-sets = <128>;
115 next-level-cache = <&l2_0>;
116 performance-domains = <&performance 0>;
117 #cooling-cells = <2>;
122 compatible = "arm,cortex-a55";
124 enable-method = "psci";
125 clock-frequency = <2000000000>;
126 capacity-dmips-mhz = <282>;
127 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
128 i-cache-size = <32768>;
129 i-cache-line-size = <64>;
130 i-cache-sets = <128>;
131 d-cache-size = <32768>;
132 d-cache-line-size = <64>;
133 d-cache-sets = <128>;
134 next-level-cache = <&l2_0>;
135 performance-domains = <&performance 0>;
136 #cooling-cells = <2>;
141 compatible = "arm,cortex-a55";
143 enable-method = "psci";
144 clock-frequency = <2000000000>;
145 capacity-dmips-mhz = <282>;
146 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
147 i-cache-size = <32768>;
148 i-cache-line-size = <64>;
149 i-cache-sets = <128>;
150 d-cache-size = <32768>;
151 d-cache-line-size = <64>;
152 d-cache-sets = <128>;
153 next-level-cache = <&l2_0>;
154 performance-domains = <&performance 0>;
155 #cooling-cells = <2>;
160 compatible = "arm,cortex-a55";
162 enable-method = "psci";
163 clock-frequency = <2000000000>;
164 capacity-dmips-mhz = <282>;
165 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
166 i-cache-size = <32768>;
167 i-cache-line-size = <64>;
168 i-cache-sets = <128>;
169 d-cache-size = <32768>;
170 d-cache-line-size = <64>;
171 d-cache-sets = <128>;
172 next-level-cache = <&l2_0>;
173 performance-domains = <&performance 0>;
174 #cooling-cells = <2>;
179 compatible = "arm,cortex-a78";
181 enable-method = "psci";
182 clock-frequency = <2600000000>;
183 capacity-dmips-mhz = <1024>;
184 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
185 i-cache-size = <65536>;
186 i-cache-line-size = <64>;
187 i-cache-sets = <256>;
188 d-cache-size = <65536>;
189 d-cache-line-size = <64>;
190 d-cache-sets = <256>;
191 next-level-cache = <&l2_1>;
192 performance-domains = <&performance 1>;
193 #cooling-cells = <2>;
198 compatible = "arm,cortex-a78";
200 enable-method = "psci";
201 clock-frequency = <2600000000>;
202 capacity-dmips-mhz = <1024>;
203 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
204 i-cache-size = <65536>;
205 i-cache-line-size = <64>;
206 i-cache-sets = <256>;
207 d-cache-size = <65536>;
208 d-cache-line-size = <64>;
209 d-cache-sets = <256>;
210 next-level-cache = <&l2_1>;
211 performance-domains = <&performance 1>;
212 #cooling-cells = <2>;
215 cpu-map {
251 idle-states {
252 entry-method = "psci";
254 cpu_off_l: cpu-off-l {
255 compatible = "arm,idle-state";
256 arm,psci-suspend-param = <0x00010000>;
257 local-timer-stop;
258 entry-latency-us = <50>;
259 exit-latency-us = <95>;
260 min-residency-us = <580>;
263 cpu_off_b: cpu-off-b {
264 compatible = "arm,idle-state";
265 arm,psci-suspend-param = <0x00010000>;
266 local-timer-stop;
267 entry-latency-us = <45>;
268 exit-latency-us = <140>;
269 min-residency-us = <740>;
272 cluster_off_l: cluster-off-l {
273 compatible = "arm,idle-state";
274 arm,psci-suspend-param = <0x01010010>;
275 local-timer-stop;
276 entry-latency-us = <55>;
277 exit-latency-us = <155>;
278 min-residency-us = <840>;
281 cluster_off_b: cluster-off-b {
282 compatible = "arm,idle-state";
283 arm,psci-suspend-param = <0x01010010>;
284 local-timer-stop;
285 entry-latency-us = <50>;
286 exit-latency-us = <200>;
287 min-residency-us = <1000>;
291 l2_0: l2-cache0 {
293 cache-level = <2>;
294 cache-size = <131072>;
295 cache-line-size = <64>;
296 cache-sets = <512>;
297 next-level-cache = <&l3_0>;
298 cache-unified;
301 l2_1: l2-cache1 {
303 cache-level = <2>;
304 cache-size = <262144>;
305 cache-line-size = <64>;
306 cache-sets = <512>;
307 next-level-cache = <&l3_0>;
308 cache-unified;
311 l3_0: l3-cache {
313 cache-level = <3>;
314 cache-size = <2097152>;
315 cache-line-size = <64>;
316 cache-sets = <2048>;
317 cache-unified;
321 clk13m: oscillator-13m {
322 compatible = "fixed-clock";
323 #clock-cells = <0>;
324 clock-frequency = <13000000>;
325 clock-output-names = "clk13m";
328 clk26m: oscillator-26m {
329 compatible = "fixed-clock";
330 #clock-cells = <0>;
331 clock-frequency = <26000000>;
332 clock-output-names = "clk26m";
335 clk32k: oscillator-32k {
336 compatible = "fixed-clock";
337 #clock-cells = <0>;
338 clock-frequency = <32768>;
339 clock-output-names = "clk32k";
342 gpu_opp_table: opp-table-gpu {
343 compatible = "operating-points-v2";
344 opp-shared;
346 opp-390000000 {
347 opp-hz = /bits/ 64 <390000000>;
348 opp-microvolt = <575000>;
349 opp-supported-hw = <0xff>;
351 opp-431000000 {
352 opp-hz = /bits/ 64 <431000000>;
353 opp-microvolt = <587500>;
354 opp-supported-hw = <0xff>;
356 opp-473000000 {
357 opp-hz = /bits/ 64 <473000000>;
358 opp-microvolt = <600000>;
359 opp-supported-hw = <0xff>;
361 opp-515000000 {
362 opp-hz = /bits/ 64 <515000000>;
363 opp-microvolt = <612500>;
364 opp-supported-hw = <0xff>;
366 opp-556000000 {
367 opp-hz = /bits/ 64 <556000000>;
368 opp-microvolt = <625000>;
369 opp-supported-hw = <0xff>;
371 opp-598000000 {
372 opp-hz = /bits/ 64 <598000000>;
373 opp-microvolt = <637500>;
374 opp-supported-hw = <0xff>;
376 opp-640000000 {
377 opp-hz = /bits/ 64 <640000000>;
378 opp-microvolt = <650000>;
379 opp-supported-hw = <0xff>;
381 opp-670000000 {
382 opp-hz = /bits/ 64 <670000000>;
383 opp-microvolt = <662500>;
384 opp-supported-hw = <0xff>;
386 opp-700000000 {
387 opp-hz = /bits/ 64 <700000000>;
388 opp-microvolt = <675000>;
389 opp-supported-hw = <0xff>;
391 opp-730000000 {
392 opp-hz = /bits/ 64 <730000000>;
393 opp-microvolt = <687500>;
394 opp-supported-hw = <0xff>;
396 opp-760000000 {
397 opp-hz = /bits/ 64 <760000000>;
398 opp-microvolt = <700000>;
399 opp-supported-hw = <0xff>;
401 opp-790000000 {
402 opp-hz = /bits/ 64 <790000000>;
403 opp-microvolt = <712500>;
404 opp-supported-hw = <0xff>;
406 opp-835000000 {
407 opp-hz = /bits/ 64 <835000000>;
408 opp-microvolt = <731250>;
409 opp-supported-hw = <0xff>;
411 opp-880000000 {
412 opp-hz = /bits/ 64 <880000000>;
413 opp-microvolt = <750000>;
414 opp-supported-hw = <0xff>;
416 opp-915000000 {
417 opp-hz = /bits/ 64 <915000000>;
418 opp-microvolt = <775000>;
419 opp-supported-hw = <0x8f>;
421 opp-915000000-5 {
422 opp-hz = /bits/ 64 <915000000>;
423 opp-microvolt = <762500>;
424 opp-supported-hw = <0x30>;
426 opp-915000000-6 {
427 opp-hz = /bits/ 64 <915000000>;
428 opp-microvolt = <750000>;
429 opp-supported-hw = <0x70>;
431 opp-950000000 {
432 opp-hz = /bits/ 64 <950000000>;
433 opp-microvolt = <800000>;
434 opp-supported-hw = <0x8f>;
436 opp-950000000-5 {
437 opp-hz = /bits/ 64 <950000000>;
438 opp-microvolt = <775000>;
439 opp-supported-hw = <0x30>;
441 opp-950000000-6 {
442 opp-hz = /bits/ 64 <950000000>;
443 opp-microvolt = <750000>;
444 opp-supported-hw = <0x70>;
448 pmu-a55 {
449 compatible = "arm,cortex-a55-pmu";
450 interrupt-parent = <&gic>;
454 pmu-a78 {
455 compatible = "arm,cortex-a78-pmu";
456 interrupt-parent = <&gic>;
461 compatible = "arm,psci-1.0";
470 thermal_zones: thermal-zones {
471 cpu-little0-thermal {
472 polling-delay = <1000>;
473 polling-delay-passive = <150>;
474 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU0>;
477 cpu_little0_alert0: trip-alert0 {
483 cpu_little0_alert1: trip-alert1 {
489 cpu_little0_crit: trip-crit {
496 cooling-maps {
499 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
509 cpu-little1-thermal {
510 polling-delay = <1000>;
511 polling-delay-passive = <150>;
512 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU1>;
515 cpu_little1_alert0: trip-alert0 {
521 cpu_little1_alert1: trip-alert1 {
527 cpu_little1_crit: trip-crit {
534 cooling-maps {
537 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
547 cpu-little2-thermal {
548 polling-delay = <1000>;
549 polling-delay-passive = <150>;
550 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU2>;
553 cpu_little2_alert0: trip-alert0 {
559 cpu_little2_alert1: trip-alert1 {
565 cpu_little2_crit: trip-crit {
572 cooling-maps {
575 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
585 cpu-little3-thermal {
586 polling-delay = <1000>;
587 polling-delay-passive = <150>;
588 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU3>;
591 cpu_little3_alert0: trip-alert0 {
597 cpu_little3_alert1: trip-alert1 {
603 cpu_little3_crit: trip-crit {
610 cooling-maps {
613 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
623 cpu-big0-thermal {
624 polling-delay = <1000>;
625 polling-delay-passive = <100>;
626 thermal-sensors = <&lvts_mcu MT8188_MCU_BIG_CPU0>;
629 cpu_big0_alert0: trip-alert0 {
635 cpu_big0_alert1: trip-alert1 {
641 cpu_big0_crit: trip-crit {
648 cooling-maps {
651 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
657 cpu-big1-thermal {
658 polling-delay = <1000>;
659 polling-delay-passive = <100>;
660 thermal-sensors = <&lvts_mcu MT8188_MCU_BIG_CPU1>;
663 cpu_big1_alert0: trip-alert0 {
669 cpu_big1_alert1: trip-alert1 {
675 cpu_big1_crit: trip-crit {
682 cooling-maps {
685 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
691 apu-thermal {
692 polling-delay = <1000>;
693 polling-delay-passive = <250>;
694 thermal-sensors = <&lvts_ap MT8188_AP_APU>;
697 apu_alert0: trip-alert0 {
703 apu_alert1: trip-alert1 {
709 apu_crit: trip-crit {
717 gpu-thermal {
718 polling-delay = <1000>;
719 polling-delay-passive = <250>;
720 thermal-sensors = <&lvts_ap MT8188_AP_GPU0>;
723 gpu_alert0: trip-alert0 {
729 gpu_alert1: trip-alert1 {
735 gpu_crit: trip-crit {
742 cooling-maps {
745 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
750 gpu1-thermal {
751 polling-delay = <1000>;
752 polling-delay-passive = <250>;
753 thermal-sensors = <&lvts_ap MT8188_AP_GPU1>;
756 gpu1_alert0: trip-alert0 {
762 gpu1_alert1: trip-alert1 {
768 gpu1_crit: trip-crit {
775 cooling-maps {
778 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
783 adsp-thermal {
784 polling-delay = <1000>;
785 polling-delay-passive = <250>;
786 thermal-sensors = <&lvts_ap MT8188_AP_ADSP>;
789 soc_alert0: trip-alert0 {
795 soc_alert1: trip-alert1 {
801 soc_crit: trip-crit {
809 vdo-thermal {
810 polling-delay = <1000>;
811 polling-delay-passive = <250>;
812 thermal-sensors = <&lvts_ap MT8188_AP_VDO>;
815 soc1_alert0: trip-alert0 {
821 soc1_alert1: trip-alert1 {
827 soc1_crit: trip-crit {
835 infra-thermal {
836 polling-delay = <1000>;
837 polling-delay-passive = <250>;
838 thermal-sensors = <&lvts_ap MT8188_AP_INFRA>;
841 soc2_alert0: trip-alert0 {
847 soc2_alert1: trip-alert1 {
853 soc2_crit: trip-crit {
861 cam1-thermal {
862 polling-delay = <1000>;
863 polling-delay-passive = <250>;
864 thermal-sensors = <&lvts_ap MT8188_AP_CAM1>;
867 cam1_alert0: trip-alert0 {
873 cam1_alert1: trip-alert1 {
879 cam1_crit: trip-crit {
887 cam2-thermal {
888 polling-delay = <1000>;
889 polling-delay-passive = <250>;
890 thermal-sensors = <&lvts_ap MT8188_AP_CAM2>;
893 cam2_alert0: trip-alert0 {
899 cam2_alert1: trip-alert1 {
905 cam2_crit: trip-crit {
915 compatible = "arm,armv8-timer";
916 interrupt-parent = <&gic>;
921 clock-frequency = <13000000>;
925 #address-cells = <2>;
926 #size-cells = <2>;
927 compatible = "simple-bus";
928 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
931 performance: performance-controller@11bc10 {
932 compatible = "mediatek,cpufreq-hw";
934 #performance-domain-cells = <1>;
937 gic: interrupt-controller@c000000 {
938 compatible = "arm,gic-v3";
939 #interrupt-cells = <4>;
940 #redistributor-regions = <1>;
941 interrupt-parent = <&gic>;
942 interrupt-controller;
947 ppi-partitions {
948 ppi_cluster0: interrupt-partition-0 {
952 ppi_cluster1: interrupt-partition-1 {
959 compatible = "mediatek,mt8188-topckgen", "syscon";
961 #clock-cells = <1>;
965 compatible = "mediatek,mt8188-infracfg-ao", "syscon";
967 #clock-cells = <1>;
968 #reset-cells = <1>;
972 compatible = "mediatek,mt8188-pericfg", "syscon";
974 #clock-cells = <1>;
977 pio: pinctrl@10005000 {
978 compatible = "mediatek,mt8188-pinctrl";
985 reg-names = "iocfg0", "iocfg_rm", "iocfg_lt",
987 gpio-controller;
988 #gpio-cells = <2>;
989 gpio-ranges = <&pio 0 0 176>;
990 interrupt-controller;
992 #interrupt-cells = <2>;
996 compatible = "mediatek,mt8188-scpsys", "syscon", "simple-mfd";
1000 spm: power-controller {
1001 compatible = "mediatek,mt8188-power-controller";
1002 #address-cells = <1>;
1003 #size-cells = <0>;
1004 #power-domain-cells = <1>;
1007 mfg0: power-domain@MT8188_POWER_DOMAIN_MFG0 {
1009 #address-cells = <1>;
1010 #size-cells = <0>;
1011 #power-domain-cells = <1>;
1013 mfg1: power-domain@MT8188_POWER_DOMAIN_MFG1 {
1017 clock-names = "mfg", "alt";
1019 #address-cells = <1>;
1020 #size-cells = <0>;
1021 #power-domain-cells = <1>;
1023 power-domain@MT8188_POWER_DOMAIN_MFG2 {
1025 #power-domain-cells = <0>;
1028 power-domain@MT8188_POWER_DOMAIN_MFG3 {
1030 #power-domain-cells = <0>;
1033 power-domain@MT8188_POWER_DOMAIN_MFG4 {
1035 #power-domain-cells = <0>;
1040 power-domain@MT8188_POWER_DOMAIN_VPPSYS0 {
1070 clock-names = "top", "cam", "ccu", "img", "venc",
1072 "ss-sram-cmn", "ss-sram-v0l0", "ss-sram-v0l1",
1073 "ss-sram-ve0", "ss-sram-ve1", "ss-sram-ifa",
1074 "ss-sram-cam", "ss-sram-v1l5", "ss-sram-v1l6",
1075 "ss-sram-rdr", "ss-iommu", "ss-imgcam",
1076 "ss-emi", "ss-subcmn-rdr", "ss-rsi",
1077 "ss-cmn-l4", "ss-vdec1", "ss-wpe",
1078 "ss-cvdo-ve1";
1080 #address-cells = <1>;
1081 #size-cells = <0>;
1082 #power-domain-cells = <1>;
1084 power-domain@MT8188_POWER_DOMAIN_VDOSYS0 {
1095 clock-names = "cfgck", "cfgxo", "ss-gals",
1096 "ss-cmn", "ss-emi", "ss-iommu",
1097 "ss-larb", "ss-rsi", "ss-bus";
1099 #address-cells = <1>;
1100 #size-cells = <0>;
1101 #power-domain-cells = <1>;
1103 power-domain@MT8188_POWER_DOMAIN_VPPSYS1 {
1111 clock-names = "cfgck", "cfgxo",
1112 "ss-vpp1-g5", "ss-vpp1-g6",
1113 "ss-vpp1-l5", "ss-vpp1-l6";
1115 #power-domain-cells = <0>;
1118 power-domain@MT8188_POWER_DOMAIN_VDEC0 {
1121 clock-names = "ss-vdec1-soc-l1";
1123 #address-cells = <1>;
1124 #size-cells = <0>;
1125 #power-domain-cells = <1>;
1127 power-domain@MT8188_POWER_DOMAIN_VDEC1 {
1130 clock-names = "ss-vdec2-l1";
1132 #power-domain-cells = <0>;
1136 cam_vcore: power-domain@MT8188_POWER_DOMAIN_CAM_VCORE {
1142 clock-names = "cam", "ccu", "bus", "cfgck";
1144 #address-cells = <1>;
1145 #size-cells = <0>;
1146 #power-domain-cells = <1>;
1148 power-domain@MT8188_POWER_DOMAIN_CAM_MAIN {
1155 clock-names= "ss-cam-l13", "ss-cam-l14",
1156 "ss-cam-mm0", "ss-cam-mm1",
1157 "ss-camsys";
1159 #address-cells = <1>;
1160 #size-cells = <0>;
1161 #power-domain-cells = <1>;
1163 power-domain@MT8188_POWER_DOMAIN_CAM_SUBB {
1168 clock-names = "ss-camb-sub",
1169 "ss-camb-raw",
1170 "ss-camb-yuv";
1171 #power-domain-cells = <0>;
1174 power-domain@MT8188_POWER_DOMAIN_CAM_SUBA {
1179 clock-names = "ss-cama-sub",
1180 "ss-cama-raw",
1181 "ss-cama-yuv";
1182 #power-domain-cells = <0>;
1187 power-domain@MT8188_POWER_DOMAIN_VDOSYS1 {
1194 clock-names = "cfgck", "cfgxo", "ss-larb2",
1195 "ss-larb3", "ss-gals";
1197 #address-cells = <1>;
1198 #size-cells = <0>;
1199 #power-domain-cells = <1>;
1201 power-domain@MT8188_POWER_DOMAIN_HDMI_TX {
1205 clock-names = "bus", "hdcp";
1207 #power-domain-cells = <0>;
1210 power-domain@MT8188_POWER_DOMAIN_DP_TX {
1213 #power-domain-cells = <0>;
1216 power-domain@MT8188_POWER_DOMAIN_EDP_TX {
1219 #power-domain-cells = <0>;
1223 power-domain@MT8188_POWER_DOMAIN_VENC {
1229 clock-names = "ss-ve1-larb", "ss-ve1-core",
1230 "ss-ve1-gals", "ss-ve1-sram";
1232 #power-domain-cells = <0>;
1235 power-domain@MT8188_POWER_DOMAIN_WPE {
1239 clock-names = "ss-wpe-l7", "ss-wpe-l7pce";
1241 #power-domain-cells = <0>;
1246 power-domain@MT8188_POWER_DOMAIN_PEXTP_MAC_P0 {
1250 clock-names = "ss-pextp-fmem";
1251 #power-domain-cells = <0>;
1254 power-domain@MT8188_POWER_DOMAIN_CSIRX_TOP {
1258 clock-names = "seninf0", "seninf1";
1259 #power-domain-cells = <0>;
1262 power-domain@MT8188_POWER_DOMAIN_PEXTP_PHY_TOP {
1264 #power-domain-cells = <0>;
1267 power-domain@MT8188_POWER_DOMAIN_ADSP_AO {
1271 clock-names = "bus", "main";
1273 #address-cells = <1>;
1274 #size-cells = <0>;
1275 #power-domain-cells = <1>;
1277 power-domain@MT8188_POWER_DOMAIN_ADSP_INFRA {
1280 #address-cells = <1>;
1281 #size-cells = <0>;
1282 #power-domain-cells = <1>;
1284 power-domain@MT8188_POWER_DOMAIN_AUDIO_ASRC {
1287 clock-names = "asm";
1289 #power-domain-cells = <0>;
1292 power-domain@MT8188_POWER_DOMAIN_AUDIO {
1297 clock-names = "a1sys", "intbus", "adspck";
1299 #power-domain-cells = <0>;
1302 power-domain@MT8188_POWER_DOMAIN_ADSP {
1305 #power-domain-cells = <0>;
1310 power-domain@MT8188_POWER_DOMAIN_ETHER {
1313 clock-names = "ethermac";
1315 #power-domain-cells = <0>;
1321 compatible = "mediatek,mt8188-wdt";
1323 mediatek,disable-extrst;
1324 #reset-cells = <1>;
1328 compatible = "mediatek,mt8188-apmixedsys", "syscon";
1330 #clock-cells = <1>;
1334 compatible = "mediatek,mt8188-timer", "mediatek,mt6765-timer";
1341 compatible = "mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap", "syscon";
1343 reg-names = "pwrap";
1347 clock-names = "spi", "wrap";
1351 compatible = "mediatek,mt8188-spmi", "mediatek,mt8195-spmi";
1353 reg-names = "pmif", "spmimst";
1354 assigned-clocks = <&topckgen CLK_TOP_SPMI_M_MST>;
1355 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
1359 clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux";
1363 compatible = "mediatek,mt8188-iommu-infra";
1366 #iommu-cells = <1>;
1370 compatible = "mediatek,mt8188-gce";
1373 #mbox-cells = <2>;
1378 compatible = "mediatek,mt8188-gce";
1381 #mbox-cells = <2>;
1386 compatible = "mediatek,mt8188-scp";
1389 reg-names = "sram", "cfg";
1393 afe: audio-controller@10b10000 {
1394 compatible = "mediatek,mt8188-afe";
1396 assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP>;
1397 assigned-clock-parents = <&topckgen CLK_TOP_APLL1_D4>;
1421 clock-names = "clk26m",
1445 power-domains = <&spm MT8188_POWER_DOMAIN_AUDIO>;
1447 reset-names = "audiosys";
1454 compatible = "mediatek,mt8188-dsp";
1459 reg-names = "cfg", "sram", "sec", "bus";
1460 assigned-clocks = <&topckgen CLK_TOP_ADSP>;
1463 clock-names = "audiodsp", "adsp_bus";
1465 mbox-names = "rx", "tx";
1466 power-domains = <&spm MT8188_POWER_DOMAIN_ADSP>;
1471 compatible = "mediatek,mt8188-adsp-mbox", "mediatek,mt8186-adsp-mbox";
1474 #mbox-cells = <0>;
1478 compatible = "mediatek,mt8188-adsp-mbox", "mediatek,mt8186-adsp-mbox";
1481 #mbox-cells = <0>;
1484 adsp_audio26m: clock-controller@10b91100 {
1485 compatible = "mediatek,mt8188-adsp-audio26m";
1487 #clock-cells = <1>;
1491 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
1495 clock-names = "baud", "bus";
1500 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
1504 clock-names = "baud", "bus";
1509 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
1513 clock-names = "baud", "bus";
1518 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
1522 clock-names = "baud", "bus";
1527 compatible = "mediatek,mt8188-auxadc", "mediatek,mt8173-auxadc";
1530 clock-names = "main";
1531 #io-channel-cells = <1>;
1536 compatible = "mediatek,mt8188-pericfg-ao", "syscon";
1538 #clock-cells = <1>;
1542 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1543 #address-cells = <1>;
1544 #size-cells = <0>;
1550 clock-names = "parent-clk", "sel-clk", "spi-clk";
1554 lvts_ap: thermal-sensor@1100b000 {
1555 compatible = "mediatek,mt8188-lvts-ap";
1560 nvmem-cells = <&lvts_efuse_data1>;
1561 nvmem-cell-names = "lvts-calib-data-1";
1562 #thermal-sensor-cells = <1>;
1566 compatible = "mediatek,mt8188-disp-pwm", "mediatek,mt8183-disp-pwm";
1570 clock-names = "main", "mm";
1572 #pwm-cells = <2>;
1577 compatible = "mediatek,mt8188-disp-pwm", "mediatek,mt8183-disp-pwm";
1581 clock-names = "main", "mm";
1583 #pwm-cells = <2>;
1588 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1589 #address-cells = <1>;
1590 #size-cells = <0>;
1596 clock-names = "parent-clk", "sel-clk", "spi-clk";
1601 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1602 #address-cells = <1>;
1603 #size-cells = <0>;
1609 clock-names = "parent-clk", "sel-clk", "spi-clk";
1614 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1615 #address-cells = <1>;
1616 #size-cells = <0>;
1622 clock-names = "parent-clk", "sel-clk", "spi-clk";
1627 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1628 #address-cells = <1>;
1629 #size-cells = <0>;
1635 clock-names = "parent-clk", "sel-clk", "spi-clk";
1640 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
1641 #address-cells = <1>;
1642 #size-cells = <0>;
1648 clock-names = "parent-clk", "sel-clk", "spi-clk";
1653 compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3";
1655 reg-names = "mac", "ippc";
1657 #address-cells = <2>;
1658 #size-cells = <2>;
1660 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>;
1661 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1665 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1667 wakeup-source;
1668 mediatek,syscon-wakeup = <&pericfg 0x468 2>;
1672 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
1674 reg-names = "mac";
1676 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI>;
1677 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1679 clock-names = "sys_ck";
1685 compatible = "mediatek,mt8188-gmac", "mediatek,mt8195-gmac",
1686 "snps,dwmac-5.10a";
1689 interrupt-names = "macirq";
1696 clock-names = "axi", "apb", "mac_main", "ptp_ref",
1698 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
1701 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
1704 power-domains = <&spm MT8188_POWER_DOMAIN_ETHER>;
1706 snps,axi-config = <&stmmac_axi_setup>;
1707 snps,mtl-rx-config = <&mtl_rx_setup>;
1708 snps,mtl-tx-config = <&mtl_tx_setup>;
1711 snps,clk-csr = <0>;
1715 compatible = "snps,dwmac-mdio";
1716 #address-cells = <1>;
1717 #size-cells = <0>;
1720 stmmac_axi_setup: stmmac-axi-config {
1726 mtl_rx_setup: rx-queues-config {
1727 snps,rx-queues-to-use = <4>;
1728 snps,rx-sched-sp;
1731 snps,dcb-algorithm;
1732 snps,map-to-dma-channel = <0x0>;
1736 snps,dcb-algorithm;
1737 snps,map-to-dma-channel = <0x0>;
1741 snps,dcb-algorithm;
1742 snps,map-to-dma-channel = <0x0>;
1746 snps,dcb-algorithm;
1747 snps,map-to-dma-channel = <0x0>;
1751 mtl_tx_setup: tx-queues-config {
1752 snps,tx-queues-to-use = <4>;
1753 snps,tx-sched-wrr;
1756 snps,dcb-algorithm;
1762 snps,dcb-algorithm;
1768 snps,dcb-algorithm;
1774 snps,dcb-algorithm;
1782 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
1790 clock-names = "source", "hclk", "source_cg", "crypto_clk";
1795 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
1802 clock-names = "source", "hclk", "source_cg";
1803 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1804 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1809 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
1816 clock-names = "source", "hclk", "source_cg";
1817 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
1818 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1822 lvts_mcu: thermal-sensor@11278000 {
1823 compatible = "mediatek,mt8188-lvts-mcu";
1828 nvmem-cells = <&lvts_efuse_data1>;
1829 nvmem-cell-names = "lvts-calib-data-1";
1830 #thermal-sensor-cells = <1>;
1834 compatible = "mediatek,mt8188-i2c";
1838 clock-div = <1>;
1841 clock-names = "main", "dma";
1842 #address-cells = <1>;
1843 #size-cells = <0>;
1848 compatible = "mediatek,mt8188-i2c";
1852 clock-div = <1>;
1855 clock-names = "main", "dma";
1856 #address-cells = <1>;
1857 #size-cells = <0>;
1862 compatible = "mediatek,mt8188-i2c";
1866 clock-div = <1>;
1869 clock-names = "main", "dma";
1870 #address-cells = <1>;
1871 #size-cells = <0>;
1875 imp_iic_wrap_c: clock-controller@11283000 {
1876 compatible = "mediatek,mt8188-imp-iic-wrap-c";
1878 #clock-cells = <1>;
1882 compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3";
1884 reg-names = "mac", "ippc";
1886 #address-cells = <2>;
1887 #size-cells = <2>;
1889 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>;
1890 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1894 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1896 wakeup-source;
1897 mediatek,syscon-wakeup = <&pericfg 0x470 2>;
1901 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
1903 reg-names = "mac";
1905 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
1906 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1908 clock-names = "sys_ck";
1914 compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3";
1916 reg-names = "mac", "ippc";
1918 #address-cells = <2>;
1919 #size-cells = <2>;
1921 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
1922 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1926 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1928 wakeup-source;
1929 mediatek,syscon-wakeup = <&pericfg 0x460 2>;
1933 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
1935 reg-names = "mac";
1937 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>;
1938 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1940 clock-names = "sys_ck";
1946 compatible = "mediatek,mt8188-pcie", "mediatek,mt8192-pcie";
1948 reg-names = "pcie-mac";
1950 bus-range = <0 0xff>;
1952 linux,pci-domain = <0>;
1953 #address-cells = <3>;
1954 #size-cells = <2>;
1962 clock-names = "pl_250m", "tl_26m", "tl_96m", "tl_32k",
1965 #interrupt-cells = <1>;
1967 interrupt-map = <0 0 0 1 &pcie_intc 0>,
1971 interrupt-map-mask = <0 0 0 7>;
1973 iommu-map = <0 &infra_iommu IFR_IOMMU_PORT_PCIE_0 0xffff>;
1974 iommu-map-mask = <0>;
1977 phy-names = "pcie-phy";
1979 power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_MAC_P0>;
1982 reset-names = "mac";
1986 pcie_intc: interrupt-controller {
1987 #address-cells = <0>;
1988 #interrupt-cells = <1>;
1989 interrupt-controller;
1994 compatible = "mediatek,mt8188-nor", "mediatek,mt8186-nor";
1999 clock-names = "spi", "sf", "axi";
2000 assigned-clocks = <&topckgen CLK_TOP_SPINOR>;
2002 #address-cells = <1>;
2003 #size-cells = <0>;
2007 pciephy: t-phy@11c20700 {
2008 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
2010 #address-cells = <1>;
2011 #size-cells = <1>;
2012 power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_PHY_TOP>;
2015 pcieport: pcie-phy@0 {
2018 clock-names = "ref";
2019 #phy-cells = <1>;
2023 mipi_tx_config0: dsi-phy@11c80000 {
2024 compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx";
2027 clock-output-names = "mipi_tx0_pll";
2028 #clock-cells = <0>;
2029 #phy-cells = <0>;
2033 mipi_tx_config1: dsi-phy@11c90000 {
2034 compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx";
2037 clock-output-names = "mipi_tx0_pll";
2038 #clock-cells = <0>;
2039 #phy-cells = <0>;
2044 compatible = "mediatek,mt8188-i2c";
2048 clock-div = <1>;
2051 clock-names = "main", "dma";
2052 #address-cells = <1>;
2053 #size-cells = <0>;
2058 compatible = "mediatek,mt8188-i2c";
2062 clock-div = <1>;
2065 clock-names = "main", "dma";
2066 #address-cells = <1>;
2067 #size-cells = <0>;
2071 imp_iic_wrap_w: clock-controller@11e02000 {
2072 compatible = "mediatek,mt8188-imp-iic-wrap-w";
2074 #clock-cells = <1>;
2077 u3phy0: t-phy@11e30000 {
2078 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
2079 #address-cells = <1>;
2080 #size-cells = <1>;
2084 u2port0: usb-phy@0 {
2088 clock-names = "ref", "da_ref";
2089 #phy-cells = <1>;
2093 u3phy1: t-phy@11e40000 {
2094 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
2095 #address-cells = <1>;
2096 #size-cells = <1>;
2100 u2port1: usb-phy@0 {
2104 clock-names = "ref", "da_ref";
2105 #phy-cells = <1>;
2108 u3port1: usb-phy@700 {
2112 clock-names = "ref", "da_ref";
2113 #phy-cells = <1>;
2117 u3phy2: t-phy@11e80000 {
2118 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
2119 #address-cells = <1>;
2120 #size-cells = <1>;
2124 u2port2: usb-phy@0 {
2128 clock-names = "ref", "da_ref";
2129 #phy-cells = <1>;
2134 compatible = "mediatek,mt8188-i2c";
2138 clock-div = <1>;
2141 clock-names = "main", "dma";
2142 #address-cells = <1>;
2143 #size-cells = <0>;
2148 compatible = "mediatek,mt8188-i2c";
2152 clock-div = <1>;
2155 clock-names = "main", "dma";
2156 #address-cells = <1>;
2157 #size-cells = <0>;
2161 imp_iic_wrap_en: clock-controller@11ec2000 {
2162 compatible = "mediatek,mt8188-imp-iic-wrap-en";
2164 #clock-cells = <1>;
2168 compatible = "mediatek,mt8188-efuse", "mediatek,efuse";
2170 #address-cells = <1>;
2171 #size-cells = <1>;
2173 dp_calib_data: dp-calib@1a0 {
2177 lvts_efuse_data1: lvts1-calib@1ac {
2181 gpu_speedbin: gpu-speedbin@581 {
2186 socinfo-data1@7a0 {
2190 socinfo-data2@7e0 {
2196 compatible = "mediatek,mt8188-mali", "arm,mali-valhall-jm";
2203 interrupt-names = "job", "mmu", "gpu";
2204 nvmem-cells = <&gpu_speedbin>;
2205 nvmem-cell-names = "speed-bin";
2206 operating-points-v2 = <&gpu_opp_table>;
2207 power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>,
2210 power-domain-names = "core0", "core1", "core2";
2211 #cooling-cells = <2>;
2215 mfgcfg: clock-controller@13fbf000 {
2216 compatible = "mediatek,mt8188-mfgcfg";
2218 #clock-cells = <1>;
2222 compatible = "mediatek,mt8188-vppsys0", "syscon";
2224 #clock-cells = <1>;
2228 compatible = "mediatek,mt8188-smi-common-vpp";
2232 clock-names = "apb", "smi";
2233 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
2237 compatible = "mediatek,mt8188-smi-larb";
2241 clock-names = "apb", "smi";
2242 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
2243 mediatek,larb-id = <SMI_L4_ID>;
2248 compatible = "mediatek,mt8188-iommu-vpp";
2251 clock-names = "bclk";
2253 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
2254 #iommu-cells = <1>;
2258 wpesys: clock-controller@14e00000 {
2259 compatible = "mediatek,mt8188-wpesys";
2261 #clock-cells = <1>;
2264 wpesys_vpp0: clock-controller@14e02000 {
2265 compatible = "mediatek,mt8188-wpesys-vpp0";
2267 #clock-cells = <1>;
2271 compatible = "mediatek,mt8188-smi-larb";
2275 clock-names = "apb", "smi";
2276 power-domains = <&spm MT8188_POWER_DOMAIN_WPE>;
2277 mediatek,larb-id = <SMI_L7_ID>;
2282 compatible = "mediatek,mt8188-vppsys1", "syscon";
2284 #clock-cells = <1>;
2288 compatible = "mediatek,mt8188-smi-larb";
2292 clock-names = "apb", "smi";
2293 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
2294 mediatek,larb-id = <SMI_L5_ID>;
2299 compatible = "mediatek,mt8188-smi-larb";
2303 clock-names = "apb", "smi";
2304 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
2305 mediatek,larb-id = <SMI_L6_ID>;
2309 imgsys: clock-controller@15000000 {
2310 compatible = "mediatek,mt8188-imgsys";
2312 #clock-cells = <1>;
2315 imgsys1_dip_top: clock-controller@15110000 {
2316 compatible = "mediatek,mt8188-imgsys1-dip-top";
2318 #clock-cells = <1>;
2321 imgsys1_dip_nr: clock-controller@15130000 {
2322 compatible = "mediatek,mt8188-imgsys1-dip-nr";
2324 #clock-cells = <1>;
2327 imgsys_wpe1: clock-controller@15220000 {
2328 compatible = "mediatek,mt8188-imgsys-wpe1";
2330 #clock-cells = <1>;
2333 ipesys: clock-controller@15330000 {
2334 compatible = "mediatek,mt8188-ipesys";
2336 #clock-cells = <1>;
2339 imgsys_wpe2: clock-controller@15520000 {
2340 compatible = "mediatek,mt8188-imgsys-wpe2";
2342 #clock-cells = <1>;
2345 imgsys_wpe3: clock-controller@15620000 {
2346 compatible = "mediatek,mt8188-imgsys-wpe3";
2348 #clock-cells = <1>;
2351 camsys: clock-controller@16000000 {
2352 compatible = "mediatek,mt8188-camsys";
2354 #clock-cells = <1>;
2357 camsys_rawa: clock-controller@1604f000 {
2358 compatible = "mediatek,mt8188-camsys-rawa";
2360 #clock-cells = <1>;
2363 camsys_yuva: clock-controller@1606f000 {
2364 compatible = "mediatek,mt8188-camsys-yuva";
2366 #clock-cells = <1>;
2369 camsys_rawb: clock-controller@1608f000 {
2370 compatible = "mediatek,mt8188-camsys-rawb";
2372 #clock-cells = <1>;
2375 camsys_yuvb: clock-controller@160af000 {
2376 compatible = "mediatek,mt8188-camsys-yuvb";
2378 #clock-cells = <1>;
2381 ccusys: clock-controller@17200000 {
2382 compatible = "mediatek,mt8188-ccusys";
2384 #clock-cells = <1>;
2387 video_decoder: video-decoder@18000000 {
2388 compatible = "mediatek,mt8188-vcodec-dec";
2392 #address-cells = <2>;
2393 #size-cells = <2>;
2396 video-codec@10000 {
2397 compatible = "mediatek,mtk-vcodec-lat";
2399 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2400 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
2405 clock-names = "sel", "vdec", "lat", "top";
2416 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>;
2419 video-codec@25000 {
2420 compatible = "mediatek,mtk-vcodec-core";
2422 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2423 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
2428 clock-names = "sel", "vdec", "lat", "top";
2441 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC1>;
2446 compatible = "mediatek,mt8188-smi-larb";
2450 clock-names = "apb", "smi";
2451 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>;
2452 mediatek,larb-id = <SMI_L23_ID>;
2456 vdecsys_soc: clock-controller@1800f000 {
2457 compatible = "mediatek,mt8188-vdecsys-soc";
2459 #clock-cells = <1>;
2463 compatible = "mediatek,mt8188-smi-larb";
2467 clock-names = "apb", "smi";
2468 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC1>;
2469 mediatek,larb-id = <SMI_L21_ID>;
2473 vdecsys: clock-controller@1802f000 {
2474 compatible = "mediatek,mt8188-vdecsys";
2476 #clock-cells = <1>;
2479 vencsys: clock-controller@1a000000 {
2480 compatible = "mediatek,mt8188-vencsys";
2482 #clock-cells = <1>;
2486 compatible = "mediatek,mt8188-smi-larb";
2490 clock-names = "apb", "smi";
2491 power-domains = <&spm MT8188_POWER_DOMAIN_VENC>;
2492 mediatek,larb-id = <SMI_L19_ID>;
2496 video_encoder: video-encoder@1a020000 {
2497 compatible = "mediatek,mt8188-vcodec-enc";
2499 #address-cells = <2>;
2500 #size-cells = <2>;
2501 assigned-clocks = <&topckgen CLK_TOP_VENC>;
2502 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2504 clock-names = "venc_sel";
2517 power-domains = <&spm MT8188_POWER_DOMAIN_VENC>;
2521 jpeg_encoder: jpeg-encoder@1a030000 {
2522 compatible = "mediatek,mt8188-jpgenc", "mediatek,mtk-jpgenc";
2525 clock-names = "jpgenc";
2531 power-domains = <&spm MT8188_POWER_DOMAIN_VENC>;
2534 jpeg_decoder: jpeg-decoder@1a040000 {
2535 compatible = "mediatek,mt8188-jpgdec", "mediatek,mt2701-jpgdec";
2539 clock-names = "jpgdec-smi", "jpgdec";
2547 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>;
2551 compatible = "mediatek,mt8188-disp-ovl", "mediatek,mt8195-disp-ovl";
2556 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2557 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
2560 #address-cells = <1>;
2561 #size-cells = <0>;
2571 remote-endpoint = <&rdma0_in>;
2578 compatible = "mediatek,mt8188-disp-rdma", "mediatek,mt8195-disp-rdma";
2583 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2584 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
2587 #address-cells = <1>;
2588 #size-cells = <0>;
2593 remote-endpoint = <&ovl0_out>;
2600 remote-endpoint = <&color0_in>;
2607 compatible = "mediatek,mt8188-disp-color", "mediatek,mt8173-disp-color";
2611 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2612 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
2615 #address-cells = <1>;
2616 #size-cells = <0>;
2621 remote-endpoint = <&rdma0_out>;
2628 remote-endpoint = <&ccorr0_in>;
2635 compatible = "mediatek,mt8188-disp-ccorr", "mediatek,mt8192-disp-ccorr";
2639 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2640 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
2643 #address-cells = <1>;
2644 #size-cells = <0>;
2649 remote-endpoint = <&color0_out>;
2656 remote-endpoint = <&aal0_in>;
2663 compatible = "mediatek,mt8188-disp-aal", "mediatek,mt8183-disp-aal";
2667 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2668 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
2671 #address-cells = <1>;
2672 #size-cells = <0>;
2677 remote-endpoint = <&ccorr0_out>;
2684 remote-endpoint = <&gamma0_in>;
2691 compatible = "mediatek,mt8188-disp-gamma", "mediatek,mt8195-disp-gamma";
2695 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2696 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
2699 #address-cells = <1>;
2700 #size-cells = <0>;
2705 remote-endpoint = <&aal0_out>;
2717 compatible = "mediatek,mt8188-disp-dither", "mediatek,mt8183-disp-dither";
2721 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2722 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
2725 #address-cells = <1>;
2726 #size-cells = <0>;
2741 compatible = "mediatek,mt8188-dsi";
2746 clock-names = "engine", "digital", "hs";
2749 phy-names = "dphy";
2750 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2756 compatible = "mediatek,mt8188-disp-dsc", "mediatek,mt8195-disp-dsc";
2760 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2761 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;
2765 compatible = "mediatek,mt8188-dsi";
2770 clock-names = "engine", "digital", "hs";
2773 phy-names = "dphy";
2774 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2780 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";
2784 clock-names = "merge", "merge_async";
2786 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2787 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
2790 dp_intf0: dp-intf@1c015000 {
2791 compatible = "mediatek,mt8188-dp-intf";
2796 clock-names = "pixel", "engine", "pll";
2798 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2803 compatible = "mediatek,mt8188-disp-mutex";
2807 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2808 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>;
2809 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
2813 compatible = "mediatek,mt8188-disp-postmask",
2814 "mediatek,mt8192-disp-postmask";
2818 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2819 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>;
2822 #address-cells = <1>;
2823 #size-cells = <0>;
2838 compatible = "mediatek,mt8188-vdosys0", "syscon";
2840 #clock-cells = <1>;
2841 #reset-cells = <1>;
2843 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xd000 0x1000>;
2847 compatible = "mediatek,mt8188-smi-larb";
2851 clock-names = "apb", "smi";
2852 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2853 mediatek,larb-id = <SMI_L0_ID>;
2858 compatible = "mediatek,mt8188-smi-larb";
2862 clock-names = "apb", "smi";
2863 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2864 mediatek,larb-id = <SMI_L1_ID>;
2869 compatible = "mediatek,mt8188-smi-common-vdo";
2873 clock-names = "apb", "smi";
2874 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2878 compatible = "mediatek,mt8188-iommu-vdo";
2881 clock-names = "bclk";
2883 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
2884 #iommu-cells = <1>;
2889 compatible = "mediatek,mt8188-vdosys1", "syscon";
2891 #clock-cells = <1>;
2892 #reset-cells = <1>;
2894 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0 0x1000>;
2898 compatible = "mediatek,mt8188-disp-mutex";
2902 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2903 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>;
2904 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
2908 compatible = "mediatek,mt8188-smi-larb";
2912 clock-names = "apb", "smi";
2913 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2914 mediatek,larb-id = <SMI_L2_ID>;
2919 compatible = "mediatek,mt8188-smi-larb";
2923 clock-names = "apb", "smi";
2924 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2925 mediatek,larb-id = <SMI_L3_ID>;
2930 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
2935 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2936 #dma-cells = <1>;
2937 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
2941 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
2946 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2947 #dma-cells = <1>;
2948 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>;
2952 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
2957 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2958 #dma-cells = <1>;
2959 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>;
2963 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
2968 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2969 #dma-cells = <1>;
2970 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>;
2974 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
2979 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2980 #dma-cells = <1>;
2981 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>;
2985 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
2990 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
2991 #dma-cells = <1>;
2992 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>;
2996 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
3001 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3002 #dma-cells = <1>;
3003 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>;
3007 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
3012 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3013 #dma-cells = <1>;
3014 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>;
3018 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";
3022 clock-names = "merge", "merge_async";
3024 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3026 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>;
3027 mediatek,merge-mute;
3031 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";
3035 clock-names = "merge", "merge_async";
3037 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3039 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>;
3040 mediatek,merge-mute;
3044 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";
3048 clock-names = "merge", "merge_async";
3050 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3052 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>;
3053 mediatek,merge-mute;
3057 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";
3061 clock-names = "merge", "merge_async";
3063 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3065 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>;
3066 mediatek,merge-mute;
3070 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";
3074 clock-names = "merge", "merge_async";
3076 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3078 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>;
3079 mediatek,merge-fifo-en;
3082 dp_intf1: dp-intf@1c113000 {
3083 compatible = "mediatek,mt8188-dp-intf";
3088 clock-names = "pixel", "engine", "pll";
3090 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3095 compatible = "mediatek,mt8188-disp-ethdr", "mediatek,mt8195-disp-ethdr";
3103 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3119 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3126 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3133 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
3143 compatible = "mediatek,mt8188-disp-padding";
3146 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3147 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>;
3151 compatible = "mediatek,mt8188-disp-padding";
3154 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3155 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xe000 0x1000>;
3159 compatible = "mediatek,mt8188-disp-padding";
3162 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3163 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xf000 0x1000>;
3167 compatible = "mediatek,mt8188-disp-padding";
3170 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3171 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x0000 0x1000>;
3175 compatible = "mediatek,mt8188-disp-padding";
3178 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3179 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x1000 0x1000>;
3183 compatible = "mediatek,mt8188-disp-padding";
3186 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3187 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x2000 0x1000>;
3191 compatible = "mediatek,mt8188-disp-padding";
3194 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3195 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x3000 0x1000>;
3199 compatible = "mediatek,mt8188-disp-padding";
3202 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
3203 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x4000 0x1000>;
3206 edp_tx: edp-tx@1c500000 {
3207 compatible = "mediatek,mt8188-edp-tx";
3210 nvmem-cells = <&dp_calib_data>;
3211 nvmem-cell-names = "dp_calibration_data";
3212 power-domains = <&spm MT8188_POWER_DOMAIN_EDP_TX>;
3213 max-linkrate-mhz = <8100>;
3217 dp_tx: dp-tx@1c600000 {
3218 compatible = "mediatek,mt8188-dp-tx";
3221 nvmem-cells = <&dp_calib_data>;
3222 nvmem-cell-names = "dp_calibration_data";
3223 power-domains = <&spm MT8188_POWER_DOMAIN_DP_TX>;
3224 max-linkrate-mhz = <5400>;