Lines Matching +full:1 +full:c600000
58 #address-cells = <1>;
190 performance-domains = <&performance 1>;
209 performance-domains = <&performance 1>;
932 #performance-domain-cells = <1>;
938 #redistributor-regions = <1>;
950 ppi_cluster1: interrupt-partition-1 {
959 #clock-cells = <1>;
965 #clock-cells = <1>;
966 #reset-cells = <1>;
972 #clock-cells = <1>;
1000 #address-cells = <1>;
1002 #power-domain-cells = <1>;
1007 #address-cells = <1>;
1009 #power-domain-cells = <1>;
1017 #address-cells = <1>;
1019 #power-domain-cells = <1>;
1078 #address-cells = <1>;
1080 #power-domain-cells = <1>;
1097 #address-cells = <1>;
1099 #power-domain-cells = <1>;
1121 #address-cells = <1>;
1123 #power-domain-cells = <1>;
1142 #address-cells = <1>;
1144 #power-domain-cells = <1>;
1157 #address-cells = <1>;
1159 #power-domain-cells = <1>;
1195 #address-cells = <1>;
1197 #power-domain-cells = <1>;
1271 #address-cells = <1>;
1273 #power-domain-cells = <1>;
1278 #address-cells = <1>;
1280 #power-domain-cells = <1>;
1322 #reset-cells = <1>;
1328 #clock-cells = <1>;
1364 #iommu-cells = <1>;
1485 #clock-cells = <1>;
1529 #io-channel-cells = <1>;
1536 #clock-cells = <1>;
1541 #address-cells = <1>;
1559 nvmem-cell-names = "lvts-calib-data-1";
1560 #thermal-sensor-cells = <1>;
1587 #address-cells = <1>;
1600 #address-cells = <1>;
1613 #address-cells = <1>;
1626 #address-cells = <1>;
1639 #address-cells = <1>;
1682 #address-cells = <1>;
1802 nvmem-cell-names = "lvts-calib-data-1";
1803 #thermal-sensor-cells = <1>;
1811 clock-div = <1>;
1815 #address-cells = <1>;
1825 clock-div = <1>;
1829 #address-cells = <1>;
1839 clock-div = <1>;
1843 #address-cells = <1>;
1851 #clock-cells = <1>;
1912 #interrupt-cells = <1>;
1914 interrupt-map = <0 0 0 1 &pcie_intc 0>,
1915 <0 0 0 2 &pcie_intc 1>,
1935 #interrupt-cells = <1>;
1949 #address-cells = <1>;
1957 #address-cells = <1>;
1958 #size-cells = <1>;
1966 #phy-cells = <1>;
1995 clock-div = <1>;
1999 #address-cells = <1>;
2009 clock-div = <1>;
2013 #address-cells = <1>;
2021 #clock-cells = <1>;
2026 #address-cells = <1>;
2027 #size-cells = <1>;
2036 #phy-cells = <1>;
2042 #address-cells = <1>;
2043 #size-cells = <1>;
2052 #phy-cells = <1>;
2060 #phy-cells = <1>;
2066 #address-cells = <1>;
2067 #size-cells = <1>;
2076 #phy-cells = <1>;
2085 clock-div = <1>;
2089 #address-cells = <1>;
2099 clock-div = <1>;
2103 #address-cells = <1>;
2111 #clock-cells = <1>;
2117 #address-cells = <1>;
2118 #size-cells = <1>;
2120 dp_calib_data: dp-calib@1a0 {
2124 lvts_efuse_data1: lvts1-calib@1ac {
2158 #clock-cells = <1>;
2164 #clock-cells = <1>;
2194 #iommu-cells = <1>;
2201 #clock-cells = <1>;
2207 #clock-cells = <1>;
2224 #clock-cells = <1>;
2252 #clock-cells = <1>;
2258 #clock-cells = <1>;
2264 #clock-cells = <1>;
2270 #clock-cells = <1>;
2276 #clock-cells = <1>;
2282 #clock-cells = <1>;
2288 #clock-cells = <1>;
2294 #clock-cells = <1>;
2300 #clock-cells = <1>;
2306 #clock-cells = <1>;
2312 #clock-cells = <1>;
2318 #clock-cells = <1>;
2324 #clock-cells = <1>;
2399 #clock-cells = <1>;
2416 #clock-cells = <1>;
2419 vencsys: clock-controller@1a000000 {
2422 #clock-cells = <1>;
2425 larb19: smi@1a010000 {
2436 video_encoder: video-encoder@1a020000 {
2461 jpeg_encoder: jpeg-encoder@1a030000 {
2474 jpeg_decoder: jpeg-decoder@1a040000 {
2490 ovl0: ovl@1c000000 {
2500 rdma0: rdma@1c002000 {
2510 color0: color@1c003000 {
2519 ccorr0: ccorr@1c004000 {
2528 aal0: aal@1c005000 {
2537 gamma0: gamma@1c006000 {
2546 dither0: dither@1c007000 {
2555 disp_dsi0: dsi@1c008000 {
2570 disp_dsi1: dsi@1c012000 {
2585 dp_intf0: dp-intf@1c015000 {
2597 mutex0: mutex@1c016000 {
2607 postmask0: postmask@1c01a000 {
2617 vdosys0: syscon@1c01d000 {
2620 #clock-cells = <1>;
2621 #reset-cells = <1>;
2626 larb0: smi@1c022000 {
2637 larb1: smi@1c023000 {
2648 vdo_smi_common: smi@1c024000 {
2657 vdo_iommu: iommu@1c028000 {
2664 #iommu-cells = <1>;
2668 vdosys1: syscon@1c100000 {
2671 #clock-cells = <1>;
2672 #reset-cells = <1>;
2673 mboxes = <&gce0 1 CMDQ_THR_PRIO_4>;
2677 mutex1: mutex@1c101000 {
2687 larb2: smi@1c102000 {
2698 larb3: smi@1c103000 {
2709 vdo1_rdma0: rdma@1c104000 {
2716 #dma-cells = <1>;
2720 vdo1_rdma1: rdma@1c105000 {
2727 #dma-cells = <1>;
2731 vdo1_rdma2: rdma@1c106000 {
2738 #dma-cells = <1>;
2742 vdo1_rdma3: rdma@1c107000 {
2749 #dma-cells = <1>;
2753 vdo1_rdma4: rdma@1c108000 {
2760 #dma-cells = <1>;
2764 vdo1_rdma5: rdma@1c109000 {
2771 #dma-cells = <1>;
2775 vdo1_rdma6: rdma@1c10a000 {
2782 #dma-cells = <1>;
2786 vdo1_rdma7: rdma@1c10b000 {
2793 #dma-cells = <1>;
2797 merge1: merge@1c10c000 {
2810 merge2: merge@1c10d000 {
2823 merge3: merge@1c10e000 {
2836 merge4: merge@1c10f000 {
2849 merge5: merge@1c110000 {
2862 dp_intf1: dp-intf@1c113000 {
2874 ethdr0: ethdr@1c114000 {
2922 padding0: padding@1c11d000 {
2930 padding1: padding@1c11e000 {
2938 padding2: padding@1c11f000 {
2946 padding3: padding@1c120000 {
2954 padding4: padding@1c121000 {
2962 padding5: padding@1c122000 {
2970 padding6: padding@1c123000 {
2978 padding7: padding@1c124000 {
2986 edp_tx: edp-tx@1c500000 {
2997 dp_tx: dp-tx@1c600000 {