Lines Matching +full:mt8195 +full:- +full:efuse
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
6 /dts-v1/;
7 #include <dt-bindings/clock/mt8186-clk.h>
8 #include <dt-bindings/gce/mt8186-gce.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/memory/mt8186-memory-port.h>
12 #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
13 #include <dt-bindings/power/mt8186-power.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/reset/mt8186-resets.h>
16 #include <dt-bindings/thermal/thermal.h>
17 #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
21 interrupt-parent = <&gic>;
22 #address-cells = <2>;
23 #size-cells = <2>;
27 ovl-2l0 = &ovl_2l0;
33 compatible = "mediatek,mt8186-cci";
36 clock-names = "cci", "intermediate";
37 operating-points-v2 = <&cci_opp>;
40 cci_opp: opp-table-cci {
41 compatible = "operating-points-v2";
42 opp-shared;
44 cci_opp_0: opp-500000000 {
45 opp-hz = /bits/ 64 <500000000>;
46 opp-microvolt = <600000>;
49 cci_opp_1: opp-560000000 {
50 opp-hz = /bits/ 64 <560000000>;
51 opp-microvolt = <675000>;
54 cci_opp_2: opp-612000000 {
55 opp-hz = /bits/ 64 <612000000>;
56 opp-microvolt = <693750>;
59 cci_opp_3: opp-682000000 {
60 opp-hz = /bits/ 64 <682000000>;
61 opp-microvolt = <718750>;
64 cci_opp_4: opp-752000000 {
65 opp-hz = /bits/ 64 <752000000>;
66 opp-microvolt = <743750>;
69 cci_opp_5: opp-822000000 {
70 opp-hz = /bits/ 64 <822000000>;
71 opp-microvolt = <768750>;
74 cci_opp_6: opp-875000000 {
75 opp-hz = /bits/ 64 <875000000>;
76 opp-microvolt = <781250>;
79 cci_opp_7: opp-927000000 {
80 opp-hz = /bits/ 64 <927000000>;
81 opp-microvolt = <800000>;
84 cci_opp_8: opp-980000000 {
85 opp-hz = /bits/ 64 <980000000>;
86 opp-microvolt = <818750>;
89 cci_opp_9: opp-1050000000 {
90 opp-hz = /bits/ 64 <1050000000>;
91 opp-microvolt = <843750>;
94 cci_opp_10: opp-1120000000 {
95 opp-hz = /bits/ 64 <1120000000>;
96 opp-microvolt = <862500>;
99 cci_opp_11: opp-1155000000 {
100 opp-hz = /bits/ 64 <1155000000>;
101 opp-microvolt = <887500>;
104 cci_opp_12: opp-1190000000 {
105 opp-hz = /bits/ 64 <1190000000>;
106 opp-microvolt = <906250>;
109 cci_opp_13: opp-1260000000 {
110 opp-hz = /bits/ 64 <1260000000>;
111 opp-microvolt = <950000>;
114 cci_opp_14: opp-1330000000 {
115 opp-hz = /bits/ 64 <1330000000>;
116 opp-microvolt = <993750>;
119 cci_opp_15: opp-1400000000 {
120 opp-hz = /bits/ 64 <1400000000>;
121 opp-microvolt = <1031250>;
125 cluster0_opp: opp-table-cluster0 {
126 compatible = "operating-points-v2";
127 opp-shared;
129 opp-500000000 {
130 opp-hz = /bits/ 64 <500000000>;
131 opp-microvolt = <600000>;
132 required-opps = <&cci_opp_0>;
135 opp-774000000 {
136 opp-hz = /bits/ 64 <774000000>;
137 opp-microvolt = <675000>;
138 required-opps = <&cci_opp_1>;
141 opp-875000000 {
142 opp-hz = /bits/ 64 <875000000>;
143 opp-microvolt = <700000>;
144 required-opps = <&cci_opp_2>;
147 opp-975000000 {
148 opp-hz = /bits/ 64 <975000000>;
149 opp-microvolt = <725000>;
150 required-opps = <&cci_opp_3>;
153 opp-1075000000 {
154 opp-hz = /bits/ 64 <1075000000>;
155 opp-microvolt = <750000>;
156 required-opps = <&cci_opp_4>;
159 opp-1175000000 {
160 opp-hz = /bits/ 64 <1175000000>;
161 opp-microvolt = <775000>;
162 required-opps = <&cci_opp_5>;
165 opp-1275000000 {
166 opp-hz = /bits/ 64 <1275000000>;
167 opp-microvolt = <800000>;
168 required-opps = <&cci_opp_6>;
171 opp-1375000000 {
172 opp-hz = /bits/ 64 <1375000000>;
173 opp-microvolt = <825000>;
174 required-opps = <&cci_opp_7>;
177 opp-1500000000 {
178 opp-hz = /bits/ 64 <1500000000>;
179 opp-microvolt = <856250>;
180 required-opps = <&cci_opp_8>;
183 opp-1618000000 {
184 opp-hz = /bits/ 64 <1618000000>;
185 opp-microvolt = <875000>;
186 required-opps = <&cci_opp_9>;
189 opp-1666000000 {
190 opp-hz = /bits/ 64 <1666000000>;
191 opp-microvolt = <900000>;
192 required-opps = <&cci_opp_10>;
195 opp-1733000000 {
196 opp-hz = /bits/ 64 <1733000000>;
197 opp-microvolt = <925000>;
198 required-opps = <&cci_opp_11>;
201 opp-1800000000 {
202 opp-hz = /bits/ 64 <1800000000>;
203 opp-microvolt = <950000>;
204 required-opps = <&cci_opp_12>;
207 opp-1866000000 {
208 opp-hz = /bits/ 64 <1866000000>;
209 opp-microvolt = <981250>;
210 required-opps = <&cci_opp_13>;
213 opp-1933000000 {
214 opp-hz = /bits/ 64 <1933000000>;
215 opp-microvolt = <1006250>;
216 required-opps = <&cci_opp_14>;
219 opp-2000000000 {
220 opp-hz = /bits/ 64 <2000000000>;
221 opp-microvolt = <1031250>;
222 required-opps = <&cci_opp_15>;
226 cluster1_opp: opp-table-cluster1 {
227 compatible = "operating-points-v2";
228 opp-shared;
230 opp-774000000 {
231 opp-hz = /bits/ 64 <774000000>;
232 opp-microvolt = <675000>;
233 required-opps = <&cci_opp_0>;
236 opp-835000000 {
237 opp-hz = /bits/ 64 <835000000>;
238 opp-microvolt = <693750>;
239 required-opps = <&cci_opp_1>;
242 opp-919000000 {
243 opp-hz = /bits/ 64 <919000000>;
244 opp-microvolt = <718750>;
245 required-opps = <&cci_opp_2>;
248 opp-1002000000 {
249 opp-hz = /bits/ 64 <1002000000>;
250 opp-microvolt = <743750>;
251 required-opps = <&cci_opp_3>;
254 opp-1085000000 {
255 opp-hz = /bits/ 64 <1085000000>;
256 opp-microvolt = <775000>;
257 required-opps = <&cci_opp_4>;
260 opp-1169000000 {
261 opp-hz = /bits/ 64 <1169000000>;
262 opp-microvolt = <800000>;
263 required-opps = <&cci_opp_5>;
266 opp-1308000000 {
267 opp-hz = /bits/ 64 <1308000000>;
268 opp-microvolt = <843750>;
269 required-opps = <&cci_opp_6>;
272 opp-1419000000 {
273 opp-hz = /bits/ 64 <1419000000>;
274 opp-microvolt = <875000>;
275 required-opps = <&cci_opp_7>;
278 opp-1530000000 {
279 opp-hz = /bits/ 64 <1530000000>;
280 opp-microvolt = <912500>;
281 required-opps = <&cci_opp_8>;
284 opp-1670000000 {
285 opp-hz = /bits/ 64 <1670000000>;
286 opp-microvolt = <956250>;
287 required-opps = <&cci_opp_9>;
290 opp-1733000000 {
291 opp-hz = /bits/ 64 <1733000000>;
292 opp-microvolt = <981250>;
293 required-opps = <&cci_opp_10>;
296 opp-1796000000 {
297 opp-hz = /bits/ 64 <1796000000>;
298 opp-microvolt = <1012500>;
299 required-opps = <&cci_opp_11>;
302 opp-1860000000 {
303 opp-hz = /bits/ 64 <1860000000>;
304 opp-microvolt = <1037500>;
305 required-opps = <&cci_opp_12>;
308 opp-1923000000 {
309 opp-hz = /bits/ 64 <1923000000>;
310 opp-microvolt = <1062500>;
311 required-opps = <&cci_opp_13>;
314 cluster1_opp_14: opp-1986000000 {
315 opp-hz = /bits/ 64 <1986000000>;
316 opp-microvolt = <1093750>;
317 required-opps = <&cci_opp_14>;
320 cluster1_opp_15: opp-2050000000 {
321 opp-hz = /bits/ 64 <2050000000>;
322 opp-microvolt = <1118750>;
323 required-opps = <&cci_opp_15>;
328 #address-cells = <1>;
329 #size-cells = <0>;
331 cpu-map {
369 compatible = "arm,cortex-a55";
371 enable-method = "psci";
372 clock-frequency = <2000000000>;
375 clock-names = "cpu", "intermediate";
376 operating-points-v2 = <&cluster0_opp>;
377 dynamic-power-coefficient = <84>;
378 capacity-dmips-mhz = <382>;
379 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
380 i-cache-size = <32768>;
381 i-cache-line-size = <64>;
382 i-cache-sets = <128>;
383 d-cache-size = <32768>;
384 d-cache-line-size = <64>;
385 d-cache-sets = <128>;
386 next-level-cache = <&l2_0>;
387 #cooling-cells = <2>;
393 compatible = "arm,cortex-a55";
395 enable-method = "psci";
396 clock-frequency = <2000000000>;
399 clock-names = "cpu", "intermediate";
400 operating-points-v2 = <&cluster0_opp>;
401 dynamic-power-coefficient = <84>;
402 capacity-dmips-mhz = <382>;
403 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
404 i-cache-size = <32768>;
405 i-cache-line-size = <64>;
406 i-cache-sets = <128>;
407 d-cache-size = <32768>;
408 d-cache-line-size = <64>;
409 d-cache-sets = <128>;
410 next-level-cache = <&l2_0>;
411 #cooling-cells = <2>;
417 compatible = "arm,cortex-a55";
419 enable-method = "psci";
420 clock-frequency = <2000000000>;
423 clock-names = "cpu", "intermediate";
424 operating-points-v2 = <&cluster0_opp>;
425 dynamic-power-coefficient = <84>;
426 capacity-dmips-mhz = <382>;
427 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
428 i-cache-size = <32768>;
429 i-cache-line-size = <64>;
430 i-cache-sets = <128>;
431 d-cache-size = <32768>;
432 d-cache-line-size = <64>;
433 d-cache-sets = <128>;
434 next-level-cache = <&l2_0>;
435 #cooling-cells = <2>;
441 compatible = "arm,cortex-a55";
443 enable-method = "psci";
444 clock-frequency = <2000000000>;
447 clock-names = "cpu", "intermediate";
448 operating-points-v2 = <&cluster0_opp>;
449 dynamic-power-coefficient = <84>;
450 capacity-dmips-mhz = <382>;
451 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
452 i-cache-size = <32768>;
453 i-cache-line-size = <64>;
454 i-cache-sets = <128>;
455 d-cache-size = <32768>;
456 d-cache-line-size = <64>;
457 d-cache-sets = <128>;
458 next-level-cache = <&l2_0>;
459 #cooling-cells = <2>;
465 compatible = "arm,cortex-a55";
467 enable-method = "psci";
468 clock-frequency = <2000000000>;
471 clock-names = "cpu", "intermediate";
472 operating-points-v2 = <&cluster0_opp>;
473 dynamic-power-coefficient = <84>;
474 capacity-dmips-mhz = <382>;
475 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
476 i-cache-size = <32768>;
477 i-cache-line-size = <64>;
478 i-cache-sets = <128>;
479 d-cache-size = <32768>;
480 d-cache-line-size = <64>;
481 d-cache-sets = <128>;
482 next-level-cache = <&l2_0>;
483 #cooling-cells = <2>;
489 compatible = "arm,cortex-a55";
491 enable-method = "psci";
492 clock-frequency = <2000000000>;
495 clock-names = "cpu", "intermediate";
496 operating-points-v2 = <&cluster0_opp>;
497 dynamic-power-coefficient = <84>;
498 capacity-dmips-mhz = <382>;
499 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
500 i-cache-size = <32768>;
501 i-cache-line-size = <64>;
502 i-cache-sets = <128>;
503 d-cache-size = <32768>;
504 d-cache-line-size = <64>;
505 d-cache-sets = <128>;
506 next-level-cache = <&l2_0>;
507 #cooling-cells = <2>;
513 compatible = "arm,cortex-a76";
515 enable-method = "psci";
516 clock-frequency = <2050000000>;
519 clock-names = "cpu", "intermediate";
520 operating-points-v2 = <&cluster1_opp>;
521 dynamic-power-coefficient = <335>;
522 capacity-dmips-mhz = <1024>;
523 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
524 i-cache-size = <65536>;
525 i-cache-line-size = <64>;
526 i-cache-sets = <256>;
527 d-cache-size = <65536>;
528 d-cache-line-size = <64>;
529 d-cache-sets = <256>;
530 next-level-cache = <&l2_1>;
531 #cooling-cells = <2>;
537 compatible = "arm,cortex-a76";
539 enable-method = "psci";
540 clock-frequency = <2050000000>;
543 clock-names = "cpu", "intermediate";
544 operating-points-v2 = <&cluster1_opp>;
545 dynamic-power-coefficient = <335>;
546 capacity-dmips-mhz = <1024>;
547 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
548 i-cache-size = <65536>;
549 i-cache-line-size = <64>;
550 i-cache-sets = <256>;
551 d-cache-size = <65536>;
552 d-cache-line-size = <64>;
553 d-cache-sets = <256>;
554 next-level-cache = <&l2_1>;
555 #cooling-cells = <2>;
559 idle-states {
560 entry-method = "psci";
562 cpu_ret_l: cpu-retention-l {
563 compatible = "arm,idle-state";
564 arm,psci-suspend-param = <0x00010001>;
565 local-timer-stop;
566 entry-latency-us = <50>;
567 exit-latency-us = <100>;
568 min-residency-us = <1600>;
571 cpu_ret_b: cpu-retention-b {
572 compatible = "arm,idle-state";
573 arm,psci-suspend-param = <0x00010001>;
574 local-timer-stop;
575 entry-latency-us = <50>;
576 exit-latency-us = <100>;
577 min-residency-us = <1400>;
580 cpu_off_l: cpu-off-l {
581 compatible = "arm,idle-state";
582 arm,psci-suspend-param = <0x01010001>;
583 local-timer-stop;
584 entry-latency-us = <100>;
585 exit-latency-us = <250>;
586 min-residency-us = <2100>;
589 cpu_off_b: cpu-off-b {
590 compatible = "arm,idle-state";
591 arm,psci-suspend-param = <0x01010001>;
592 local-timer-stop;
593 entry-latency-us = <100>;
594 exit-latency-us = <250>;
595 min-residency-us = <1900>;
599 l2_0: l2-cache0 {
601 cache-level = <2>;
602 cache-size = <131072>;
603 cache-line-size = <64>;
604 cache-sets = <512>;
605 next-level-cache = <&l3_0>;
606 cache-unified;
609 l2_1: l2-cache1 {
611 cache-level = <2>;
612 cache-size = <262144>;
613 cache-line-size = <64>;
614 cache-sets = <512>;
615 next-level-cache = <&l3_0>;
616 cache-unified;
619 l3_0: l3-cache {
621 cache-level = <3>;
622 cache-size = <1048576>;
623 cache-line-size = <64>;
624 cache-sets = <1024>;
625 cache-unified;
629 clk13m: fixed-factor-clock-13m {
630 compatible = "fixed-factor-clock";
631 #clock-cells = <0>;
633 clock-div = <2>;
634 clock-mult = <1>;
635 clock-output-names = "clk13m";
638 clk26m: oscillator-26m {
639 compatible = "fixed-clock";
640 #clock-cells = <0>;
641 clock-frequency = <26000000>;
642 clock-output-names = "clk26m";
645 clk32k: oscillator-32k {
646 compatible = "fixed-clock";
647 #clock-cells = <0>;
648 clock-frequency = <32768>;
649 clock-output-names = "clk32k";
652 gpu_opp_table: opp-table-gpu {
653 compatible = "operating-points-v2";
655 opp-299000000 {
656 opp-hz = /bits/ 64 <299000000>;
657 opp-microvolt = <612500>;
658 opp-supported-hw = <0xff>;
661 opp-332000000 {
662 opp-hz = /bits/ 64 <332000000>;
663 opp-microvolt = <625000>;
664 opp-supported-hw = <0xff>;
667 opp-366000000 {
668 opp-hz = /bits/ 64 <366000000>;
669 opp-microvolt = <637500>;
670 opp-supported-hw = <0xff>;
673 opp-400000000 {
674 opp-hz = /bits/ 64 <400000000>;
675 opp-microvolt = <643750>;
676 opp-supported-hw = <0xff>;
679 opp-434000000 {
680 opp-hz = /bits/ 64 <434000000>;
681 opp-microvolt = <656250>;
682 opp-supported-hw = <0xff>;
685 opp-484000000 {
686 opp-hz = /bits/ 64 <484000000>;
687 opp-microvolt = <668750>;
688 opp-supported-hw = <0xff>;
691 opp-535000000 {
692 opp-hz = /bits/ 64 <535000000>;
693 opp-microvolt = <687500>;
694 opp-supported-hw = <0xff>;
697 opp-586000000 {
698 opp-hz = /bits/ 64 <586000000>;
699 opp-microvolt = <700000>;
700 opp-supported-hw = <0xff>;
703 opp-637000000 {
704 opp-hz = /bits/ 64 <637000000>;
705 opp-microvolt = <712500>;
706 opp-supported-hw = <0xff>;
709 opp-690000000 {
710 opp-hz = /bits/ 64 <690000000>;
711 opp-microvolt = <737500>;
712 opp-supported-hw = <0xff>;
715 opp-743000000 {
716 opp-hz = /bits/ 64 <743000000>;
717 opp-microvolt = <756250>;
718 opp-supported-hw = <0xff>;
721 opp-796000000 {
722 opp-hz = /bits/ 64 <796000000>;
723 opp-microvolt = <781250>;
724 opp-supported-hw = <0xff>;
727 opp-850000000 {
728 opp-hz = /bits/ 64 <850000000>;
729 opp-microvolt = <800000>;
730 opp-supported-hw = <0xff>;
733 opp-900000000-3 {
734 opp-hz = /bits/ 64 <900000000>;
735 opp-microvolt = <850000>;
736 opp-supported-hw = <0xcf>;
739 opp-900000000-4 {
740 opp-hz = /bits/ 64 <900000000>;
741 opp-microvolt = <837500>;
742 opp-supported-hw = <0x10>;
745 opp-900000000-5 {
746 opp-hz = /bits/ 64 <900000000>;
747 opp-microvolt = <825000>;
748 opp-supported-hw = <0x20>;
751 opp-950000000-3 {
752 opp-hz = /bits/ 64 <950000000>;
753 opp-microvolt = <900000>;
754 opp-supported-hw = <0xcf>;
757 opp-950000000-4 {
758 opp-hz = /bits/ 64 <950000000>;
759 opp-microvolt = <875000>;
760 opp-supported-hw = <0x10>;
763 opp-950000000-5 {
764 opp-hz = /bits/ 64 <950000000>;
765 opp-microvolt = <850000>;
766 opp-supported-hw = <0x20>;
769 opp-1000000000-3 {
770 opp-hz = /bits/ 64 <1000000000>;
771 opp-microvolt = <950000>;
772 opp-supported-hw = <0xcf>;
775 opp-1000000000-4 {
776 opp-hz = /bits/ 64 <1000000000>;
777 opp-microvolt = <912500>;
778 opp-supported-hw = <0x10>;
781 opp-1000000000-5 {
782 opp-hz = /bits/ 64 <1000000000>;
783 opp-microvolt = <875000>;
784 opp-supported-hw = <0x20>;
788 pmu-a55 {
789 compatible = "arm,cortex-a55-pmu";
790 interrupt-parent = <&gic>;
794 pmu-a76 {
795 compatible = "arm,cortex-a76-pmu";
796 interrupt-parent = <&gic>;
801 compatible = "arm,psci-1.0";
806 compatible = "arm,armv8-timer";
807 interrupt-parent = <&gic>;
815 #address-cells = <2>;
816 #size-cells = <2>;
817 compatible = "simple-bus";
818 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
821 gic: interrupt-controller@c000000 {
822 compatible = "arm,gic-v3";
823 #interrupt-cells = <4>;
824 #redistributor-regions = <1>;
825 interrupt-parent = <&gic>;
826 interrupt-controller;
831 ppi-partitions {
832 ppi_cluster0: interrupt-partition-0 {
836 ppi_cluster1: interrupt-partition-1 {
843 compatible = "mediatek,mt8186-mcusys", "syscon";
845 #clock-cells = <1>;
849 compatible = "mediatek,mt8186-topckgen", "syscon";
851 #clock-cells = <1>;
855 compatible = "mediatek,mt8186-infracfg_ao", "syscon";
857 #clock-cells = <1>;
858 #reset-cells = <1>;
862 compatible = "mediatek,mt8186-pericfg", "syscon";
867 compatible = "mediatek,mt8186-pinctrl";
876 reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb",
878 gpio-controller;
879 #gpio-cells = <2>;
880 gpio-ranges = <&pio 0 0 185>;
881 interrupt-controller;
883 #interrupt-cells = <2>;
887 compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd";
891 spm: power-controller {
892 compatible = "mediatek,mt8186-power-controller";
893 #address-cells = <1>;
894 #size-cells = <0>;
895 #power-domain-cells = <1>;
898 mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 {
901 clock-names = "mfg00";
902 #address-cells = <1>;
903 #size-cells = <0>;
904 #power-domain-cells = <1>;
906 mfg1: power-domain@MT8186_POWER_DOMAIN_MFG1 {
909 #address-cells = <1>;
910 #size-cells = <0>;
911 #power-domain-cells = <1>;
913 power-domain@MT8186_POWER_DOMAIN_MFG2 {
915 #power-domain-cells = <0>;
918 power-domain@MT8186_POWER_DOMAIN_MFG3 {
920 #power-domain-cells = <0>;
925 power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP {
929 clock-names = "subsys-csirx-top0",
930 "subsys-csirx-top1";
931 #power-domain-cells = <0>;
934 power-domain@MT8186_POWER_DOMAIN_SSUSB {
938 clock-names = "sys_ck", "ref_ck";
939 #power-domain-cells = <0>;
942 power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 {
946 clock-names = "sys_ck", "ref_ck";
947 #power-domain-cells = <0>;
950 power-domain@MT8186_POWER_DOMAIN_ADSP_AO {
954 clock-names = "audioadsp",
955 "subsys-adsp-bus";
956 #address-cells = <1>;
957 #size-cells = <0>;
958 #power-domain-cells = <1>;
960 power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA {
962 #address-cells = <1>;
963 #size-cells = <0>;
964 #power-domain-cells = <1>;
966 power-domain@MT8186_POWER_DOMAIN_ADSP_TOP {
969 #power-domain-cells = <0>;
974 power-domain@MT8186_POWER_DOMAIN_CONN_ON {
977 #power-domain-cells = <0>;
980 power-domain@MT8186_POWER_DOMAIN_DIS {
988 clock-names = "disp", "mdp",
989 "subsys-smi-infra",
990 "subsys-smi-common",
991 "subsys-smi-gals",
992 "subsys-smi-iommu";
994 #address-cells = <1>;
995 #size-cells = <0>;
996 #power-domain-cells = <1>;
998 power-domain@MT8186_POWER_DOMAIN_VDEC {
1002 clock-names = "vdec0", "larb";
1004 #power-domain-cells = <0>;
1007 power-domain@MT8186_POWER_DOMAIN_CAM {
1016 clock-names = "cam0", "cam1", "cam2",
1018 "subsys-cam-tm",
1019 "subsys-cam-top";
1021 #address-cells = <1>;
1022 #size-cells = <0>;
1023 #power-domain-cells = <1>;
1025 power-domain@MT8186_POWER_DOMAIN_CAM_RAWB {
1027 #power-domain-cells = <0>;
1030 power-domain@MT8186_POWER_DOMAIN_CAM_RAWA {
1032 #power-domain-cells = <0>;
1036 power-domain@MT8186_POWER_DOMAIN_IMG {
1040 clock-names = "gals", "subsys-img-top";
1042 #address-cells = <1>;
1043 #size-cells = <0>;
1044 #power-domain-cells = <1>;
1046 power-domain@MT8186_POWER_DOMAIN_IMG2 {
1048 #power-domain-cells = <0>;
1052 power-domain@MT8186_POWER_DOMAIN_IPE {
1059 clock-names = "subsys-ipe-top",
1060 "subsys-ipe-larb0",
1061 "subsys-ipe-larb1",
1062 "subsys-ipe-smi",
1063 "subsys-ipe-gals";
1065 #power-domain-cells = <0>;
1068 power-domain@MT8186_POWER_DOMAIN_VENC {
1072 clock-names = "venc0", "subsys-larb";
1074 #power-domain-cells = <0>;
1077 power-domain@MT8186_POWER_DOMAIN_WPE {
1082 clock-names = "wpe0",
1083 "subsys-larb-ck",
1084 "subsys-larb-pclk";
1086 #power-domain-cells = <0>;
1093 compatible = "mediatek,mt8186-wdt";
1094 mediatek,disable-extrst;
1096 #reset-cells = <1>;
1100 compatible = "mediatek,mt8186-apmixedsys", "syscon";
1102 #clock-cells = <1>;
1106 compatible = "mediatek,mt8186-pwrap", "syscon";
1108 reg-names = "pwrap";
1112 clock-names = "spi", "wrap";
1116 compatible = "mediatek,mt8186-spmi", "mediatek,mt8195-spmi";
1118 reg-names = "pmif", "spmimst";
1122 clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux";
1123 assigned-clocks = <&topckgen CLK_TOP_SPMI_MST>;
1124 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
1131 compatible = "mediatek,mt8186-timer",
1132 "mediatek,mt6765-timer";
1139 compatible = "mediatek,mt8186-gce";
1142 clock-names = "gce";
1144 #mbox-cells = <2>;
1148 compatible = "mediatek,mt8186-scp";
1151 reg-names = "sram", "cfg";
1156 compatible = "mediatek,mt8186-dsp";
1159 reg-names = "cfg", "sram", "sec", "bus";
1161 clock-names = "audiodsp", "adsp_bus";
1162 assigned-clocks = <&topckgen CLK_TOP_AUDIODSP>,
1164 assigned-clock-parents = <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>;
1165 mbox-names = "rx", "tx";
1167 power-domains = <&spm MT8186_POWER_DOMAIN_ADSP_TOP>;
1172 compatible = "mediatek,mt8186-adsp-mbox";
1173 #mbox-cells = <0>;
1179 compatible = "mediatek,mt8186-adsp-mbox";
1180 #mbox-cells = <0>;
1186 compatible = "mediatek,mt8186-nor";
1192 clock-names = "spi", "sf", "axi", "axi_s";
1193 assigned-clocks = <&topckgen CLK_TOP_SPINOR>;
1194 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>;
1200 compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc";
1202 #io-channel-cells = <1>;
1204 clock-names = "main";
1208 compatible = "mediatek,mt8186-uart",
1209 "mediatek,mt6577-uart";
1213 clock-names = "baud", "bus";
1218 compatible = "mediatek,mt8186-uart",
1219 "mediatek,mt6577-uart";
1223 clock-names = "baud", "bus";
1228 compatible = "mediatek,mt8186-i2c";
1234 clock-names = "main", "dma";
1235 clock-div = <1>;
1236 #address-cells = <1>;
1237 #size-cells = <0>;
1242 compatible = "mediatek,mt8186-i2c";
1248 clock-names = "main", "dma";
1249 clock-div = <1>;
1250 #address-cells = <1>;
1251 #size-cells = <0>;
1256 compatible = "mediatek,mt8186-i2c";
1262 clock-names = "main", "dma";
1263 clock-div = <1>;
1264 #address-cells = <1>;
1265 #size-cells = <0>;
1270 compatible = "mediatek,mt8186-i2c";
1276 clock-names = "main", "dma";
1277 clock-div = <1>;
1278 #address-cells = <1>;
1279 #size-cells = <0>;
1284 compatible = "mediatek,mt8186-i2c";
1290 clock-names = "main", "dma";
1291 clock-div = <1>;
1292 #address-cells = <1>;
1293 #size-cells = <0>;
1298 compatible = "mediatek,mt8186-i2c";
1304 clock-names = "main", "dma";
1305 clock-div = <1>;
1306 #address-cells = <1>;
1307 #size-cells = <0>;
1312 compatible = "mediatek,mt8186-i2c";
1318 clock-names = "main", "dma";
1319 clock-div = <1>;
1320 #address-cells = <1>;
1321 #size-cells = <0>;
1326 compatible = "mediatek,mt8186-i2c";
1332 clock-names = "main", "dma";
1333 clock-div = <1>;
1334 #address-cells = <1>;
1335 #size-cells = <0>;
1340 compatible = "mediatek,mt8186-i2c";
1346 clock-names = "main", "dma";
1347 clock-div = <1>;
1348 #address-cells = <1>;
1349 #size-cells = <0>;
1354 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1355 #address-cells = <1>;
1356 #size-cells = <0>;
1362 clock-names = "parent-clk", "sel-clk", "spi-clk";
1366 lvts: thermal-sensor@1100b000 {
1367 compatible = "mediatek,mt8186-lvts";
1372 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1373 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1374 #thermal-sensor-cells = <1>;
1378 compatible = "mediatek,mt8186-svs";
1382 clock-names = "main";
1383 nvmem-cells = <&svs_calibration>, <&lvts_efuse_data1>;
1384 nvmem-cell-names = "svs-calibration-data", "t-calibration-data";
1386 reset-names = "svs_rst";
1390 compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm";
1393 #pwm-cells = <2>;
1396 clock-names = "main", "mm";
1401 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1402 #address-cells = <1>;
1403 #size-cells = <0>;
1409 clock-names = "parent-clk", "sel-clk", "spi-clk";
1414 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1415 #address-cells = <1>;
1416 #size-cells = <0>;
1422 clock-names = "parent-clk", "sel-clk", "spi-clk";
1427 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1428 #address-cells = <1>;
1429 #size-cells = <0>;
1435 clock-names = "parent-clk", "sel-clk", "spi-clk";
1440 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1441 #address-cells = <1>;
1442 #size-cells = <0>;
1448 clock-names = "parent-clk", "sel-clk", "spi-clk";
1453 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1454 #address-cells = <1>;
1455 #size-cells = <0>;
1461 clock-names = "parent-clk", "sel-clk", "spi-clk";
1465 imp_iic_wrap: clock-controller@11017000 {
1466 compatible = "mediatek,mt8186-imp_iic_wrap";
1468 #clock-cells = <1>;
1472 compatible = "mediatek,mt8186-uart",
1473 "mediatek,mt6577-uart";
1477 clock-names = "baud", "bus";
1482 compatible = "mediatek,mt8186-i2c";
1488 clock-names = "main", "dma";
1489 clock-div = <1>;
1490 #address-cells = <1>;
1491 #size-cells = <0>;
1495 afe: audio-controller@11210000 {
1496 compatible = "mediatek,mt8186-sound";
1523 clock-names = "aud_infra_clk",
1553 reset-names = "audiosys";
1558 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3";
1560 reg-names = "mac", "ippc";
1566 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
1569 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>;
1570 #address-cells = <2>;
1571 #size-cells = <2>;
1576 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci";
1578 reg-names = "mac";
1584 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
1586 mediatek,syscon-wakeup = <&pericfg 0x420 2>;
1587 wakeup-source;
1593 compatible = "mediatek,mt8186-mmc",
1594 "mediatek,mt8183-mmc";
1601 clock-names = "source", "hclk", "source_cg", "crypto";
1603 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>;
1604 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>;
1609 compatible = "mediatek,mt8186-mmc",
1610 "mediatek,mt8183-mmc";
1616 clock-names = "source", "hclk", "source_cg";
1618 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1619 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1624 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3";
1626 reg-names = "mac", "ippc";
1632 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
1635 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>;
1636 #address-cells = <2>;
1637 #size-cells = <2>;
1642 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci";
1644 reg-names = "mac";
1650 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck";
1652 mediatek,syscon-wakeup = <&pericfg 0x424 2>;
1653 wakeup-source;
1658 u3phy0: t-phy@11c80000 {
1659 compatible = "mediatek,mt8186-tphy",
1660 "mediatek,generic-tphy-v2";
1661 #address-cells = <1>;
1662 #size-cells = <1>;
1666 u2port1: usb-phy@0 {
1669 clock-names = "ref";
1670 #phy-cells = <1>;
1673 u3port1: usb-phy@700 {
1676 clock-names = "ref";
1677 #phy-cells = <1>;
1681 u3phy1: t-phy@11ca0000 {
1682 compatible = "mediatek,mt8186-tphy",
1683 "mediatek,generic-tphy-v2";
1684 #address-cells = <1>;
1685 #size-cells = <1>;
1689 u2port0: usb-phy@0 {
1692 clock-names = "ref";
1693 #phy-cells = <1>;
1698 efuse: efuse@11cb0000 { label
1699 compatible = "mediatek,mt8186-efuse", "mediatek,efuse";
1701 #address-cells = <1>;
1702 #size-cells = <1>;
1704 lvts_efuse_data1: lvts1-calib@1cc {
1708 lvts_efuse_data2: lvts2-calib@2f8 {
1716 gpu_speedbin: gpu-speedbin@59c {
1721 socinfo-data1@7a0 {
1726 mipi_tx0: dsi-phy@11cc0000 {
1727 compatible = "mediatek,mt8183-mipi-tx";
1730 #clock-cells = <0>;
1731 #phy-cells = <0>;
1732 clock-output-names = "mipi_tx0_pll";
1736 mfgsys: clock-controller@13000000 {
1737 compatible = "mediatek,mt8186-mfgsys";
1739 #clock-cells = <1>;
1743 compatible = "mediatek,mt8186-mali",
1744 "arm,mali-bifrost";
1751 interrupt-names = "job", "mmu", "gpu";
1752 power-domains = <&spm MT8186_POWER_DOMAIN_MFG2>,
1754 power-domain-names = "core0", "core1";
1755 #cooling-cells = <2>;
1756 nvmem-cells = <&gpu_speedbin>;
1757 nvmem-cell-names = "speed-bin";
1758 operating-points-v2 = <&gpu_opp_table>;
1759 dynamic-power-coefficient = <4687>;
1764 compatible = "mediatek,mt8186-mmsys", "syscon";
1766 #clock-cells = <1>;
1767 #reset-cells = <1>;
1770 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1774 compatible = "mediatek,mt8186-disp-mutex";
1778 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1779 mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
1781 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1785 compatible = "mediatek,mt8186-smi-common";
1789 clock-names = "apb", "smi", "gals0", "gals1";
1790 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1794 compatible = "mediatek,mt8186-smi-larb";
1798 clock-names = "apb", "smi";
1799 mediatek,larb-id = <0>;
1801 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1805 compatible = "mediatek,mt8186-smi-larb";
1809 clock-names = "apb", "smi";
1810 mediatek,larb-id = <1>;
1812 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1816 compatible = "mediatek,mt8186-disp-ovl", "mediatek,mt8192-disp-ovl";
1821 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
1822 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1826 compatible = "mediatek,mt8186-disp-ovl-2l", "mediatek,mt8192-disp-ovl-2l";
1831 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
1832 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1836 compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma";
1841 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
1842 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1846 compatible = "mediatek,mt8186-disp-color", "mediatek,mt8173-disp-color";
1850 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
1851 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1855 compatible = "mediatek,mt8186-dpi";
1860 clock-names = "pixel", "engine", "pll";
1861 assigned-clocks = <&topckgen CLK_TOP_DPI>;
1862 assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>;
1864 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1873 compatible = "mediatek,mt8186-disp-ccorr", "mediatek,mt8192-disp-ccorr";
1877 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
1878 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1882 compatible = "mediatek,mt8186-disp-aal", "mediatek,mt8183-disp-aal";
1886 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1887 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1891 compatible = "mediatek,mt8186-disp-gamma", "mediatek,mt8183-disp-gamma";
1895 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1896 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1900 compatible = "mediatek,mt8186-disp-postmask",
1901 "mediatek,mt8192-disp-postmask";
1905 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1906 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1910 compatible = "mediatek,mt8186-disp-dither", "mediatek,mt8183-disp-dither";
1914 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1915 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1919 compatible = "mediatek,mt8186-dsi";
1924 clock-names = "engine", "digital", "hs";
1926 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1929 phy-names = "dphy";
1938 compatible = "mediatek,mt8186-iommu-mm";
1941 clock-names = "bclk";
1947 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1948 #iommu-cells = <1>;
1952 compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma";
1957 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xf000 0x1000>;
1958 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1961 wpesys: clock-controller@14020000 {
1962 compatible = "mediatek,mt8186-wpesys";
1964 #clock-cells = <1>;
1968 compatible = "mediatek,mt8186-smi-larb";
1972 clock-names = "apb", "smi";
1973 mediatek,larb-id = <8>;
1975 power-domains = <&spm MT8186_POWER_DOMAIN_WPE>;
1978 imgsys1: clock-controller@15020000 {
1979 compatible = "mediatek,mt8186-imgsys1";
1981 #clock-cells = <1>;
1985 compatible = "mediatek,mt8186-smi-larb";
1989 clock-names = "apb", "smi";
1990 mediatek,larb-id = <9>;
1992 power-domains = <&spm MT8186_POWER_DOMAIN_IMG>;
1995 imgsys2: clock-controller@15820000 {
1996 compatible = "mediatek,mt8186-imgsys2";
1998 #clock-cells = <1>;
2002 compatible = "mediatek,mt8186-smi-larb";
2006 clock-names = "apb", "smi";
2007 mediatek,larb-id = <11>;
2009 power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>;
2012 video_decoder: video-decoder@16000000 {
2013 compatible = "mediatek,mt8186-vcodec-dec";
2016 #address-cells = <2>;
2017 #size-cells = <2>;
2018 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
2022 vcodec_core: video-codec@16025000 {
2023 compatible = "mediatek,mtk-vcodec-core";
2042 clock-names = "vdec-sel", "vdec-soc-vdec", "vdec", "vdec-top";
2043 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2044 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3>;
2045 power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>;
2050 compatible = "mediatek,mt8186-smi-larb";
2054 clock-names = "apb", "smi";
2055 mediatek,larb-id = <4>;
2057 power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>;
2060 vdecsys: clock-controller@1602f000 {
2061 compatible = "mediatek,mt8186-vdecsys";
2063 #clock-cells = <1>;
2066 vencsys: clock-controller@17000000 {
2067 compatible = "mediatek,mt8186-vencsys";
2069 #clock-cells = <1>;
2073 compatible = "mediatek,mt8186-smi-larb";
2077 clock-names = "apb", "smi";
2078 mediatek,larb-id = <7>;
2080 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
2083 venc: video-encoder@17020000 {
2084 compatible = "mediatek,mt8186-vcodec-enc", "mediatek,mt8183-vcodec-enc";
2097 clock-names = "venc_sel";
2098 assigned-clocks = <&topckgen CLK_TOP_VENC>;
2099 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3>;
2100 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
2104 jpgenc: jpeg-encoder@17030000 {
2105 compatible = "mediatek,mt8186-jpgenc", "mediatek,mtk-jpgenc";
2109 clock-names = "jpgenc";
2114 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
2117 camsys: clock-controller@1a000000 {
2118 compatible = "mediatek,mt8186-camsys";
2120 #clock-cells = <1>;
2124 compatible = "mediatek,mt8186-smi-larb";
2127 clock-names = "apb", "smi";
2128 mediatek,larb-id = <13>;
2130 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>;
2134 compatible = "mediatek,mt8186-smi-larb";
2137 clock-names = "apb", "smi";
2138 mediatek,larb-id = <14>;
2140 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>;
2144 compatible = "mediatek,mt8186-smi-larb";
2148 clock-names = "apb", "smi";
2149 mediatek,larb-id = <16>;
2151 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWA>;
2155 compatible = "mediatek,mt8186-smi-larb";
2159 clock-names = "apb", "smi";
2160 mediatek,larb-id = <17>;
2162 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWB>;
2165 camsys_rawa: clock-controller@1a04f000 {
2166 compatible = "mediatek,mt8186-camsys_rawa";
2168 #clock-cells = <1>;
2171 camsys_rawb: clock-controller@1a06f000 {
2172 compatible = "mediatek,mt8186-camsys_rawb";
2174 #clock-cells = <1>;
2177 mdpsys: clock-controller@1b000000 {
2178 compatible = "mediatek,mt8186-mdpsys";
2180 #clock-cells = <1>;
2184 compatible = "mediatek,mt8186-smi-larb";
2187 clock-names = "apb", "smi";
2188 mediatek,larb-id = <2>;
2190 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
2193 ipesys: clock-controller@1c000000 {
2194 compatible = "mediatek,mt8186-ipesys";
2196 #clock-cells = <1>;
2200 compatible = "mediatek,mt8186-smi-larb";
2203 clock-names = "apb", "smi";
2204 mediatek,larb-id = <20>;
2206 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>;
2210 compatible = "mediatek,mt8186-smi-larb";
2213 clock-names = "apb", "smi";
2214 mediatek,larb-id = <19>;
2216 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>;
2220 thermal_zones: thermal-zones {
2221 cpu-little0-thermal {
2222 polling-delay = <1000>;
2223 polling-delay-passive = <150>;
2224 thermal-sensors = <&lvts MT8186_LITTLE_CPU0>;
2227 cpu_little0_alert0: trip-alert0 {
2233 cpu_little0_alert1: trip-alert1 {
2239 cpu_little0_crit: trip-crit {
2246 cooling-maps {
2249 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2259 cpu-little1-thermal {
2260 polling-delay = <1000>;
2261 polling-delay-passive = <150>;
2262 thermal-sensors = <&lvts MT8186_LITTLE_CPU1>;
2265 cpu_little1_alert0: trip-alert0 {
2271 cpu_little1_alert1: trip-alert1 {
2277 cpu_little1_crit: trip-crit {
2284 cooling-maps {
2287 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2297 cpu-little2-thermal {
2298 polling-delay = <1000>;
2299 polling-delay-passive = <150>;
2300 thermal-sensors = <&lvts MT8186_LITTLE_CPU2>;
2303 cpu_little2_alert0: trip-alert0 {
2309 cpu_little2_alert1: trip-alert1 {
2315 cpu_little2_crit: trip-crit {
2322 cooling-maps {
2325 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2335 cam-thermal {
2336 polling-delay = <1000>;
2337 polling-delay-passive = <250>;
2338 thermal-sensors = <&lvts MT8186_CAM>;
2341 cam_alert0: trip-alert0 {
2347 cam_alert1: trip-alert1 {
2353 cam_crit: trip-crit {
2361 nna-thermal {
2362 polling-delay = <1000>;
2363 polling-delay-passive = <250>;
2364 thermal-sensors = <&lvts MT8186_NNA>;
2367 nna_alert0: trip-alert0 {
2373 nna_alert1: trip-alert1 {
2379 nna_crit: trip-crit {
2387 adsp-thermal {
2388 polling-delay = <1000>;
2389 polling-delay-passive = <250>;
2390 thermal-sensors = <&lvts MT8186_ADSP>;
2393 adsp_alert0: trip-alert0 {
2399 adsp_alert1: trip-alert1 {
2405 adsp_crit: trip-crit {
2413 gpu-thermal {
2414 polling-delay = <1000>;
2415 polling-delay-passive = <250>;
2416 thermal-sensors = <&lvts MT8186_GPU>;
2419 gpu_alert0: trip-alert0 {
2425 gpu_alert1: trip-alert1 {
2431 gpu_crit: trip-crit {
2438 cooling-maps {
2441 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2446 cpu-big0-thermal {
2447 polling-delay = <1000>;
2448 polling-delay-passive = <100>;
2449 thermal-sensors = <&lvts MT8186_BIG_CPU0>;
2452 cpu_big0_alert0: trip-alert0 {
2458 cpu_big0_alert1: trip-alert1 {
2464 cpu_big0_crit: trip-crit {
2471 cooling-maps {
2474 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2480 cpu-big1-thermal {
2481 polling-delay = <1000>;
2482 polling-delay-passive = <100>;
2483 thermal-sensors = <&lvts MT8186_BIG_CPU1>;
2486 cpu_big1_alert0: trip-alert0 {
2492 cpu_big1_alert1: trip-alert1 {
2498 cpu_big1_crit: trip-crit {
2505 cooling-maps {
2508 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,