Lines Matching +full:crit +full:- +full:soc +full:- +full:level
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
6 /dts-v1/;
7 #include <dt-bindings/clock/mt8186-clk.h>
8 #include <dt-bindings/gce/mt8186-gce.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/memory/mt8186-memory-port.h>
12 #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
13 #include <dt-bindings/power/mt8186-power.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/reset/mt8186-resets.h>
16 #include <dt-bindings/thermal/thermal.h>
17 #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
21 interrupt-parent = <&gic>;
22 #address-cells = <2>;
23 #size-cells = <2>;
27 ovl-2l0 = &ovl_2l0;
33 compatible = "mediatek,mt8186-fhctl";
40 compatible = "mediatek,mt8186-cci";
43 clock-names = "cci", "intermediate";
44 operating-points-v2 = <&cci_opp>;
47 cci_opp: opp-table-cci {
48 compatible = "operating-points-v2";
49 opp-shared;
51 cci_opp_0: opp-500000000 {
52 opp-hz = /bits/ 64 <500000000>;
53 opp-microvolt = <600000>;
56 cci_opp_1: opp-560000000 {
57 opp-hz = /bits/ 64 <560000000>;
58 opp-microvolt = <675000>;
61 cci_opp_2: opp-612000000 {
62 opp-hz = /bits/ 64 <612000000>;
63 opp-microvolt = <693750>;
66 cci_opp_3: opp-682000000 {
67 opp-hz = /bits/ 64 <682000000>;
68 opp-microvolt = <718750>;
71 cci_opp_4: opp-752000000 {
72 opp-hz = /bits/ 64 <752000000>;
73 opp-microvolt = <743750>;
76 cci_opp_5: opp-822000000 {
77 opp-hz = /bits/ 64 <822000000>;
78 opp-microvolt = <768750>;
81 cci_opp_6: opp-875000000 {
82 opp-hz = /bits/ 64 <875000000>;
83 opp-microvolt = <781250>;
86 cci_opp_7: opp-927000000 {
87 opp-hz = /bits/ 64 <927000000>;
88 opp-microvolt = <800000>;
91 cci_opp_8: opp-980000000 {
92 opp-hz = /bits/ 64 <980000000>;
93 opp-microvolt = <818750>;
96 cci_opp_9: opp-1050000000 {
97 opp-hz = /bits/ 64 <1050000000>;
98 opp-microvolt = <843750>;
101 cci_opp_10: opp-1120000000 {
102 opp-hz = /bits/ 64 <1120000000>;
103 opp-microvolt = <862500>;
106 cci_opp_11: opp-1155000000 {
107 opp-hz = /bits/ 64 <1155000000>;
108 opp-microvolt = <887500>;
111 cci_opp_12: opp-1190000000 {
112 opp-hz = /bits/ 64 <1190000000>;
113 opp-microvolt = <906250>;
116 cci_opp_13: opp-1260000000 {
117 opp-hz = /bits/ 64 <1260000000>;
118 opp-microvolt = <950000>;
121 cci_opp_14: opp-1330000000 {
122 opp-hz = /bits/ 64 <1330000000>;
123 opp-microvolt = <993750>;
126 cci_opp_15: opp-1400000000 {
127 opp-hz = /bits/ 64 <1400000000>;
128 opp-microvolt = <1031250>;
132 cluster0_opp: opp-table-cluster0 {
133 compatible = "operating-points-v2";
134 opp-shared;
136 opp-500000000 {
137 opp-hz = /bits/ 64 <500000000>;
138 opp-microvolt = <600000>;
139 required-opps = <&cci_opp_0>;
142 opp-774000000 {
143 opp-hz = /bits/ 64 <774000000>;
144 opp-microvolt = <675000>;
145 required-opps = <&cci_opp_1>;
148 opp-875000000 {
149 opp-hz = /bits/ 64 <875000000>;
150 opp-microvolt = <700000>;
151 required-opps = <&cci_opp_2>;
154 opp-975000000 {
155 opp-hz = /bits/ 64 <975000000>;
156 opp-microvolt = <725000>;
157 required-opps = <&cci_opp_3>;
160 opp-1075000000 {
161 opp-hz = /bits/ 64 <1075000000>;
162 opp-microvolt = <750000>;
163 required-opps = <&cci_opp_4>;
166 opp-1175000000 {
167 opp-hz = /bits/ 64 <1175000000>;
168 opp-microvolt = <775000>;
169 required-opps = <&cci_opp_5>;
172 opp-1275000000 {
173 opp-hz = /bits/ 64 <1275000000>;
174 opp-microvolt = <800000>;
175 required-opps = <&cci_opp_6>;
178 opp-1375000000 {
179 opp-hz = /bits/ 64 <1375000000>;
180 opp-microvolt = <825000>;
181 required-opps = <&cci_opp_7>;
184 opp-1500000000 {
185 opp-hz = /bits/ 64 <1500000000>;
186 opp-microvolt = <856250>;
187 required-opps = <&cci_opp_8>;
190 opp-1618000000 {
191 opp-hz = /bits/ 64 <1618000000>;
192 opp-microvolt = <875000>;
193 required-opps = <&cci_opp_9>;
196 opp-1666000000 {
197 opp-hz = /bits/ 64 <1666000000>;
198 opp-microvolt = <900000>;
199 required-opps = <&cci_opp_10>;
202 opp-1733000000 {
203 opp-hz = /bits/ 64 <1733000000>;
204 opp-microvolt = <925000>;
205 required-opps = <&cci_opp_11>;
208 opp-1800000000 {
209 opp-hz = /bits/ 64 <1800000000>;
210 opp-microvolt = <950000>;
211 required-opps = <&cci_opp_12>;
214 opp-1866000000 {
215 opp-hz = /bits/ 64 <1866000000>;
216 opp-microvolt = <981250>;
217 required-opps = <&cci_opp_13>;
220 opp-1933000000 {
221 opp-hz = /bits/ 64 <1933000000>;
222 opp-microvolt = <1006250>;
223 required-opps = <&cci_opp_14>;
226 opp-2000000000 {
227 opp-hz = /bits/ 64 <2000000000>;
228 opp-microvolt = <1031250>;
229 required-opps = <&cci_opp_15>;
233 cluster1_opp: opp-table-cluster1 {
234 compatible = "operating-points-v2";
235 opp-shared;
237 opp-774000000 {
238 opp-hz = /bits/ 64 <774000000>;
239 opp-microvolt = <675000>;
240 required-opps = <&cci_opp_0>;
243 opp-835000000 {
244 opp-hz = /bits/ 64 <835000000>;
245 opp-microvolt = <693750>;
246 required-opps = <&cci_opp_1>;
249 opp-919000000 {
250 opp-hz = /bits/ 64 <919000000>;
251 opp-microvolt = <718750>;
252 required-opps = <&cci_opp_2>;
255 opp-1002000000 {
256 opp-hz = /bits/ 64 <1002000000>;
257 opp-microvolt = <743750>;
258 required-opps = <&cci_opp_3>;
261 opp-1085000000 {
262 opp-hz = /bits/ 64 <1085000000>;
263 opp-microvolt = <775000>;
264 required-opps = <&cci_opp_4>;
267 opp-1169000000 {
268 opp-hz = /bits/ 64 <1169000000>;
269 opp-microvolt = <800000>;
270 required-opps = <&cci_opp_5>;
273 opp-1308000000 {
274 opp-hz = /bits/ 64 <1308000000>;
275 opp-microvolt = <843750>;
276 required-opps = <&cci_opp_6>;
279 opp-1419000000 {
280 opp-hz = /bits/ 64 <1419000000>;
281 opp-microvolt = <875000>;
282 required-opps = <&cci_opp_7>;
285 opp-1530000000 {
286 opp-hz = /bits/ 64 <1530000000>;
287 opp-microvolt = <912500>;
288 required-opps = <&cci_opp_8>;
291 opp-1670000000 {
292 opp-hz = /bits/ 64 <1670000000>;
293 opp-microvolt = <956250>;
294 required-opps = <&cci_opp_9>;
297 opp-1733000000 {
298 opp-hz = /bits/ 64 <1733000000>;
299 opp-microvolt = <981250>;
300 required-opps = <&cci_opp_10>;
303 opp-1796000000 {
304 opp-hz = /bits/ 64 <1796000000>;
305 opp-microvolt = <1012500>;
306 required-opps = <&cci_opp_11>;
309 opp-1860000000 {
310 opp-hz = /bits/ 64 <1860000000>;
311 opp-microvolt = <1037500>;
312 required-opps = <&cci_opp_12>;
315 opp-1923000000 {
316 opp-hz = /bits/ 64 <1923000000>;
317 opp-microvolt = <1062500>;
318 required-opps = <&cci_opp_13>;
321 cluster1_opp_14: opp-1986000000 {
322 opp-hz = /bits/ 64 <1986000000>;
323 opp-microvolt = <1093750>;
324 required-opps = <&cci_opp_14>;
327 cluster1_opp_15: opp-2050000000 {
328 opp-hz = /bits/ 64 <2050000000>;
329 opp-microvolt = <1118750>;
330 required-opps = <&cci_opp_15>;
335 #address-cells = <1>;
336 #size-cells = <0>;
338 cpu-map {
376 compatible = "arm,cortex-a55";
378 enable-method = "psci";
379 clock-frequency = <2000000000>;
382 clock-names = "cpu", "intermediate";
383 operating-points-v2 = <&cluster0_opp>;
384 dynamic-power-coefficient = <84>;
385 capacity-dmips-mhz = <382>;
386 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
387 i-cache-size = <32768>;
388 i-cache-line-size = <64>;
389 i-cache-sets = <128>;
390 d-cache-size = <32768>;
391 d-cache-line-size = <64>;
392 d-cache-sets = <128>;
393 next-level-cache = <&l2_0>;
394 #cooling-cells = <2>;
400 compatible = "arm,cortex-a55";
402 enable-method = "psci";
403 clock-frequency = <2000000000>;
406 clock-names = "cpu", "intermediate";
407 operating-points-v2 = <&cluster0_opp>;
408 dynamic-power-coefficient = <84>;
409 capacity-dmips-mhz = <382>;
410 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
411 i-cache-size = <32768>;
412 i-cache-line-size = <64>;
413 i-cache-sets = <128>;
414 d-cache-size = <32768>;
415 d-cache-line-size = <64>;
416 d-cache-sets = <128>;
417 next-level-cache = <&l2_0>;
418 #cooling-cells = <2>;
424 compatible = "arm,cortex-a55";
426 enable-method = "psci";
427 clock-frequency = <2000000000>;
430 clock-names = "cpu", "intermediate";
431 operating-points-v2 = <&cluster0_opp>;
432 dynamic-power-coefficient = <84>;
433 capacity-dmips-mhz = <382>;
434 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
435 i-cache-size = <32768>;
436 i-cache-line-size = <64>;
437 i-cache-sets = <128>;
438 d-cache-size = <32768>;
439 d-cache-line-size = <64>;
440 d-cache-sets = <128>;
441 next-level-cache = <&l2_0>;
442 #cooling-cells = <2>;
448 compatible = "arm,cortex-a55";
450 enable-method = "psci";
451 clock-frequency = <2000000000>;
454 clock-names = "cpu", "intermediate";
455 operating-points-v2 = <&cluster0_opp>;
456 dynamic-power-coefficient = <84>;
457 capacity-dmips-mhz = <382>;
458 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
459 i-cache-size = <32768>;
460 i-cache-line-size = <64>;
461 i-cache-sets = <128>;
462 d-cache-size = <32768>;
463 d-cache-line-size = <64>;
464 d-cache-sets = <128>;
465 next-level-cache = <&l2_0>;
466 #cooling-cells = <2>;
472 compatible = "arm,cortex-a55";
474 enable-method = "psci";
475 clock-frequency = <2000000000>;
478 clock-names = "cpu", "intermediate";
479 operating-points-v2 = <&cluster0_opp>;
480 dynamic-power-coefficient = <84>;
481 capacity-dmips-mhz = <382>;
482 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
483 i-cache-size = <32768>;
484 i-cache-line-size = <64>;
485 i-cache-sets = <128>;
486 d-cache-size = <32768>;
487 d-cache-line-size = <64>;
488 d-cache-sets = <128>;
489 next-level-cache = <&l2_0>;
490 #cooling-cells = <2>;
496 compatible = "arm,cortex-a55";
498 enable-method = "psci";
499 clock-frequency = <2000000000>;
502 clock-names = "cpu", "intermediate";
503 operating-points-v2 = <&cluster0_opp>;
504 dynamic-power-coefficient = <84>;
505 capacity-dmips-mhz = <382>;
506 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
507 i-cache-size = <32768>;
508 i-cache-line-size = <64>;
509 i-cache-sets = <128>;
510 d-cache-size = <32768>;
511 d-cache-line-size = <64>;
512 d-cache-sets = <128>;
513 next-level-cache = <&l2_0>;
514 #cooling-cells = <2>;
520 compatible = "arm,cortex-a76";
522 enable-method = "psci";
523 clock-frequency = <2050000000>;
526 clock-names = "cpu", "intermediate";
527 operating-points-v2 = <&cluster1_opp>;
528 dynamic-power-coefficient = <335>;
529 capacity-dmips-mhz = <1024>;
530 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
531 i-cache-size = <65536>;
532 i-cache-line-size = <64>;
533 i-cache-sets = <256>;
534 d-cache-size = <65536>;
535 d-cache-line-size = <64>;
536 d-cache-sets = <256>;
537 next-level-cache = <&l2_1>;
538 #cooling-cells = <2>;
544 compatible = "arm,cortex-a76";
546 enable-method = "psci";
547 clock-frequency = <2050000000>;
550 clock-names = "cpu", "intermediate";
551 operating-points-v2 = <&cluster1_opp>;
552 dynamic-power-coefficient = <335>;
553 capacity-dmips-mhz = <1024>;
554 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
555 i-cache-size = <65536>;
556 i-cache-line-size = <64>;
557 i-cache-sets = <256>;
558 d-cache-size = <65536>;
559 d-cache-line-size = <64>;
560 d-cache-sets = <256>;
561 next-level-cache = <&l2_1>;
562 #cooling-cells = <2>;
566 idle-states {
567 entry-method = "psci";
569 cpu_ret_l: cpu-retention-l {
570 compatible = "arm,idle-state";
571 arm,psci-suspend-param = <0x00010001>;
572 local-timer-stop;
573 entry-latency-us = <50>;
574 exit-latency-us = <100>;
575 min-residency-us = <1600>;
578 cpu_ret_b: cpu-retention-b {
579 compatible = "arm,idle-state";
580 arm,psci-suspend-param = <0x00010001>;
581 local-timer-stop;
582 entry-latency-us = <50>;
583 exit-latency-us = <100>;
584 min-residency-us = <1400>;
587 cpu_off_l: cpu-off-l {
588 compatible = "arm,idle-state";
589 arm,psci-suspend-param = <0x01010001>;
590 local-timer-stop;
591 entry-latency-us = <100>;
592 exit-latency-us = <250>;
593 min-residency-us = <2100>;
596 cpu_off_b: cpu-off-b {
597 compatible = "arm,idle-state";
598 arm,psci-suspend-param = <0x01010001>;
599 local-timer-stop;
600 entry-latency-us = <100>;
601 exit-latency-us = <250>;
602 min-residency-us = <1900>;
606 l2_0: l2-cache0 {
608 cache-level = <2>;
609 cache-size = <131072>;
610 cache-line-size = <64>;
611 cache-sets = <512>;
612 next-level-cache = <&l3_0>;
613 cache-unified;
616 l2_1: l2-cache1 {
618 cache-level = <2>;
619 cache-size = <262144>;
620 cache-line-size = <64>;
621 cache-sets = <512>;
622 next-level-cache = <&l3_0>;
623 cache-unified;
626 l3_0: l3-cache {
628 cache-level = <3>;
629 cache-size = <1048576>;
630 cache-line-size = <64>;
631 cache-sets = <1024>;
632 cache-unified;
636 clk13m: fixed-factor-clock-13m {
637 compatible = "fixed-factor-clock";
638 #clock-cells = <0>;
640 clock-div = <2>;
641 clock-mult = <1>;
642 clock-output-names = "clk13m";
645 clk26m: oscillator-26m {
646 compatible = "fixed-clock";
647 #clock-cells = <0>;
648 clock-frequency = <26000000>;
649 clock-output-names = "clk26m";
652 clk32k: oscillator-32k {
653 compatible = "fixed-clock";
654 #clock-cells = <0>;
655 clock-frequency = <32768>;
656 clock-output-names = "clk32k";
659 gpu_opp_table: opp-table-gpu {
660 compatible = "operating-points-v2";
662 opp-299000000 {
663 opp-hz = /bits/ 64 <299000000>;
664 opp-microvolt = <612500>;
665 opp-supported-hw = <0xff>;
668 opp-332000000 {
669 opp-hz = /bits/ 64 <332000000>;
670 opp-microvolt = <625000>;
671 opp-supported-hw = <0xff>;
674 opp-366000000 {
675 opp-hz = /bits/ 64 <366000000>;
676 opp-microvolt = <637500>;
677 opp-supported-hw = <0xff>;
680 opp-400000000 {
681 opp-hz = /bits/ 64 <400000000>;
682 opp-microvolt = <643750>;
683 opp-supported-hw = <0xff>;
686 opp-434000000 {
687 opp-hz = /bits/ 64 <434000000>;
688 opp-microvolt = <656250>;
689 opp-supported-hw = <0xff>;
692 opp-484000000 {
693 opp-hz = /bits/ 64 <484000000>;
694 opp-microvolt = <668750>;
695 opp-supported-hw = <0xff>;
698 opp-535000000 {
699 opp-hz = /bits/ 64 <535000000>;
700 opp-microvolt = <687500>;
701 opp-supported-hw = <0xff>;
704 opp-586000000 {
705 opp-hz = /bits/ 64 <586000000>;
706 opp-microvolt = <700000>;
707 opp-supported-hw = <0xff>;
710 opp-637000000 {
711 opp-hz = /bits/ 64 <637000000>;
712 opp-microvolt = <712500>;
713 opp-supported-hw = <0xff>;
716 opp-690000000 {
717 opp-hz = /bits/ 64 <690000000>;
718 opp-microvolt = <737500>;
719 opp-supported-hw = <0xff>;
722 opp-743000000 {
723 opp-hz = /bits/ 64 <743000000>;
724 opp-microvolt = <756250>;
725 opp-supported-hw = <0xff>;
728 opp-796000000 {
729 opp-hz = /bits/ 64 <796000000>;
730 opp-microvolt = <781250>;
731 opp-supported-hw = <0xff>;
734 opp-850000000 {
735 opp-hz = /bits/ 64 <850000000>;
736 opp-microvolt = <800000>;
737 opp-supported-hw = <0xff>;
740 opp-900000000-3 {
741 opp-hz = /bits/ 64 <900000000>;
742 opp-microvolt = <850000>;
743 opp-supported-hw = <0xcf>;
746 opp-900000000-4 {
747 opp-hz = /bits/ 64 <900000000>;
748 opp-microvolt = <837500>;
749 opp-supported-hw = <0x10>;
752 opp-900000000-5 {
753 opp-hz = /bits/ 64 <900000000>;
754 opp-microvolt = <825000>;
755 opp-supported-hw = <0x20>;
758 opp-950000000-3 {
759 opp-hz = /bits/ 64 <950000000>;
760 opp-microvolt = <900000>;
761 opp-supported-hw = <0xcf>;
764 opp-950000000-4 {
765 opp-hz = /bits/ 64 <950000000>;
766 opp-microvolt = <875000>;
767 opp-supported-hw = <0x10>;
770 opp-950000000-5 {
771 opp-hz = /bits/ 64 <950000000>;
772 opp-microvolt = <850000>;
773 opp-supported-hw = <0x20>;
776 opp-1000000000-3 {
777 opp-hz = /bits/ 64 <1000000000>;
778 opp-microvolt = <950000>;
779 opp-supported-hw = <0xcf>;
782 opp-1000000000-4 {
783 opp-hz = /bits/ 64 <1000000000>;
784 opp-microvolt = <912500>;
785 opp-supported-hw = <0x10>;
788 opp-1000000000-5 {
789 opp-hz = /bits/ 64 <1000000000>;
790 opp-microvolt = <875000>;
791 opp-supported-hw = <0x20>;
795 pmu-a55 {
796 compatible = "arm,cortex-a55-pmu";
797 interrupt-parent = <&gic>;
801 pmu-a76 {
802 compatible = "arm,cortex-a76-pmu";
803 interrupt-parent = <&gic>;
808 compatible = "arm,psci-1.0";
813 compatible = "arm,armv8-timer";
814 interrupt-parent = <&gic>;
821 soc {
822 #address-cells = <2>;
823 #size-cells = <2>;
824 compatible = "simple-bus";
825 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
828 gic: interrupt-controller@c000000 {
829 compatible = "arm,gic-v3";
830 #interrupt-cells = <4>;
831 #redistributor-regions = <1>;
832 interrupt-parent = <&gic>;
833 interrupt-controller;
838 ppi-partitions {
839 ppi_cluster0: interrupt-partition-0 {
843 ppi_cluster1: interrupt-partition-1 {
850 compatible = "mediatek,mt8186-mcusys", "syscon";
852 #clock-cells = <1>;
856 compatible = "mediatek,mt8186-topckgen", "syscon";
858 #clock-cells = <1>;
862 compatible = "mediatek,mt8186-infracfg_ao", "syscon";
864 #clock-cells = <1>;
865 #reset-cells = <1>;
869 compatible = "mediatek,mt8186-pericfg", "syscon";
874 compatible = "mediatek,mt8186-pinctrl";
883 reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb",
885 gpio-controller;
886 #gpio-cells = <2>;
887 gpio-ranges = <&pio 0 0 185>;
888 interrupt-controller;
890 #interrupt-cells = <2>;
894 compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd";
898 spm: power-controller {
899 compatible = "mediatek,mt8186-power-controller";
900 #address-cells = <1>;
901 #size-cells = <0>;
902 #power-domain-cells = <1>;
904 /* power domain of the SoC */
905 mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 {
908 clock-names = "mfg00";
909 #address-cells = <1>;
910 #size-cells = <0>;
911 #power-domain-cells = <1>;
913 mfg1: power-domain@MT8186_POWER_DOMAIN_MFG1 {
916 #address-cells = <1>;
917 #size-cells = <0>;
918 #power-domain-cells = <1>;
920 power-domain@MT8186_POWER_DOMAIN_MFG2 {
922 #power-domain-cells = <0>;
925 power-domain@MT8186_POWER_DOMAIN_MFG3 {
927 #power-domain-cells = <0>;
932 power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP {
936 clock-names = "subsys-csirx-top0",
937 "subsys-csirx-top1";
938 #power-domain-cells = <0>;
941 power-domain@MT8186_POWER_DOMAIN_SSUSB {
945 clock-names = "sys_ck", "ref_ck";
946 #power-domain-cells = <0>;
949 power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 {
953 clock-names = "sys_ck", "ref_ck";
954 #power-domain-cells = <0>;
957 power-domain@MT8186_POWER_DOMAIN_ADSP_AO {
961 clock-names = "audioadsp",
962 "subsys-adsp-bus";
963 #address-cells = <1>;
964 #size-cells = <0>;
965 #power-domain-cells = <1>;
967 power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA {
969 #address-cells = <1>;
970 #size-cells = <0>;
971 #power-domain-cells = <1>;
973 power-domain@MT8186_POWER_DOMAIN_ADSP_TOP {
976 #power-domain-cells = <0>;
981 power-domain@MT8186_POWER_DOMAIN_CONN_ON {
984 #power-domain-cells = <0>;
987 power-domain@MT8186_POWER_DOMAIN_DIS {
995 clock-names = "disp", "mdp",
996 "subsys-smi-infra",
997 "subsys-smi-common",
998 "subsys-smi-gals",
999 "subsys-smi-iommu";
1001 #address-cells = <1>;
1002 #size-cells = <0>;
1003 #power-domain-cells = <1>;
1005 power-domain@MT8186_POWER_DOMAIN_VDEC {
1009 clock-names = "vdec0", "larb";
1011 #power-domain-cells = <0>;
1014 power-domain@MT8186_POWER_DOMAIN_CAM {
1023 clock-names = "cam0", "cam1", "cam2",
1025 "subsys-cam-tm",
1026 "subsys-cam-top";
1028 #address-cells = <1>;
1029 #size-cells = <0>;
1030 #power-domain-cells = <1>;
1032 power-domain@MT8186_POWER_DOMAIN_CAM_RAWB {
1034 #power-domain-cells = <0>;
1037 power-domain@MT8186_POWER_DOMAIN_CAM_RAWA {
1039 #power-domain-cells = <0>;
1043 power-domain@MT8186_POWER_DOMAIN_IMG {
1047 clock-names = "gals", "subsys-img-top";
1049 #address-cells = <1>;
1050 #size-cells = <0>;
1051 #power-domain-cells = <1>;
1053 power-domain@MT8186_POWER_DOMAIN_IMG2 {
1055 #power-domain-cells = <0>;
1059 power-domain@MT8186_POWER_DOMAIN_IPE {
1066 clock-names = "subsys-ipe-top",
1067 "subsys-ipe-larb0",
1068 "subsys-ipe-larb1",
1069 "subsys-ipe-smi",
1070 "subsys-ipe-gals";
1072 #power-domain-cells = <0>;
1075 power-domain@MT8186_POWER_DOMAIN_VENC {
1079 clock-names = "venc0", "subsys-larb";
1081 #power-domain-cells = <0>;
1084 power-domain@MT8186_POWER_DOMAIN_WPE {
1089 clock-names = "wpe0",
1090 "subsys-larb-ck",
1091 "subsys-larb-pclk";
1093 #power-domain-cells = <0>;
1100 compatible = "mediatek,mt8186-wdt";
1101 mediatek,disable-extrst;
1103 #reset-cells = <1>;
1107 compatible = "mediatek,mt8186-apmixedsys", "syscon";
1109 #clock-cells = <1>;
1113 compatible = "mediatek,mt8186-pwrap", "syscon";
1115 reg-names = "pwrap";
1119 clock-names = "spi", "wrap";
1123 compatible = "mediatek,mt8186-spmi", "mediatek,mt8195-spmi";
1125 reg-names = "pmif", "spmimst";
1129 clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux";
1130 assigned-clocks = <&topckgen CLK_TOP_SPMI_MST>;
1131 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
1138 compatible = "mediatek,mt8186-timer",
1139 "mediatek,mt6765-timer";
1146 compatible = "mediatek,mt8186-gce";
1149 clock-names = "gce";
1151 #mbox-cells = <2>;
1155 compatible = "mediatek,mt8186-scp";
1158 reg-names = "sram", "cfg";
1163 compatible = "mediatek,mt8186-dsp";
1166 reg-names = "cfg", "sram", "sec", "bus";
1168 clock-names = "audiodsp", "adsp_bus";
1169 assigned-clocks = <&topckgen CLK_TOP_AUDIODSP>,
1171 assigned-clock-parents = <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>;
1172 mbox-names = "rx", "tx";
1174 power-domains = <&spm MT8186_POWER_DOMAIN_ADSP_TOP>;
1179 compatible = "mediatek,mt8186-adsp-mbox";
1180 #mbox-cells = <0>;
1186 compatible = "mediatek,mt8186-adsp-mbox";
1187 #mbox-cells = <0>;
1193 compatible = "mediatek,mt8186-nor";
1199 clock-names = "spi", "sf", "axi", "axi_s";
1200 assigned-clocks = <&topckgen CLK_TOP_SPINOR>;
1201 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>;
1207 compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc";
1209 #io-channel-cells = <1>;
1211 clock-names = "main";
1215 compatible = "mediatek,mt8186-uart",
1216 "mediatek,mt6577-uart";
1220 clock-names = "baud", "bus";
1225 compatible = "mediatek,mt8186-uart",
1226 "mediatek,mt6577-uart";
1230 clock-names = "baud", "bus";
1235 compatible = "mediatek,mt8186-i2c";
1241 clock-names = "main", "dma";
1242 clock-div = <1>;
1243 #address-cells = <1>;
1244 #size-cells = <0>;
1249 compatible = "mediatek,mt8186-i2c";
1255 clock-names = "main", "dma";
1256 clock-div = <1>;
1257 #address-cells = <1>;
1258 #size-cells = <0>;
1263 compatible = "mediatek,mt8186-i2c";
1269 clock-names = "main", "dma";
1270 clock-div = <1>;
1271 #address-cells = <1>;
1272 #size-cells = <0>;
1277 compatible = "mediatek,mt8186-i2c";
1283 clock-names = "main", "dma";
1284 clock-div = <1>;
1285 #address-cells = <1>;
1286 #size-cells = <0>;
1291 compatible = "mediatek,mt8186-i2c";
1297 clock-names = "main", "dma";
1298 clock-div = <1>;
1299 #address-cells = <1>;
1300 #size-cells = <0>;
1305 compatible = "mediatek,mt8186-i2c";
1311 clock-names = "main", "dma";
1312 clock-div = <1>;
1313 #address-cells = <1>;
1314 #size-cells = <0>;
1319 compatible = "mediatek,mt8186-i2c";
1325 clock-names = "main", "dma";
1326 clock-div = <1>;
1327 #address-cells = <1>;
1328 #size-cells = <0>;
1333 compatible = "mediatek,mt8186-i2c";
1339 clock-names = "main", "dma";
1340 clock-div = <1>;
1341 #address-cells = <1>;
1342 #size-cells = <0>;
1347 compatible = "mediatek,mt8186-i2c";
1353 clock-names = "main", "dma";
1354 clock-div = <1>;
1355 #address-cells = <1>;
1356 #size-cells = <0>;
1361 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1362 #address-cells = <1>;
1363 #size-cells = <0>;
1369 clock-names = "parent-clk", "sel-clk", "spi-clk";
1373 lvts: thermal-sensor@1100b000 {
1374 compatible = "mediatek,mt8186-lvts";
1379 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1380 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1381 #thermal-sensor-cells = <1>;
1385 compatible = "mediatek,mt8186-svs";
1389 clock-names = "main";
1390 nvmem-cells = <&svs_calibration>, <&lvts_efuse_data1>;
1391 nvmem-cell-names = "svs-calibration-data", "t-calibration-data";
1393 reset-names = "svs_rst";
1397 compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm";
1400 #pwm-cells = <2>;
1403 clock-names = "main", "mm";
1408 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1409 #address-cells = <1>;
1410 #size-cells = <0>;
1416 clock-names = "parent-clk", "sel-clk", "spi-clk";
1421 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1422 #address-cells = <1>;
1423 #size-cells = <0>;
1429 clock-names = "parent-clk", "sel-clk", "spi-clk";
1434 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1435 #address-cells = <1>;
1436 #size-cells = <0>;
1442 clock-names = "parent-clk", "sel-clk", "spi-clk";
1447 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1448 #address-cells = <1>;
1449 #size-cells = <0>;
1455 clock-names = "parent-clk", "sel-clk", "spi-clk";
1460 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1461 #address-cells = <1>;
1462 #size-cells = <0>;
1468 clock-names = "parent-clk", "sel-clk", "spi-clk";
1472 imp_iic_wrap: clock-controller@11017000 {
1473 compatible = "mediatek,mt8186-imp_iic_wrap";
1475 #clock-cells = <1>;
1479 compatible = "mediatek,mt8186-uart",
1480 "mediatek,mt6577-uart";
1484 clock-names = "baud", "bus";
1489 compatible = "mediatek,mt8186-i2c";
1495 clock-names = "main", "dma";
1496 clock-div = <1>;
1497 #address-cells = <1>;
1498 #size-cells = <0>;
1502 afe: audio-controller@11210000 {
1503 compatible = "mediatek,mt8186-sound";
1530 clock-names = "aud_infra_clk",
1560 reset-names = "audiosys";
1565 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3";
1567 reg-names = "mac", "ippc";
1573 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
1576 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>;
1577 #address-cells = <2>;
1578 #size-cells = <2>;
1583 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci";
1585 reg-names = "mac";
1591 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
1593 mediatek,syscon-wakeup = <&pericfg 0x420 2>;
1594 wakeup-source;
1600 compatible = "mediatek,mt8186-mmc",
1601 "mediatek,mt8183-mmc";
1608 clock-names = "source", "hclk", "source_cg", "crypto";
1610 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>;
1611 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>;
1616 compatible = "mediatek,mt8186-mmc",
1617 "mediatek,mt8183-mmc";
1623 clock-names = "source", "hclk", "source_cg";
1625 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1626 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1631 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3";
1633 reg-names = "mac", "ippc";
1639 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
1642 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>;
1643 #address-cells = <2>;
1644 #size-cells = <2>;
1649 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci";
1651 reg-names = "mac";
1657 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck";
1659 mediatek,syscon-wakeup = <&pericfg 0x424 2>;
1660 wakeup-source;
1665 u3phy0: t-phy@11c80000 {
1666 compatible = "mediatek,mt8186-tphy",
1667 "mediatek,generic-tphy-v2";
1668 #address-cells = <1>;
1669 #size-cells = <1>;
1673 u2port1: usb-phy@0 {
1676 clock-names = "ref";
1677 #phy-cells = <1>;
1680 u3port1: usb-phy@700 {
1683 clock-names = "ref";
1684 #phy-cells = <1>;
1688 u3phy1: t-phy@11ca0000 {
1689 compatible = "mediatek,mt8186-tphy",
1690 "mediatek,generic-tphy-v2";
1691 #address-cells = <1>;
1692 #size-cells = <1>;
1696 u2port0: usb-phy@0 {
1699 clock-names = "ref";
1700 #phy-cells = <1>;
1706 compatible = "mediatek,mt8186-efuse", "mediatek,efuse";
1708 #address-cells = <1>;
1709 #size-cells = <1>;
1711 lvts_efuse_data1: lvts1-calib@1cc {
1715 lvts_efuse_data2: lvts2-calib@2f8 {
1723 gpu_speedbin: gpu-speedbin@59c {
1728 socinfo-data1@7a0 {
1733 mipi_tx0: dsi-phy@11cc0000 {
1734 compatible = "mediatek,mt8183-mipi-tx";
1737 #clock-cells = <0>;
1738 #phy-cells = <0>;
1739 clock-output-names = "mipi_tx0_pll";
1743 mfgsys: clock-controller@13000000 {
1744 compatible = "mediatek,mt8186-mfgsys";
1746 #clock-cells = <1>;
1750 compatible = "mediatek,mt8186-mali",
1751 "arm,mali-bifrost";
1758 interrupt-names = "job", "mmu", "gpu";
1759 power-domains = <&spm MT8186_POWER_DOMAIN_MFG2>,
1761 power-domain-names = "core0", "core1";
1762 #cooling-cells = <2>;
1763 nvmem-cells = <&gpu_speedbin>;
1764 nvmem-cell-names = "speed-bin";
1765 operating-points-v2 = <&gpu_opp_table>;
1766 dynamic-power-coefficient = <4687>;
1771 compatible = "mediatek,mt8186-mmsys", "syscon";
1773 #clock-cells = <1>;
1774 #reset-cells = <1>;
1777 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1781 compatible = "mediatek,mt8186-disp-mutex";
1785 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1786 mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
1788 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1792 compatible = "mediatek,mt8186-smi-common";
1796 clock-names = "apb", "smi", "gals0", "gals1";
1797 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1801 compatible = "mediatek,mt8186-smi-larb";
1805 clock-names = "apb", "smi";
1806 mediatek,larb-id = <0>;
1808 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1812 compatible = "mediatek,mt8186-smi-larb";
1816 clock-names = "apb", "smi";
1817 mediatek,larb-id = <1>;
1819 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1823 compatible = "mediatek,mt8186-disp-ovl", "mediatek,mt8192-disp-ovl";
1828 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
1829 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1833 compatible = "mediatek,mt8186-disp-ovl-2l", "mediatek,mt8192-disp-ovl-2l";
1838 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
1839 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1843 compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma";
1848 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
1849 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1853 compatible = "mediatek,mt8186-disp-color", "mediatek,mt8173-disp-color";
1857 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
1858 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1862 compatible = "mediatek,mt8186-dpi";
1867 clock-names = "pixel", "engine", "pll";
1868 assigned-clocks = <&topckgen CLK_TOP_DPI>;
1869 assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>;
1871 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1880 compatible = "mediatek,mt8186-disp-ccorr", "mediatek,mt8192-disp-ccorr";
1884 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
1885 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1889 compatible = "mediatek,mt8186-disp-aal", "mediatek,mt8183-disp-aal";
1893 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1894 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1898 compatible = "mediatek,mt8186-disp-gamma", "mediatek,mt8183-disp-gamma";
1902 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1903 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1907 compatible = "mediatek,mt8186-disp-postmask",
1908 "mediatek,mt8192-disp-postmask";
1912 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1913 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1917 compatible = "mediatek,mt8186-disp-dither", "mediatek,mt8183-disp-dither";
1921 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1922 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1926 compatible = "mediatek,mt8186-dsi";
1931 clock-names = "engine", "digital", "hs";
1933 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1936 phy-names = "dphy";
1945 compatible = "mediatek,mt8186-iommu-mm";
1948 clock-names = "bclk";
1954 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1955 #iommu-cells = <1>;
1959 compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma";
1964 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xf000 0x1000>;
1965 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1968 wpesys: clock-controller@14020000 {
1969 compatible = "mediatek,mt8186-wpesys";
1971 #clock-cells = <1>;
1975 compatible = "mediatek,mt8186-smi-larb";
1979 clock-names = "apb", "smi";
1980 mediatek,larb-id = <8>;
1982 power-domains = <&spm MT8186_POWER_DOMAIN_WPE>;
1985 imgsys1: clock-controller@15020000 {
1986 compatible = "mediatek,mt8186-imgsys1";
1988 #clock-cells = <1>;
1992 compatible = "mediatek,mt8186-smi-larb";
1996 clock-names = "apb", "smi";
1997 mediatek,larb-id = <9>;
1999 power-domains = <&spm MT8186_POWER_DOMAIN_IMG>;
2002 imgsys2: clock-controller@15820000 {
2003 compatible = "mediatek,mt8186-imgsys2";
2005 #clock-cells = <1>;
2009 compatible = "mediatek,mt8186-smi-larb";
2013 clock-names = "apb", "smi";
2014 mediatek,larb-id = <11>;
2016 power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>;
2019 video_decoder: video-decoder@16000000 {
2020 compatible = "mediatek,mt8186-vcodec-dec";
2023 #address-cells = <2>;
2024 #size-cells = <2>;
2025 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
2029 vcodec_core: video-codec@16025000 {
2030 compatible = "mediatek,mtk-vcodec-core";
2049 clock-names = "vdec-sel", "vdec-soc-vdec", "vdec", "vdec-top";
2050 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2051 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3>;
2052 power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>;
2057 compatible = "mediatek,mt8186-smi-larb";
2061 clock-names = "apb", "smi";
2062 mediatek,larb-id = <4>;
2064 power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>;
2067 vdecsys: clock-controller@1602f000 {
2068 compatible = "mediatek,mt8186-vdecsys";
2070 #clock-cells = <1>;
2073 vencsys: clock-controller@17000000 {
2074 compatible = "mediatek,mt8186-vencsys";
2076 #clock-cells = <1>;
2080 compatible = "mediatek,mt8186-smi-larb";
2084 clock-names = "apb", "smi";
2085 mediatek,larb-id = <7>;
2087 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
2090 venc: video-encoder@17020000 {
2091 compatible = "mediatek,mt8186-vcodec-enc", "mediatek,mt8183-vcodec-enc";
2104 clock-names = "venc_sel";
2105 assigned-clocks = <&topckgen CLK_TOP_VENC>;
2106 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3>;
2107 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
2111 jpgenc: jpeg-encoder@17030000 {
2112 compatible = "mediatek,mt8186-jpgenc", "mediatek,mtk-jpgenc";
2116 clock-names = "jpgenc";
2121 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
2124 camsys: clock-controller@1a000000 {
2125 compatible = "mediatek,mt8186-camsys";
2127 #clock-cells = <1>;
2131 compatible = "mediatek,mt8186-smi-larb";
2134 clock-names = "apb", "smi";
2135 mediatek,larb-id = <13>;
2137 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>;
2141 compatible = "mediatek,mt8186-smi-larb";
2144 clock-names = "apb", "smi";
2145 mediatek,larb-id = <14>;
2147 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>;
2151 compatible = "mediatek,mt8186-smi-larb";
2155 clock-names = "apb", "smi";
2156 mediatek,larb-id = <16>;
2158 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWA>;
2162 compatible = "mediatek,mt8186-smi-larb";
2166 clock-names = "apb", "smi";
2167 mediatek,larb-id = <17>;
2169 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWB>;
2172 camsys_rawa: clock-controller@1a04f000 {
2173 compatible = "mediatek,mt8186-camsys_rawa";
2175 #clock-cells = <1>;
2178 camsys_rawb: clock-controller@1a06f000 {
2179 compatible = "mediatek,mt8186-camsys_rawb";
2181 #clock-cells = <1>;
2184 mdpsys: clock-controller@1b000000 {
2185 compatible = "mediatek,mt8186-mdpsys";
2187 #clock-cells = <1>;
2191 compatible = "mediatek,mt8186-smi-larb";
2194 clock-names = "apb", "smi";
2195 mediatek,larb-id = <2>;
2197 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
2200 ipesys: clock-controller@1c000000 {
2201 compatible = "mediatek,mt8186-ipesys";
2203 #clock-cells = <1>;
2207 compatible = "mediatek,mt8186-smi-larb";
2210 clock-names = "apb", "smi";
2211 mediatek,larb-id = <20>;
2213 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>;
2217 compatible = "mediatek,mt8186-smi-larb";
2220 clock-names = "apb", "smi";
2221 mediatek,larb-id = <19>;
2223 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>;
2227 thermal_zones: thermal-zones {
2228 cpu-little0-thermal {
2229 polling-delay = <1000>;
2230 polling-delay-passive = <150>;
2231 thermal-sensors = <&lvts MT8186_LITTLE_CPU0>;
2234 cpu_little0_alert0: trip-alert0 {
2240 cpu_little0_alert1: trip-alert1 {
2246 cpu_little0_crit: trip-crit {
2253 cooling-maps {
2256 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2266 cpu-little1-thermal {
2267 polling-delay = <1000>;
2268 polling-delay-passive = <150>;
2269 thermal-sensors = <&lvts MT8186_LITTLE_CPU1>;
2272 cpu_little1_alert0: trip-alert0 {
2278 cpu_little1_alert1: trip-alert1 {
2284 cpu_little1_crit: trip-crit {
2291 cooling-maps {
2294 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2304 cpu-little2-thermal {
2305 polling-delay = <1000>;
2306 polling-delay-passive = <150>;
2307 thermal-sensors = <&lvts MT8186_LITTLE_CPU2>;
2310 cpu_little2_alert0: trip-alert0 {
2316 cpu_little2_alert1: trip-alert1 {
2322 cpu_little2_crit: trip-crit {
2329 cooling-maps {
2332 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2342 cam-thermal {
2343 polling-delay = <1000>;
2344 polling-delay-passive = <250>;
2345 thermal-sensors = <&lvts MT8186_CAM>;
2348 cam_alert0: trip-alert0 {
2354 cam_alert1: trip-alert1 {
2360 cam_crit: trip-crit {
2368 nna-thermal {
2369 polling-delay = <1000>;
2370 polling-delay-passive = <250>;
2371 thermal-sensors = <&lvts MT8186_NNA>;
2374 nna_alert0: trip-alert0 {
2380 nna_alert1: trip-alert1 {
2386 nna_crit: trip-crit {
2394 adsp-thermal {
2395 polling-delay = <1000>;
2396 polling-delay-passive = <250>;
2397 thermal-sensors = <&lvts MT8186_ADSP>;
2400 adsp_alert0: trip-alert0 {
2406 adsp_alert1: trip-alert1 {
2412 adsp_crit: trip-crit {
2420 gpu-thermal {
2421 polling-delay = <1000>;
2422 polling-delay-passive = <250>;
2423 thermal-sensors = <&lvts MT8186_GPU>;
2426 gpu_alert0: trip-alert0 {
2432 gpu_alert1: trip-alert1 {
2438 gpu_crit: trip-crit {
2445 cooling-maps {
2448 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2453 cpu-big0-thermal {
2454 polling-delay = <1000>;
2455 polling-delay-passive = <100>;
2456 thermal-sensors = <&lvts MT8186_BIG_CPU0>;
2459 cpu_big0_alert0: trip-alert0 {
2465 cpu_big0_alert1: trip-alert1 {
2471 cpu_big0_crit: trip-crit {
2478 cooling-maps {
2481 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2487 cpu-big1-thermal {
2488 polling-delay = <1000>;
2489 polling-delay-passive = <100>;
2490 thermal-sensors = <&lvts MT8186_BIG_CPU1>;
2493 cpu_big1_alert0: trip-alert0 {
2499 cpu_big1_alert1: trip-alert1 {
2505 cpu_big1_crit: trip-crit {
2512 cooling-maps {
2515 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,