Lines Matching +full:mt8183 +full:- +full:mdp3 +full:- +full:rdma
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt8183-clk.h>
9 #include <dt-bindings/gce/mt8183-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8183-larb-port.h>
13 #include <dt-bindings/power/mt8183-power.h>
14 #include <dt-bindings/reset/mt8183-resets.h>
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/thermal/thermal.h>
17 #include <dt-bindings/pinctrl/mt8183-pinfunc.h>
20 compatible = "mediatek,mt8183";
21 interrupt-parent = <&sysirq>;
22 #address-cells = <2>;
23 #size-cells = <2>;
39 ovl-2l0 = &ovl_2l0;
40 ovl-2l1 = &ovl_2l1;
45 cluster0_opp: opp-table-cluster0 {
46 compatible = "operating-points-v2";
47 opp-shared;
48 opp0-793000000 {
49 opp-hz = /bits/ 64 <793000000>;
50 opp-microvolt = <650000>;
51 required-opps = <&opp2_00>;
53 opp0-910000000 {
54 opp-hz = /bits/ 64 <910000000>;
55 opp-microvolt = <687500>;
56 required-opps = <&opp2_01>;
58 opp0-1014000000 {
59 opp-hz = /bits/ 64 <1014000000>;
60 opp-microvolt = <718750>;
61 required-opps = <&opp2_02>;
63 opp0-1131000000 {
64 opp-hz = /bits/ 64 <1131000000>;
65 opp-microvolt = <756250>;
66 required-opps = <&opp2_03>;
68 opp0-1248000000 {
69 opp-hz = /bits/ 64 <1248000000>;
70 opp-microvolt = <800000>;
71 required-opps = <&opp2_04>;
73 opp0-1326000000 {
74 opp-hz = /bits/ 64 <1326000000>;
75 opp-microvolt = <818750>;
76 required-opps = <&opp2_05>;
78 opp0-1417000000 {
79 opp-hz = /bits/ 64 <1417000000>;
80 opp-microvolt = <850000>;
81 required-opps = <&opp2_06>;
83 opp0-1508000000 {
84 opp-hz = /bits/ 64 <1508000000>;
85 opp-microvolt = <868750>;
86 required-opps = <&opp2_07>;
88 opp0-1586000000 {
89 opp-hz = /bits/ 64 <1586000000>;
90 opp-microvolt = <893750>;
91 required-opps = <&opp2_08>;
93 opp0-1625000000 {
94 opp-hz = /bits/ 64 <1625000000>;
95 opp-microvolt = <906250>;
96 required-opps = <&opp2_09>;
98 opp0-1677000000 {
99 opp-hz = /bits/ 64 <1677000000>;
100 opp-microvolt = <931250>;
101 required-opps = <&opp2_10>;
103 opp0-1716000000 {
104 opp-hz = /bits/ 64 <1716000000>;
105 opp-microvolt = <943750>;
106 required-opps = <&opp2_11>;
108 opp0-1781000000 {
109 opp-hz = /bits/ 64 <1781000000>;
110 opp-microvolt = <975000>;
111 required-opps = <&opp2_12>;
113 opp0-1846000000 {
114 opp-hz = /bits/ 64 <1846000000>;
115 opp-microvolt = <1000000>;
116 required-opps = <&opp2_13>;
118 opp0-1924000000 {
119 opp-hz = /bits/ 64 <1924000000>;
120 opp-microvolt = <1025000>;
121 required-opps = <&opp2_14>;
123 opp0-1989000000 {
124 opp-hz = /bits/ 64 <1989000000>;
125 opp-microvolt = <1050000>;
126 required-opps = <&opp2_15>;
129 cluster1_opp: opp-table-cluster1 {
130 compatible = "operating-points-v2";
131 opp-shared;
132 opp1-793000000 {
133 opp-hz = /bits/ 64 <793000000>;
134 opp-microvolt = <700000>;
135 required-opps = <&opp2_00>;
137 opp1-910000000 {
138 opp-hz = /bits/ 64 <910000000>;
139 opp-microvolt = <725000>;
140 required-opps = <&opp2_01>;
142 opp1-1014000000 {
143 opp-hz = /bits/ 64 <1014000000>;
144 opp-microvolt = <750000>;
145 required-opps = <&opp2_02>;
147 opp1-1131000000 {
148 opp-hz = /bits/ 64 <1131000000>;
149 opp-microvolt = <775000>;
150 required-opps = <&opp2_03>;
152 opp1-1248000000 {
153 opp-hz = /bits/ 64 <1248000000>;
154 opp-microvolt = <800000>;
155 required-opps = <&opp2_04>;
157 opp1-1326000000 {
158 opp-hz = /bits/ 64 <1326000000>;
159 opp-microvolt = <825000>;
160 required-opps = <&opp2_05>;
162 opp1-1417000000 {
163 opp-hz = /bits/ 64 <1417000000>;
164 opp-microvolt = <850000>;
165 required-opps = <&opp2_06>;
167 opp1-1508000000 {
168 opp-hz = /bits/ 64 <1508000000>;
169 opp-microvolt = <875000>;
170 required-opps = <&opp2_07>;
172 opp1-1586000000 {
173 opp-hz = /bits/ 64 <1586000000>;
174 opp-microvolt = <900000>;
175 required-opps = <&opp2_08>;
177 opp1-1625000000 {
178 opp-hz = /bits/ 64 <1625000000>;
179 opp-microvolt = <912500>;
180 required-opps = <&opp2_09>;
182 opp1-1677000000 {
183 opp-hz = /bits/ 64 <1677000000>;
184 opp-microvolt = <931250>;
185 required-opps = <&opp2_10>;
187 opp1-1716000000 {
188 opp-hz = /bits/ 64 <1716000000>;
189 opp-microvolt = <950000>;
190 required-opps = <&opp2_11>;
192 opp1-1781000000 {
193 opp-hz = /bits/ 64 <1781000000>;
194 opp-microvolt = <975000>;
195 required-opps = <&opp2_12>;
197 opp1-1846000000 {
198 opp-hz = /bits/ 64 <1846000000>;
199 opp-microvolt = <1000000>;
200 required-opps = <&opp2_13>;
202 opp1-1924000000 {
203 opp-hz = /bits/ 64 <1924000000>;
204 opp-microvolt = <1025000>;
205 required-opps = <&opp2_14>;
207 opp1-1989000000 {
208 opp-hz = /bits/ 64 <1989000000>;
209 opp-microvolt = <1050000>;
210 required-opps = <&opp2_15>;
214 cci_opp: opp-table-cci {
215 compatible = "operating-points-v2";
216 opp-shared;
217 opp2_00: opp-273000000 {
218 opp-hz = /bits/ 64 <273000000>;
219 opp-microvolt = <650000>;
221 opp2_01: opp-338000000 {
222 opp-hz = /bits/ 64 <338000000>;
223 opp-microvolt = <687500>;
225 opp2_02: opp-403000000 {
226 opp-hz = /bits/ 64 <403000000>;
227 opp-microvolt = <718750>;
229 opp2_03: opp-463000000 {
230 opp-hz = /bits/ 64 <463000000>;
231 opp-microvolt = <756250>;
233 opp2_04: opp-546000000 {
234 opp-hz = /bits/ 64 <546000000>;
235 opp-microvolt = <800000>;
237 opp2_05: opp-624000000 {
238 opp-hz = /bits/ 64 <624000000>;
239 opp-microvolt = <818750>;
241 opp2_06: opp-689000000 {
242 opp-hz = /bits/ 64 <689000000>;
243 opp-microvolt = <850000>;
245 opp2_07: opp-767000000 {
246 opp-hz = /bits/ 64 <767000000>;
247 opp-microvolt = <868750>;
249 opp2_08: opp-845000000 {
250 opp-hz = /bits/ 64 <845000000>;
251 opp-microvolt = <893750>;
253 opp2_09: opp-871000000 {
254 opp-hz = /bits/ 64 <871000000>;
255 opp-microvolt = <906250>;
257 opp2_10: opp-923000000 {
258 opp-hz = /bits/ 64 <923000000>;
259 opp-microvolt = <931250>;
261 opp2_11: opp-962000000 {
262 opp-hz = /bits/ 64 <962000000>;
263 opp-microvolt = <943750>;
265 opp2_12: opp-1027000000 {
266 opp-hz = /bits/ 64 <1027000000>;
267 opp-microvolt = <975000>;
269 opp2_13: opp-1092000000 {
270 opp-hz = /bits/ 64 <1092000000>;
271 opp-microvolt = <1000000>;
273 opp2_14: opp-1144000000 {
274 opp-hz = /bits/ 64 <1144000000>;
275 opp-microvolt = <1025000>;
277 opp2_15: opp-1196000000 {
278 opp-hz = /bits/ 64 <1196000000>;
279 opp-microvolt = <1050000>;
284 compatible = "mediatek,mt8183-cci";
287 clock-names = "cci", "intermediate";
288 operating-points-v2 = <&cci_opp>;
292 #address-cells = <1>;
293 #size-cells = <0>;
295 cpu-map {
329 compatible = "arm,cortex-a53";
331 enable-method = "psci";
332 capacity-dmips-mhz = <741>;
333 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
336 clock-names = "cpu", "intermediate";
337 operating-points-v2 = <&cluster0_opp>;
338 dynamic-power-coefficient = <84>;
339 i-cache-size = <32768>;
340 i-cache-line-size = <64>;
341 i-cache-sets = <256>;
342 d-cache-size = <32768>;
343 d-cache-line-size = <64>;
344 d-cache-sets = <128>;
345 next-level-cache = <&l2_0>;
346 #cooling-cells = <2>;
352 compatible = "arm,cortex-a53";
354 enable-method = "psci";
355 capacity-dmips-mhz = <741>;
356 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
359 clock-names = "cpu", "intermediate";
360 operating-points-v2 = <&cluster0_opp>;
361 dynamic-power-coefficient = <84>;
362 i-cache-size = <32768>;
363 i-cache-line-size = <64>;
364 i-cache-sets = <256>;
365 d-cache-size = <32768>;
366 d-cache-line-size = <64>;
367 d-cache-sets = <128>;
368 next-level-cache = <&l2_0>;
369 #cooling-cells = <2>;
375 compatible = "arm,cortex-a53";
377 enable-method = "psci";
378 capacity-dmips-mhz = <741>;
379 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
382 clock-names = "cpu", "intermediate";
383 operating-points-v2 = <&cluster0_opp>;
384 dynamic-power-coefficient = <84>;
385 i-cache-size = <32768>;
386 i-cache-line-size = <64>;
387 i-cache-sets = <256>;
388 d-cache-size = <32768>;
389 d-cache-line-size = <64>;
390 d-cache-sets = <128>;
391 next-level-cache = <&l2_0>;
392 #cooling-cells = <2>;
398 compatible = "arm,cortex-a53";
400 enable-method = "psci";
401 capacity-dmips-mhz = <741>;
402 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
405 clock-names = "cpu", "intermediate";
406 operating-points-v2 = <&cluster0_opp>;
407 dynamic-power-coefficient = <84>;
408 i-cache-size = <32768>;
409 i-cache-line-size = <64>;
410 i-cache-sets = <256>;
411 d-cache-size = <32768>;
412 d-cache-line-size = <64>;
413 d-cache-sets = <128>;
414 next-level-cache = <&l2_0>;
415 #cooling-cells = <2>;
421 compatible = "arm,cortex-a73";
423 enable-method = "psci";
424 capacity-dmips-mhz = <1024>;
425 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
428 clock-names = "cpu", "intermediate";
429 operating-points-v2 = <&cluster1_opp>;
430 dynamic-power-coefficient = <211>;
431 i-cache-size = <65536>;
432 i-cache-line-size = <64>;
433 i-cache-sets = <256>;
434 d-cache-size = <65536>;
435 d-cache-line-size = <64>;
436 d-cache-sets = <256>;
437 next-level-cache = <&l2_1>;
438 #cooling-cells = <2>;
444 compatible = "arm,cortex-a73";
446 enable-method = "psci";
447 capacity-dmips-mhz = <1024>;
448 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
451 clock-names = "cpu", "intermediate";
452 operating-points-v2 = <&cluster1_opp>;
453 dynamic-power-coefficient = <211>;
454 i-cache-size = <65536>;
455 i-cache-line-size = <64>;
456 i-cache-sets = <256>;
457 d-cache-size = <65536>;
458 d-cache-line-size = <64>;
459 d-cache-sets = <256>;
460 next-level-cache = <&l2_1>;
461 #cooling-cells = <2>;
467 compatible = "arm,cortex-a73";
469 enable-method = "psci";
470 capacity-dmips-mhz = <1024>;
471 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
474 clock-names = "cpu", "intermediate";
475 operating-points-v2 = <&cluster1_opp>;
476 dynamic-power-coefficient = <211>;
477 i-cache-size = <65536>;
478 i-cache-line-size = <64>;
479 i-cache-sets = <256>;
480 d-cache-size = <65536>;
481 d-cache-line-size = <64>;
482 d-cache-sets = <256>;
483 next-level-cache = <&l2_1>;
484 #cooling-cells = <2>;
490 compatible = "arm,cortex-a73";
492 enable-method = "psci";
493 capacity-dmips-mhz = <1024>;
494 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
497 clock-names = "cpu", "intermediate";
498 operating-points-v2 = <&cluster1_opp>;
499 dynamic-power-coefficient = <211>;
500 i-cache-size = <65536>;
501 i-cache-line-size = <64>;
502 i-cache-sets = <256>;
503 d-cache-size = <65536>;
504 d-cache-line-size = <64>;
505 d-cache-sets = <256>;
506 next-level-cache = <&l2_1>;
507 #cooling-cells = <2>;
511 idle-states {
512 entry-method = "psci";
514 CPU_SLEEP: cpu-sleep {
515 compatible = "arm,idle-state";
516 local-timer-stop;
517 arm,psci-suspend-param = <0x00010001>;
518 entry-latency-us = <200>;
519 exit-latency-us = <200>;
520 min-residency-us = <800>;
523 CLUSTER_SLEEP0: cluster-sleep-0 {
524 compatible = "arm,idle-state";
525 local-timer-stop;
526 arm,psci-suspend-param = <0x01010001>;
527 entry-latency-us = <250>;
528 exit-latency-us = <400>;
529 min-residency-us = <1000>;
531 CLUSTER_SLEEP1: cluster-sleep-1 {
532 compatible = "arm,idle-state";
533 local-timer-stop;
534 arm,psci-suspend-param = <0x01010001>;
535 entry-latency-us = <250>;
536 exit-latency-us = <400>;
537 min-residency-us = <1300>;
541 l2_0: l2-cache0 {
543 cache-level = <2>;
544 cache-size = <1048576>;
545 cache-line-size = <64>;
546 cache-sets = <1024>;
547 cache-unified;
550 l2_1: l2-cache1 {
552 cache-level = <2>;
553 cache-size = <1048576>;
554 cache-line-size = <64>;
555 cache-sets = <1024>;
556 cache-unified;
560 gpu_opp_table: opp-table-0 {
561 compatible = "operating-points-v2";
562 opp-shared;
564 opp-300000000 {
565 opp-hz = /bits/ 64 <300000000>;
566 opp-microvolt = <625000>;
569 opp-320000000 {
570 opp-hz = /bits/ 64 <320000000>;
571 opp-microvolt = <631250>;
574 opp-340000000 {
575 opp-hz = /bits/ 64 <340000000>;
576 opp-microvolt = <637500>;
579 opp-360000000 {
580 opp-hz = /bits/ 64 <360000000>;
581 opp-microvolt = <643750>;
584 opp-380000000 {
585 opp-hz = /bits/ 64 <380000000>;
586 opp-microvolt = <650000>;
589 opp-400000000 {
590 opp-hz = /bits/ 64 <400000000>;
591 opp-microvolt = <656250>;
594 opp-420000000 {
595 opp-hz = /bits/ 64 <420000000>;
596 opp-microvolt = <662500>;
599 opp-460000000 {
600 opp-hz = /bits/ 64 <460000000>;
601 opp-microvolt = <675000>;
604 opp-500000000 {
605 opp-hz = /bits/ 64 <500000000>;
606 opp-microvolt = <687500>;
609 opp-540000000 {
610 opp-hz = /bits/ 64 <540000000>;
611 opp-microvolt = <700000>;
614 opp-580000000 {
615 opp-hz = /bits/ 64 <580000000>;
616 opp-microvolt = <712500>;
619 opp-620000000 {
620 opp-hz = /bits/ 64 <620000000>;
621 opp-microvolt = <725000>;
624 opp-653000000 {
625 opp-hz = /bits/ 64 <653000000>;
626 opp-microvolt = <743750>;
629 opp-698000000 {
630 opp-hz = /bits/ 64 <698000000>;
631 opp-microvolt = <768750>;
634 opp-743000000 {
635 opp-hz = /bits/ 64 <743000000>;
636 opp-microvolt = <793750>;
639 opp-800000000 {
640 opp-hz = /bits/ 64 <800000000>;
641 opp-microvolt = <825000>;
645 pmu-a53 {
646 compatible = "arm,cortex-a53-pmu";
647 interrupt-parent = <&gic>;
651 pmu-a73 {
652 compatible = "arm,cortex-a73-pmu";
653 interrupt-parent = <&gic>;
658 compatible = "arm,psci-1.0";
662 clk13m: fixed-factor-clock-13m {
663 compatible = "fixed-factor-clock";
664 #clock-cells = <0>;
666 clock-div = <2>;
667 clock-mult = <1>;
668 clock-output-names = "clk13m";
672 compatible = "fixed-clock";
673 #clock-cells = <0>;
674 clock-frequency = <26000000>;
675 clock-output-names = "clk26m";
679 compatible = "arm,armv8-timer";
680 interrupt-parent = <&gic>;
688 #address-cells = <2>;
689 #size-cells = <2>;
690 compatible = "simple-bus";
694 compatible = "mediatek,mt8183-efuse",
697 #address-cells = <1>;
698 #size-cells = <1>;
702 gic: interrupt-controller@c000000 {
703 compatible = "arm,gic-v3";
704 #interrupt-cells = <4>;
705 interrupt-parent = <&gic>;
706 interrupt-controller;
714 ppi-partitions {
715 ppi_cluster0: interrupt-partition-0 {
718 ppi_cluster1: interrupt-partition-1 {
725 compatible = "mediatek,mt8183-mcucfg", "syscon";
727 #clock-cells = <1>;
730 sysirq: interrupt-controller@c530a80 {
731 compatible = "mediatek,mt8183-sysirq",
732 "mediatek,mt6577-sysirq";
733 interrupt-controller;
734 #interrupt-cells = <3>;
735 interrupt-parent = <&gic>;
739 cpu_debug0: cpu-debug@d410000 {
740 compatible = "arm,coresight-cpu-debug", "arm,primecell";
743 clock-names = "apb_pclk";
747 cpu_debug1: cpu-debug@d510000 {
748 compatible = "arm,coresight-cpu-debug", "arm,primecell";
751 clock-names = "apb_pclk";
755 cpu_debug2: cpu-debug@d610000 {
756 compatible = "arm,coresight-cpu-debug", "arm,primecell";
759 clock-names = "apb_pclk";
763 cpu_debug3: cpu-debug@d710000 {
764 compatible = "arm,coresight-cpu-debug", "arm,primecell";
767 clock-names = "apb_pclk";
771 cpu_debug4: cpu-debug@d810000 {
772 compatible = "arm,coresight-cpu-debug", "arm,primecell";
775 clock-names = "apb_pclk";
779 cpu_debug5: cpu-debug@d910000 {
780 compatible = "arm,coresight-cpu-debug", "arm,primecell";
783 clock-names = "apb_pclk";
787 cpu_debug6: cpu-debug@da10000 {
788 compatible = "arm,coresight-cpu-debug", "arm,primecell";
791 clock-names = "apb_pclk";
795 cpu_debug7: cpu-debug@db10000 {
796 compatible = "arm,coresight-cpu-debug", "arm,primecell";
799 clock-names = "apb_pclk";
804 compatible = "mediatek,mt8183-topckgen", "syscon";
806 #clock-cells = <1>;
810 compatible = "mediatek,mt8183-infracfg", "syscon";
812 #clock-cells = <1>;
813 #reset-cells = <1>;
817 compatible = "mediatek,mt8183-pericfg", "syscon";
819 #clock-cells = <1>;
823 compatible = "mediatek,mt8183-pinctrl";
834 reg-names = "iocfg0", "iocfg1", "iocfg2",
838 gpio-controller;
839 #gpio-cells = <2>;
840 gpio-ranges = <&pio 0 0 192>;
841 interrupt-controller;
843 #interrupt-cells = <2>;
847 compatible = "mediatek,mt8183-scpsys", "syscon", "simple-mfd";
851 spm: power-controller {
852 compatible = "mediatek,mt8183-power-controller";
853 #address-cells = <1>;
854 #size-cells = <0>;
855 #power-domain-cells = <1>;
858 power-domain@MT8183_POWER_DOMAIN_AUDIO {
863 clock-names = "audio", "audio1", "audio2";
864 #power-domain-cells = <0>;
867 power-domain@MT8183_POWER_DOMAIN_CONN {
870 #power-domain-cells = <0>;
873 mfg_async: power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC {
875 #address-cells = <1>;
876 #size-cells = <0>;
877 #power-domain-cells = <1>;
879 mfg: power-domain@MT8183_POWER_DOMAIN_MFG {
881 #address-cells = <1>;
882 #size-cells = <0>;
883 #power-domain-cells = <1>;
885 power-domain@MT8183_POWER_DOMAIN_MFG_CORE0 {
887 #power-domain-cells = <0>;
890 power-domain@MT8183_POWER_DOMAIN_MFG_CORE1 {
892 #power-domain-cells = <0>;
895 power-domain@MT8183_POWER_DOMAIN_MFG_2D {
898 #power-domain-cells = <0>;
903 power-domain@MT8183_POWER_DOMAIN_DISP {
916 clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3",
917 "mm-4", "mm-5", "mm-6", "mm-7",
918 "mm-8", "mm-9";
921 #address-cells = <1>;
922 #size-cells = <0>;
923 #power-domain-cells = <1>;
925 power-domain@MT8183_POWER_DOMAIN_CAM {
935 clock-names = "cam", "cam-0", "cam-1",
936 "cam-2", "cam-3", "cam-4",
937 "cam-5", "cam-6";
940 #power-domain-cells = <0>;
943 power-domain@MT8183_POWER_DOMAIN_ISP {
948 clock-names = "isp", "isp-0", "isp-1";
951 #power-domain-cells = <0>;
954 power-domain@MT8183_POWER_DOMAIN_VDEC {
957 #power-domain-cells = <0>;
960 power-domain@MT8183_POWER_DOMAIN_VENC {
963 #power-domain-cells = <0>;
966 power-domain@MT8183_POWER_DOMAIN_VPU_TOP {
976 clock-names = "vpu", "vpu1", "vpu-0", "vpu-1",
977 "vpu-2", "vpu-3", "vpu-4", "vpu-5";
980 #address-cells = <1>;
981 #size-cells = <0>;
982 #power-domain-cells = <1>;
984 power-domain@MT8183_POWER_DOMAIN_VPU_CORE0 {
987 clock-names = "vpu2";
989 #power-domain-cells = <0>;
992 power-domain@MT8183_POWER_DOMAIN_VPU_CORE1 {
995 clock-names = "vpu3";
997 #power-domain-cells = <0>;
1005 compatible = "mediatek,mt8183-wdt";
1007 #reset-cells = <1>;
1011 compatible = "mediatek,mt8183-apmixedsys", "syscon";
1013 #clock-cells = <1>;
1017 compatible = "mediatek,mt8183-pwrap";
1019 reg-names = "pwrap";
1023 clock-names = "spi", "wrap";
1027 compatible = "mediatek,mt6779-keypad";
1031 clock-names = "kpd";
1036 compatible = "mediatek,mt8183-scp";
1039 reg-names = "sram", "cfg";
1042 clock-names = "main";
1043 memory-region = <&scp_mem_reserved>;
1048 compatible = "mediatek,mt8183-timer",
1049 "mediatek,mt6765-timer";
1056 compatible = "mediatek,mt8183-m4u";
1061 #iommu-cells = <1>;
1065 compatible = "mediatek,mt8183-gce";
1068 #mbox-cells = <2>;
1070 clock-names = "gce";
1074 compatible = "mediatek,mt8183-auxadc",
1075 "mediatek,mt8173-auxadc";
1078 clock-names = "main";
1079 #io-channel-cells = <1>;
1084 compatible = "mediatek,mt8183-uart",
1085 "mediatek,mt6577-uart";
1089 clock-names = "baud", "bus";
1094 compatible = "mediatek,mt8183-uart",
1095 "mediatek,mt6577-uart";
1099 clock-names = "baud", "bus";
1104 compatible = "mediatek,mt8183-uart",
1105 "mediatek,mt6577-uart";
1109 clock-names = "baud", "bus";
1114 compatible = "mediatek,mt8183-i2c";
1120 clock-names = "main", "dma";
1121 clock-div = <1>;
1122 #address-cells = <1>;
1123 #size-cells = <0>;
1128 compatible = "mediatek,mt8183-i2c";
1134 clock-names = "main", "dma";
1135 clock-div = <1>;
1136 #address-cells = <1>;
1137 #size-cells = <0>;
1142 compatible = "mediatek,mt8183-i2c";
1149 clock-names = "main", "dma","arb";
1150 clock-div = <1>;
1151 #address-cells = <1>;
1152 #size-cells = <0>;
1157 compatible = "mediatek,mt8183-i2c";
1164 clock-names = "main", "dma", "arb";
1165 clock-div = <1>;
1166 #address-cells = <1>;
1167 #size-cells = <0>;
1172 compatible = "mediatek,mt8183-spi";
1173 #address-cells = <1>;
1174 #size-cells = <0>;
1180 clock-names = "parent-clk", "sel-clk", "spi-clk";
1184 thermal: thermal-sensor@1100b000 {
1185 #thermal-sensor-cells = <1>;
1186 compatible = "mediatek,mt8183-thermal";
1190 clock-names = "therm", "auxadc";
1195 nvmem-cells = <&thermal_calibration>;
1196 nvmem-cell-names = "calibration-data";
1200 compatible = "mediatek,mt8183-svs";
1204 clock-names = "main";
1205 nvmem-cells = <&svs_calibration>,
1207 nvmem-cell-names = "svs-calibration-data",
1208 "t-calibration-data";
1212 compatible = "mediatek,mt8183-disp-pwm";
1215 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1216 #pwm-cells = <2>;
1219 clock-names = "main", "mm";
1223 compatible = "mediatek,mt8183-pwm";
1225 #pwm-cells = <2>;
1232 clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
1237 compatible = "mediatek,mt8183-i2c";
1243 clock-names = "main", "dma";
1244 clock-div = <1>;
1245 #address-cells = <1>;
1246 #size-cells = <0>;
1251 compatible = "mediatek,mt8183-spi";
1252 #address-cells = <1>;
1253 #size-cells = <0>;
1259 clock-names = "parent-clk", "sel-clk", "spi-clk";
1264 compatible = "mediatek,mt8183-i2c";
1270 clock-names = "main", "dma";
1271 clock-div = <1>;
1272 #address-cells = <1>;
1273 #size-cells = <0>;
1278 compatible = "mediatek,mt8183-spi";
1279 #address-cells = <1>;
1280 #size-cells = <0>;
1286 clock-names = "parent-clk", "sel-clk", "spi-clk";
1291 compatible = "mediatek,mt8183-spi";
1292 #address-cells = <1>;
1293 #size-cells = <0>;
1299 clock-names = "parent-clk", "sel-clk", "spi-clk";
1304 compatible = "mediatek,mt8183-i2c";
1311 clock-names = "main", "dma", "arb";
1312 clock-div = <1>;
1313 #address-cells = <1>;
1314 #size-cells = <0>;
1319 compatible = "mediatek,mt8183-i2c";
1326 clock-names = "main", "dma", "arb";
1327 clock-div = <1>;
1328 #address-cells = <1>;
1329 #size-cells = <0>;
1334 compatible = "mediatek,mt8183-i2c";
1341 clock-names = "main", "dma", "arb";
1342 clock-div = <1>;
1343 #address-cells = <1>;
1344 #size-cells = <0>;
1349 compatible = "mediatek,mt8183-i2c";
1356 clock-names = "main", "dma", "arb";
1357 clock-div = <1>;
1358 #address-cells = <1>;
1359 #size-cells = <0>;
1364 compatible = "mediatek,mt8183-spi";
1365 #address-cells = <1>;
1366 #size-cells = <0>;
1372 clock-names = "parent-clk", "sel-clk", "spi-clk";
1377 compatible = "mediatek,mt8183-spi";
1378 #address-cells = <1>;
1379 #size-cells = <0>;
1385 clock-names = "parent-clk", "sel-clk", "spi-clk";
1390 compatible = "mediatek,mt8183-i2c";
1396 clock-names = "main", "dma";
1397 clock-div = <1>;
1398 #address-cells = <1>;
1399 #size-cells = <0>;
1404 compatible = "mediatek,mt8183-i2c";
1410 clock-names = "main", "dma";
1411 clock-div = <1>;
1412 #address-cells = <1>;
1413 #size-cells = <0>;
1418 compatible = "mediatek,mt8183-mtu3", "mediatek,mtu3";
1421 reg-names = "mac", "ippc";
1427 clock-names = "sys_ck", "ref_ck";
1428 mediatek,syscon-wakeup = <&pericfg 0x420 101>;
1429 #address-cells = <2>;
1430 #size-cells = <2>;
1435 compatible = "mediatek,mt8183-xhci",
1436 "mediatek,mtk-xhci";
1438 reg-names = "mac";
1442 clock-names = "sys_ck", "ref_ck";
1447 audiosys: audio-controller@11220000 {
1448 compatible = "mediatek,mt8183-audiosys", "syscon";
1450 #clock-cells = <1>;
1451 afe: mt8183-afe-pcm {
1452 compatible = "mediatek,mt8183-audio";
1455 reset-names = "audiosys";
1456 power-domains =
1500 clock-names = "aud_afe_clk",
1546 compatible = "mediatek,mt8183-mmc";
1553 clock-names = "source", "hclk", "source_cg";
1558 compatible = "mediatek,mt8183-mmc";
1565 clock-names = "source", "hclk", "source_cg";
1569 mipi_tx0: dsi-phy@11e50000 {
1570 compatible = "mediatek,mt8183-mipi-tx";
1573 #clock-cells = <0>;
1574 #phy-cells = <0>;
1575 clock-output-names = "mipi_tx0_pll";
1576 nvmem-cells = <&mipi_tx_calibration>;
1577 nvmem-cell-names = "calibration-data";
1581 compatible = "mediatek,mt8183-efuse",
1584 #address-cells = <1>;
1585 #size-cells = <1>;
1587 socinfo-data1@4c {
1591 socinfo-data2@60 {
1608 u3phy: t-phy@11f40000 {
1609 compatible = "mediatek,mt8183-tphy",
1610 "mediatek,generic-tphy-v2";
1611 #address-cells = <1>;
1612 #size-cells = <1>;
1616 u2port0: usb-phy@0 {
1619 clock-names = "ref";
1620 #phy-cells = <1>;
1625 u3port0: usb-phy@700 {
1628 clock-names = "ref";
1629 #phy-cells = <1>;
1635 compatible = "mediatek,mt8183-mfgcfg", "syscon";
1637 #clock-cells = <1>;
1638 power-domains = <&spm MT8183_POWER_DOMAIN_MFG_ASYNC>;
1642 compatible = "mediatek,mt8183b-mali", "arm,mali-bifrost";
1648 interrupt-names = "job", "mmu", "gpu";
1652 power-domains =
1656 power-domain-names = "core0", "core1", "core2";
1658 operating-points-v2 = <&gpu_opp_table>;
1662 compatible = "mediatek,mt8183-mmsys", "syscon";
1664 #clock-cells = <1>;
1665 #reset-cells = <1>;
1668 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1671 dma-controller0@14001000 {
1672 compatible = "mediatek,mt8183-mdp3-rdma";
1674 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
1675 mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
1677 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1683 #dma-cells = <1>;
1686 mdp3-rsz0@14003000 {
1687 compatible = "mediatek,mt8183-mdp3-rsz";
1689 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
1690 mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>,
1695 mdp3-rsz1@14004000 {
1696 compatible = "mediatek,mt8183-mdp3-rsz";
1698 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
1699 mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ1_SOF>,
1704 dma-controller@14005000 {
1705 compatible = "mediatek,mt8183-mdp3-wrot";
1707 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
1708 mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,
1710 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1713 #dma-cells = <1>;
1716 mdp3-wdma@14006000 {
1717 compatible = "mediatek,mt8183-mdp3-wdma";
1719 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
1720 mediatek,gce-events = <CMDQ_EVENT_MDP_WDMA0_SOF>,
1722 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1728 compatible = "mediatek,mt8183-disp-ovl";
1731 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1734 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
1738 compatible = "mediatek,mt8183-disp-ovl-2l";
1741 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1744 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
1748 compatible = "mediatek,mt8183-disp-ovl-2l";
1751 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1754 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
1757 rdma0: rdma@1400b000 {
1758 compatible = "mediatek,mt8183-disp-rdma";
1761 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1764 mediatek,rdma-fifo-size = <5120>;
1765 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
1768 rdma1: rdma@1400c000 {
1769 compatible = "mediatek,mt8183-disp-rdma";
1772 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1775 mediatek,rdma-fifo-size = <2048>;
1776 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1780 compatible = "mediatek,mt8183-disp-color",
1781 "mediatek,mt8173-disp-color";
1784 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1786 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1790 compatible = "mediatek,mt8183-disp-ccorr";
1793 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1795 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1799 compatible = "mediatek,mt8183-disp-aal";
1802 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1804 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
1808 compatible = "mediatek,mt8183-disp-gamma";
1811 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1813 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1817 compatible = "mediatek,mt8183-disp-dither";
1820 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1822 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
1826 compatible = "mediatek,mt8183-dsi";
1829 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1833 clock-names = "engine", "digital", "hs";
1836 phy-names = "dphy";
1840 compatible = "mediatek,mt8183-dpi";
1843 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1847 clock-names = "pixel", "engine", "pll";
1851 compatible = "mediatek,mt8183-disp-mutex";
1854 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1855 mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
1857 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
1861 compatible = "mediatek,mt8183-smi-larb";
1866 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1867 clock-names = "apb", "smi";
1871 compatible = "mediatek,mt8183-smi-common";
1877 clock-names = "apb", "smi", "gals0", "gals1";
1878 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1881 mdp3-ccorr@1401c000 {
1882 compatible = "mediatek,mt8183-mdp3-ccorr";
1884 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
1885 mediatek,gce-events = <CMDQ_EVENT_MDP_CCORR_SOF>,
1891 compatible = "mediatek,mt8183-imgsys", "syscon";
1893 #clock-cells = <1>;
1897 compatible = "mediatek,mt8183-smi-larb";
1902 clock-names = "apb", "smi", "gals";
1903 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>;
1907 compatible = "mediatek,mt8183-smi-larb";
1912 clock-names = "apb", "smi", "gals";
1913 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>;
1917 compatible = "mediatek,mt8183-vdecsys", "syscon";
1919 #clock-cells = <1>;
1922 vcodec_dec: video-codec@16020000 {
1923 compatible = "mediatek,mt8183-vcodec-dec";
1935 reg-names = "misc", "ld", "top", "cm", "ad", "av", "pp",
1947 power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>;
1949 clock-names = "vdec";
1953 compatible = "mediatek,mt8183-smi-larb";
1957 clock-names = "apb", "smi";
1958 power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>;
1962 compatible = "mediatek,mt8183-vencsys", "syscon";
1964 #clock-cells = <1>;
1968 compatible = "mediatek,mt8183-smi-larb";
1973 clock-names = "apb", "smi";
1974 power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
1977 venc_jpg: jpeg-encoder@17030000 {
1978 compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc";
1983 power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
1985 clock-names = "jpgenc";
1989 compatible = "mediatek,mt8183-ipu_conn", "syscon";
1991 #clock-cells = <1>;
1995 compatible = "mediatek,mt8183-ipu_adl", "syscon";
1997 #clock-cells = <1>;
2001 compatible = "mediatek,mt8183-ipu_core0", "syscon";
2003 #clock-cells = <1>;
2007 compatible = "mediatek,mt8183-ipu_core1", "syscon";
2009 #clock-cells = <1>;
2013 compatible = "mediatek,mt8183-camsys", "syscon";
2015 #clock-cells = <1>;
2019 compatible = "mediatek,mt8183-smi-larb";
2024 clock-names = "apb", "smi", "gals";
2025 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
2029 compatible = "mediatek,mt8183-smi-larb";
2034 clock-names = "apb", "smi", "gals";
2035 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
2039 thermal_zones: thermal-zones {
2040 cpu_thermal: cpu-thermal {
2041 polling-delay-passive = <100>;
2042 polling-delay = <500>;
2043 thermal-sensors = <&thermal 0>;
2044 sustainable-power = <5000>;
2047 threshold: trip-point0 {
2053 target: trip-point1 {
2059 cpu_crit: cpu-crit {
2066 cooling-maps {
2069 cooling-device = <&cpu0
2085 cooling-device = <&cpu4
2102 tzts1: soc-thermal {
2103 polling-delay = <1000>;
2104 polling-delay-passive = <250>;
2105 thermal-sensors = <&thermal 1>;
2106 sustainable-power = <5000>;
2108 soc_alert: trip-alert {
2114 soc_crit: trip-crit {
2122 tzts2: gpu-thermal {
2123 polling-delay = <1000>;
2124 polling-delay-passive = <250>;
2125 thermal-sensors = <&thermal 2>;
2126 sustainable-power = <5000>;
2129 gpu_alert: trip-alert {
2135 gpu_crit: trip-crit {
2143 tzts3: md1-thermal {
2144 polling-delay = <1000>;
2145 polling-delay-passive = <250>;
2146 thermal-sensors = <&thermal 3>;
2147 sustainable-power = <5000>;
2150 md1_alert: trip-alert {
2156 md1_crit: trip-crit {
2164 tzts4: cpu-little-thermal {
2165 polling-delay = <1000>;
2166 polling-delay-passive = <250>;
2167 thermal-sensors = <&thermal 4>;
2168 sustainable-power = <5000>;
2171 cpul_alert: trip-alert {
2177 cpul_crit: trip-crit {
2185 tzts5: cpu-big-thermal {
2186 polling-delay = <1000>;
2187 polling-delay-passive = <250>;
2188 thermal-sensors = <&thermal 5>;
2189 sustainable-power = <5000>;
2192 cpub_alert: trip-alert {
2198 cpub_crit: trip-crit {
2206 tztsABB: tsabb-thermal {
2207 polling-delay = <1000>;
2208 polling-delay-passive = <250>;
2209 thermal-sensors = <&thermal 6>;
2210 sustainable-power = <5000>;
2213 tsabb_alert: trip-alert {
2219 tsabb_crit: trip-crit {