Lines Matching +full:- +full:infracfg
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt8183-clk.h>
9 #include <dt-bindings/gce/mt8183-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8183-larb-port.h>
13 #include <dt-bindings/power/mt8183-power.h>
14 #include <dt-bindings/reset/mt8183-resets.h>
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/thermal/thermal.h>
17 #include <dt-bindings/pinctrl/mt8183-pinfunc.h>
21 interrupt-parent = <&sysirq>;
22 #address-cells = <2>;
23 #size-cells = <2>;
39 ovl-2l0 = &ovl_2l0;
40 ovl-2l1 = &ovl_2l1;
45 cluster0_opp: opp-table-cluster0 {
46 compatible = "operating-points-v2";
47 opp-shared;
48 opp0-793000000 {
49 opp-hz = /bits/ 64 <793000000>;
50 opp-microvolt = <650000>;
51 required-opps = <&opp2_00>;
53 opp0-910000000 {
54 opp-hz = /bits/ 64 <910000000>;
55 opp-microvolt = <687500>;
56 required-opps = <&opp2_01>;
58 opp0-1014000000 {
59 opp-hz = /bits/ 64 <1014000000>;
60 opp-microvolt = <718750>;
61 required-opps = <&opp2_02>;
63 opp0-1131000000 {
64 opp-hz = /bits/ 64 <1131000000>;
65 opp-microvolt = <756250>;
66 required-opps = <&opp2_03>;
68 opp0-1248000000 {
69 opp-hz = /bits/ 64 <1248000000>;
70 opp-microvolt = <800000>;
71 required-opps = <&opp2_04>;
73 opp0-1326000000 {
74 opp-hz = /bits/ 64 <1326000000>;
75 opp-microvolt = <818750>;
76 required-opps = <&opp2_05>;
78 opp0-1417000000 {
79 opp-hz = /bits/ 64 <1417000000>;
80 opp-microvolt = <850000>;
81 required-opps = <&opp2_06>;
83 opp0-1508000000 {
84 opp-hz = /bits/ 64 <1508000000>;
85 opp-microvolt = <868750>;
86 required-opps = <&opp2_07>;
88 opp0-1586000000 {
89 opp-hz = /bits/ 64 <1586000000>;
90 opp-microvolt = <893750>;
91 required-opps = <&opp2_08>;
93 opp0-1625000000 {
94 opp-hz = /bits/ 64 <1625000000>;
95 opp-microvolt = <906250>;
96 required-opps = <&opp2_09>;
98 opp0-1677000000 {
99 opp-hz = /bits/ 64 <1677000000>;
100 opp-microvolt = <931250>;
101 required-opps = <&opp2_10>;
103 opp0-1716000000 {
104 opp-hz = /bits/ 64 <1716000000>;
105 opp-microvolt = <943750>;
106 required-opps = <&opp2_11>;
108 opp0-1781000000 {
109 opp-hz = /bits/ 64 <1781000000>;
110 opp-microvolt = <975000>;
111 required-opps = <&opp2_12>;
113 opp0-1846000000 {
114 opp-hz = /bits/ 64 <1846000000>;
115 opp-microvolt = <1000000>;
116 required-opps = <&opp2_13>;
118 opp0-1924000000 {
119 opp-hz = /bits/ 64 <1924000000>;
120 opp-microvolt = <1025000>;
121 required-opps = <&opp2_14>;
123 opp0-1989000000 {
124 opp-hz = /bits/ 64 <1989000000>;
125 opp-microvolt = <1050000>;
126 required-opps = <&opp2_15>;
129 cluster1_opp: opp-table-cluster1 {
130 compatible = "operating-points-v2";
131 opp-shared;
132 opp1-793000000 {
133 opp-hz = /bits/ 64 <793000000>;
134 opp-microvolt = <700000>;
135 required-opps = <&opp2_00>;
137 opp1-910000000 {
138 opp-hz = /bits/ 64 <910000000>;
139 opp-microvolt = <725000>;
140 required-opps = <&opp2_01>;
142 opp1-1014000000 {
143 opp-hz = /bits/ 64 <1014000000>;
144 opp-microvolt = <750000>;
145 required-opps = <&opp2_02>;
147 opp1-1131000000 {
148 opp-hz = /bits/ 64 <1131000000>;
149 opp-microvolt = <775000>;
150 required-opps = <&opp2_03>;
152 opp1-1248000000 {
153 opp-hz = /bits/ 64 <1248000000>;
154 opp-microvolt = <800000>;
155 required-opps = <&opp2_04>;
157 opp1-1326000000 {
158 opp-hz = /bits/ 64 <1326000000>;
159 opp-microvolt = <825000>;
160 required-opps = <&opp2_05>;
162 opp1-1417000000 {
163 opp-hz = /bits/ 64 <1417000000>;
164 opp-microvolt = <850000>;
165 required-opps = <&opp2_06>;
167 opp1-1508000000 {
168 opp-hz = /bits/ 64 <1508000000>;
169 opp-microvolt = <875000>;
170 required-opps = <&opp2_07>;
172 opp1-1586000000 {
173 opp-hz = /bits/ 64 <1586000000>;
174 opp-microvolt = <900000>;
175 required-opps = <&opp2_08>;
177 opp1-1625000000 {
178 opp-hz = /bits/ 64 <1625000000>;
179 opp-microvolt = <912500>;
180 required-opps = <&opp2_09>;
182 opp1-1677000000 {
183 opp-hz = /bits/ 64 <1677000000>;
184 opp-microvolt = <931250>;
185 required-opps = <&opp2_10>;
187 opp1-1716000000 {
188 opp-hz = /bits/ 64 <1716000000>;
189 opp-microvolt = <950000>;
190 required-opps = <&opp2_11>;
192 opp1-1781000000 {
193 opp-hz = /bits/ 64 <1781000000>;
194 opp-microvolt = <975000>;
195 required-opps = <&opp2_12>;
197 opp1-1846000000 {
198 opp-hz = /bits/ 64 <1846000000>;
199 opp-microvolt = <1000000>;
200 required-opps = <&opp2_13>;
202 opp1-1924000000 {
203 opp-hz = /bits/ 64 <1924000000>;
204 opp-microvolt = <1025000>;
205 required-opps = <&opp2_14>;
207 opp1-1989000000 {
208 opp-hz = /bits/ 64 <1989000000>;
209 opp-microvolt = <1050000>;
210 required-opps = <&opp2_15>;
214 cci_opp: opp-table-cci {
215 compatible = "operating-points-v2";
216 opp-shared;
217 opp2_00: opp-273000000 {
218 opp-hz = /bits/ 64 <273000000>;
219 opp-microvolt = <650000>;
221 opp2_01: opp-338000000 {
222 opp-hz = /bits/ 64 <338000000>;
223 opp-microvolt = <687500>;
225 opp2_02: opp-403000000 {
226 opp-hz = /bits/ 64 <403000000>;
227 opp-microvolt = <718750>;
229 opp2_03: opp-463000000 {
230 opp-hz = /bits/ 64 <463000000>;
231 opp-microvolt = <756250>;
233 opp2_04: opp-546000000 {
234 opp-hz = /bits/ 64 <546000000>;
235 opp-microvolt = <800000>;
237 opp2_05: opp-624000000 {
238 opp-hz = /bits/ 64 <624000000>;
239 opp-microvolt = <818750>;
241 opp2_06: opp-689000000 {
242 opp-hz = /bits/ 64 <689000000>;
243 opp-microvolt = <850000>;
245 opp2_07: opp-767000000 {
246 opp-hz = /bits/ 64 <767000000>;
247 opp-microvolt = <868750>;
249 opp2_08: opp-845000000 {
250 opp-hz = /bits/ 64 <845000000>;
251 opp-microvolt = <893750>;
253 opp2_09: opp-871000000 {
254 opp-hz = /bits/ 64 <871000000>;
255 opp-microvolt = <906250>;
257 opp2_10: opp-923000000 {
258 opp-hz = /bits/ 64 <923000000>;
259 opp-microvolt = <931250>;
261 opp2_11: opp-962000000 {
262 opp-hz = /bits/ 64 <962000000>;
263 opp-microvolt = <943750>;
265 opp2_12: opp-1027000000 {
266 opp-hz = /bits/ 64 <1027000000>;
267 opp-microvolt = <975000>;
269 opp2_13: opp-1092000000 {
270 opp-hz = /bits/ 64 <1092000000>;
271 opp-microvolt = <1000000>;
273 opp2_14: opp-1144000000 {
274 opp-hz = /bits/ 64 <1144000000>;
275 opp-microvolt = <1025000>;
277 opp2_15: opp-1196000000 {
278 opp-hz = /bits/ 64 <1196000000>;
279 opp-microvolt = <1050000>;
284 compatible = "mediatek,mt8183-cci";
287 clock-names = "cci", "intermediate";
288 operating-points-v2 = <&cci_opp>;
292 #address-cells = <1>;
293 #size-cells = <0>;
295 cpu-map {
329 compatible = "arm,cortex-a53";
331 enable-method = "psci";
332 capacity-dmips-mhz = <741>;
333 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
336 clock-names = "cpu", "intermediate";
337 operating-points-v2 = <&cluster0_opp>;
338 dynamic-power-coefficient = <84>;
339 i-cache-size = <32768>;
340 i-cache-line-size = <64>;
341 i-cache-sets = <256>;
342 d-cache-size = <32768>;
343 d-cache-line-size = <64>;
344 d-cache-sets = <128>;
345 next-level-cache = <&l2_0>;
346 #cooling-cells = <2>;
352 compatible = "arm,cortex-a53";
354 enable-method = "psci";
355 capacity-dmips-mhz = <741>;
356 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
359 clock-names = "cpu", "intermediate";
360 operating-points-v2 = <&cluster0_opp>;
361 dynamic-power-coefficient = <84>;
362 i-cache-size = <32768>;
363 i-cache-line-size = <64>;
364 i-cache-sets = <256>;
365 d-cache-size = <32768>;
366 d-cache-line-size = <64>;
367 d-cache-sets = <128>;
368 next-level-cache = <&l2_0>;
369 #cooling-cells = <2>;
375 compatible = "arm,cortex-a53";
377 enable-method = "psci";
378 capacity-dmips-mhz = <741>;
379 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
382 clock-names = "cpu", "intermediate";
383 operating-points-v2 = <&cluster0_opp>;
384 dynamic-power-coefficient = <84>;
385 i-cache-size = <32768>;
386 i-cache-line-size = <64>;
387 i-cache-sets = <256>;
388 d-cache-size = <32768>;
389 d-cache-line-size = <64>;
390 d-cache-sets = <128>;
391 next-level-cache = <&l2_0>;
392 #cooling-cells = <2>;
398 compatible = "arm,cortex-a53";
400 enable-method = "psci";
401 capacity-dmips-mhz = <741>;
402 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
405 clock-names = "cpu", "intermediate";
406 operating-points-v2 = <&cluster0_opp>;
407 dynamic-power-coefficient = <84>;
408 i-cache-size = <32768>;
409 i-cache-line-size = <64>;
410 i-cache-sets = <256>;
411 d-cache-size = <32768>;
412 d-cache-line-size = <64>;
413 d-cache-sets = <128>;
414 next-level-cache = <&l2_0>;
415 #cooling-cells = <2>;
421 compatible = "arm,cortex-a73";
423 enable-method = "psci";
424 capacity-dmips-mhz = <1024>;
425 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
428 clock-names = "cpu", "intermediate";
429 operating-points-v2 = <&cluster1_opp>;
430 dynamic-power-coefficient = <211>;
431 i-cache-size = <65536>;
432 i-cache-line-size = <64>;
433 i-cache-sets = <256>;
434 d-cache-size = <65536>;
435 d-cache-line-size = <64>;
436 d-cache-sets = <256>;
437 next-level-cache = <&l2_1>;
438 #cooling-cells = <2>;
444 compatible = "arm,cortex-a73";
446 enable-method = "psci";
447 capacity-dmips-mhz = <1024>;
448 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
451 clock-names = "cpu", "intermediate";
452 operating-points-v2 = <&cluster1_opp>;
453 dynamic-power-coefficient = <211>;
454 i-cache-size = <65536>;
455 i-cache-line-size = <64>;
456 i-cache-sets = <256>;
457 d-cache-size = <65536>;
458 d-cache-line-size = <64>;
459 d-cache-sets = <256>;
460 next-level-cache = <&l2_1>;
461 #cooling-cells = <2>;
467 compatible = "arm,cortex-a73";
469 enable-method = "psci";
470 capacity-dmips-mhz = <1024>;
471 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
474 clock-names = "cpu", "intermediate";
475 operating-points-v2 = <&cluster1_opp>;
476 dynamic-power-coefficient = <211>;
477 i-cache-size = <65536>;
478 i-cache-line-size = <64>;
479 i-cache-sets = <256>;
480 d-cache-size = <65536>;
481 d-cache-line-size = <64>;
482 d-cache-sets = <256>;
483 next-level-cache = <&l2_1>;
484 #cooling-cells = <2>;
490 compatible = "arm,cortex-a73";
492 enable-method = "psci";
493 capacity-dmips-mhz = <1024>;
494 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
497 clock-names = "cpu", "intermediate";
498 operating-points-v2 = <&cluster1_opp>;
499 dynamic-power-coefficient = <211>;
500 i-cache-size = <65536>;
501 i-cache-line-size = <64>;
502 i-cache-sets = <256>;
503 d-cache-size = <65536>;
504 d-cache-line-size = <64>;
505 d-cache-sets = <256>;
506 next-level-cache = <&l2_1>;
507 #cooling-cells = <2>;
511 idle-states {
512 entry-method = "psci";
514 CPU_SLEEP: cpu-sleep {
515 compatible = "arm,idle-state";
516 local-timer-stop;
517 arm,psci-suspend-param = <0x00010001>;
518 entry-latency-us = <200>;
519 exit-latency-us = <200>;
520 min-residency-us = <800>;
523 CLUSTER_SLEEP0: cluster-sleep-0 {
524 compatible = "arm,idle-state";
525 local-timer-stop;
526 arm,psci-suspend-param = <0x01010001>;
527 entry-latency-us = <250>;
528 exit-latency-us = <400>;
529 min-residency-us = <1000>;
531 CLUSTER_SLEEP1: cluster-sleep-1 {
532 compatible = "arm,idle-state";
533 local-timer-stop;
534 arm,psci-suspend-param = <0x01010001>;
535 entry-latency-us = <250>;
536 exit-latency-us = <400>;
537 min-residency-us = <1300>;
541 l2_0: l2-cache0 {
543 cache-level = <2>;
544 cache-size = <1048576>;
545 cache-line-size = <64>;
546 cache-sets = <1024>;
547 cache-unified;
550 l2_1: l2-cache1 {
552 cache-level = <2>;
553 cache-size = <1048576>;
554 cache-line-size = <64>;
555 cache-sets = <1024>;
556 cache-unified;
560 gpu_opp_table: opp-table-0 {
561 compatible = "operating-points-v2";
562 opp-shared;
564 opp-300000000 {
565 opp-hz = /bits/ 64 <300000000>;
566 opp-microvolt = <625000>;
569 opp-320000000 {
570 opp-hz = /bits/ 64 <320000000>;
571 opp-microvolt = <631250>;
574 opp-340000000 {
575 opp-hz = /bits/ 64 <340000000>;
576 opp-microvolt = <637500>;
579 opp-360000000 {
580 opp-hz = /bits/ 64 <360000000>;
581 opp-microvolt = <643750>;
584 opp-380000000 {
585 opp-hz = /bits/ 64 <380000000>;
586 opp-microvolt = <650000>;
589 opp-400000000 {
590 opp-hz = /bits/ 64 <400000000>;
591 opp-microvolt = <656250>;
594 opp-420000000 {
595 opp-hz = /bits/ 64 <420000000>;
596 opp-microvolt = <662500>;
599 opp-460000000 {
600 opp-hz = /bits/ 64 <460000000>;
601 opp-microvolt = <675000>;
604 opp-500000000 {
605 opp-hz = /bits/ 64 <500000000>;
606 opp-microvolt = <687500>;
609 opp-540000000 {
610 opp-hz = /bits/ 64 <540000000>;
611 opp-microvolt = <700000>;
614 opp-580000000 {
615 opp-hz = /bits/ 64 <580000000>;
616 opp-microvolt = <712500>;
619 opp-620000000 {
620 opp-hz = /bits/ 64 <620000000>;
621 opp-microvolt = <725000>;
624 opp-653000000 {
625 opp-hz = /bits/ 64 <653000000>;
626 opp-microvolt = <743750>;
629 opp-698000000 {
630 opp-hz = /bits/ 64 <698000000>;
631 opp-microvolt = <768750>;
634 opp-743000000 {
635 opp-hz = /bits/ 64 <743000000>;
636 opp-microvolt = <793750>;
639 opp-800000000 {
640 opp-hz = /bits/ 64 <800000000>;
641 opp-microvolt = <825000>;
645 pmu-a53 {
646 compatible = "arm,cortex-a53-pmu";
647 interrupt-parent = <&gic>;
651 pmu-a73 {
652 compatible = "arm,cortex-a73-pmu";
653 interrupt-parent = <&gic>;
658 compatible = "arm,psci-1.0";
662 clk13m: fixed-factor-clock-13m {
663 compatible = "fixed-factor-clock";
664 #clock-cells = <0>;
666 clock-div = <2>;
667 clock-mult = <1>;
668 clock-output-names = "clk13m";
672 compatible = "fixed-clock";
673 #clock-cells = <0>;
674 clock-frequency = <26000000>;
675 clock-output-names = "clk26m";
679 compatible = "arm,armv8-timer";
680 interrupt-parent = <&gic>;
688 #address-cells = <2>;
689 #size-cells = <2>;
690 compatible = "simple-bus";
694 compatible = "mediatek,mt8183-efuse",
697 #address-cells = <1>;
698 #size-cells = <1>;
702 gic: interrupt-controller@c000000 {
703 compatible = "arm,gic-v3";
704 #interrupt-cells = <4>;
705 interrupt-parent = <&gic>;
706 interrupt-controller;
714 ppi-partitions {
715 ppi_cluster0: interrupt-partition-0 {
718 ppi_cluster1: interrupt-partition-1 {
725 compatible = "mediatek,mt8183-mcucfg", "syscon";
727 #clock-cells = <1>;
730 sysirq: interrupt-controller@c530a80 {
731 compatible = "mediatek,mt8183-sysirq",
732 "mediatek,mt6577-sysirq";
733 interrupt-controller;
734 #interrupt-cells = <3>;
735 interrupt-parent = <&gic>;
739 cpu_debug0: cpu-debug@d410000 {
740 compatible = "arm,coresight-cpu-debug", "arm,primecell";
742 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
743 clock-names = "apb_pclk";
747 cpu_debug1: cpu-debug@d510000 {
748 compatible = "arm,coresight-cpu-debug", "arm,primecell";
750 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
751 clock-names = "apb_pclk";
755 cpu_debug2: cpu-debug@d610000 {
756 compatible = "arm,coresight-cpu-debug", "arm,primecell";
758 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
759 clock-names = "apb_pclk";
763 cpu_debug3: cpu-debug@d710000 {
764 compatible = "arm,coresight-cpu-debug", "arm,primecell";
766 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
767 clock-names = "apb_pclk";
771 cpu_debug4: cpu-debug@d810000 {
772 compatible = "arm,coresight-cpu-debug", "arm,primecell";
774 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
775 clock-names = "apb_pclk";
779 cpu_debug5: cpu-debug@d910000 {
780 compatible = "arm,coresight-cpu-debug", "arm,primecell";
782 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
783 clock-names = "apb_pclk";
787 cpu_debug6: cpu-debug@da10000 {
788 compatible = "arm,coresight-cpu-debug", "arm,primecell";
790 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
791 clock-names = "apb_pclk";
795 cpu_debug7: cpu-debug@db10000 {
796 compatible = "arm,coresight-cpu-debug", "arm,primecell";
798 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
799 clock-names = "apb_pclk";
804 compatible = "mediatek,mt8183-topckgen", "syscon";
806 #clock-cells = <1>;
809 infracfg: syscon@10001000 {
810 compatible = "mediatek,mt8183-infracfg", "syscon";
812 #clock-cells = <1>;
813 #reset-cells = <1>;
817 compatible = "mediatek,mt8183-pericfg", "syscon";
819 #clock-cells = <1>;
823 compatible = "mediatek,mt8183-pinctrl";
834 reg-names = "iocfg0", "iocfg1", "iocfg2",
838 gpio-controller;
839 #gpio-cells = <2>;
840 gpio-ranges = <&pio 0 0 192>;
841 interrupt-controller;
843 #interrupt-cells = <2>;
847 compatible = "mediatek,mt8183-scpsys", "syscon", "simple-mfd";
851 spm: power-controller {
852 compatible = "mediatek,mt8183-power-controller";
853 #address-cells = <1>;
854 #size-cells = <0>;
855 #power-domain-cells = <1>;
858 power-domain@MT8183_POWER_DOMAIN_AUDIO {
861 <&infracfg CLK_INFRA_AUDIO>,
862 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>;
863 clock-names = "audio", "audio1", "audio2";
864 #power-domain-cells = <0>;
867 power-domain@MT8183_POWER_DOMAIN_CONN {
869 mediatek,infracfg = <&infracfg>;
870 #power-domain-cells = <0>;
873 mfg_async: power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC {
875 #address-cells = <1>;
876 #size-cells = <0>;
877 #power-domain-cells = <1>;
879 mfg: power-domain@MT8183_POWER_DOMAIN_MFG {
881 #address-cells = <1>;
882 #size-cells = <0>;
883 #power-domain-cells = <1>;
885 power-domain@MT8183_POWER_DOMAIN_MFG_CORE0 {
887 #power-domain-cells = <0>;
890 power-domain@MT8183_POWER_DOMAIN_MFG_CORE1 {
892 #power-domain-cells = <0>;
895 power-domain@MT8183_POWER_DOMAIN_MFG_2D {
897 mediatek,infracfg = <&infracfg>;
898 #power-domain-cells = <0>;
903 power-domain@MT8183_POWER_DOMAIN_DISP {
916 clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3",
917 "mm-4", "mm-5", "mm-6", "mm-7",
918 "mm-8", "mm-9";
919 mediatek,infracfg = <&infracfg>;
921 #address-cells = <1>;
922 #size-cells = <0>;
923 #power-domain-cells = <1>;
925 power-domain@MT8183_POWER_DOMAIN_CAM {
935 clock-names = "cam", "cam-0", "cam-1",
936 "cam-2", "cam-3", "cam-4",
937 "cam-5", "cam-6";
938 mediatek,infracfg = <&infracfg>;
940 #power-domain-cells = <0>;
943 power-domain@MT8183_POWER_DOMAIN_ISP {
948 clock-names = "isp", "isp-0", "isp-1";
949 mediatek,infracfg = <&infracfg>;
951 #power-domain-cells = <0>;
954 power-domain@MT8183_POWER_DOMAIN_VDEC {
957 #power-domain-cells = <0>;
960 power-domain@MT8183_POWER_DOMAIN_VENC {
963 #power-domain-cells = <0>;
966 power-domain@MT8183_POWER_DOMAIN_VPU_TOP {
976 clock-names = "vpu", "vpu1", "vpu-0", "vpu-1",
977 "vpu-2", "vpu-3", "vpu-4", "vpu-5";
978 mediatek,infracfg = <&infracfg>;
980 #address-cells = <1>;
981 #size-cells = <0>;
982 #power-domain-cells = <1>;
984 power-domain@MT8183_POWER_DOMAIN_VPU_CORE0 {
987 clock-names = "vpu2";
988 mediatek,infracfg = <&infracfg>;
989 #power-domain-cells = <0>;
992 power-domain@MT8183_POWER_DOMAIN_VPU_CORE1 {
995 clock-names = "vpu3";
996 mediatek,infracfg = <&infracfg>;
997 #power-domain-cells = <0>;
1005 compatible = "mediatek,mt8183-wdt";
1007 #reset-cells = <1>;
1011 compatible = "mediatek,mt8183-apmixedsys", "syscon";
1013 #clock-cells = <1>;
1017 compatible = "mediatek,mt8183-pwrap";
1019 reg-names = "pwrap";
1022 <&infracfg CLK_INFRA_PMIC_AP>;
1023 clock-names = "spi", "wrap";
1027 compatible = "mediatek,mt8183-keypad",
1028 "mediatek,mt6779-keypad";
1032 clock-names = "kpd";
1037 compatible = "mediatek,mt8183-scp";
1040 reg-names = "sram", "cfg";
1042 clocks = <&infracfg CLK_INFRA_SCPSYS>;
1043 clock-names = "main";
1044 memory-region = <&scp_mem_reserved>;
1049 compatible = "mediatek,mt8183-timer",
1050 "mediatek,mt6765-timer";
1057 compatible = "mediatek,mt8183-m4u";
1062 #iommu-cells = <1>;
1066 compatible = "mediatek,mt8183-gce";
1069 #mbox-cells = <2>;
1070 clocks = <&infracfg CLK_INFRA_GCE>;
1071 clock-names = "gce";
1075 compatible = "mediatek,mt8183-auxadc",
1076 "mediatek,mt8173-auxadc";
1078 clocks = <&infracfg CLK_INFRA_AUXADC>;
1079 clock-names = "main";
1080 #io-channel-cells = <1>;
1085 compatible = "mediatek,mt8183-uart",
1086 "mediatek,mt6577-uart";
1089 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
1090 clock-names = "baud", "bus";
1095 compatible = "mediatek,mt8183-uart",
1096 "mediatek,mt6577-uart";
1099 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
1100 clock-names = "baud", "bus";
1105 compatible = "mediatek,mt8183-uart",
1106 "mediatek,mt6577-uart";
1109 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
1110 clock-names = "baud", "bus";
1115 compatible = "mediatek,mt8183-i2c";
1119 clocks = <&infracfg CLK_INFRA_I2C6>,
1120 <&infracfg CLK_INFRA_AP_DMA>;
1121 clock-names = "main", "dma";
1122 clock-div = <1>;
1123 #address-cells = <1>;
1124 #size-cells = <0>;
1129 compatible = "mediatek,mt8183-i2c";
1133 clocks = <&infracfg CLK_INFRA_I2C0>,
1134 <&infracfg CLK_INFRA_AP_DMA>;
1135 clock-names = "main", "dma";
1136 clock-div = <1>;
1137 #address-cells = <1>;
1138 #size-cells = <0>;
1143 compatible = "mediatek,mt8183-i2c";
1147 clocks = <&infracfg CLK_INFRA_I2C1>,
1148 <&infracfg CLK_INFRA_AP_DMA>,
1149 <&infracfg CLK_INFRA_I2C1_ARBITER>;
1150 clock-names = "main", "dma","arb";
1151 clock-div = <1>;
1152 #address-cells = <1>;
1153 #size-cells = <0>;
1158 compatible = "mediatek,mt8183-i2c";
1162 clocks = <&infracfg CLK_INFRA_I2C2>,
1163 <&infracfg CLK_INFRA_AP_DMA>,
1164 <&infracfg CLK_INFRA_I2C2_ARBITER>;
1165 clock-names = "main", "dma", "arb";
1166 clock-div = <1>;
1167 #address-cells = <1>;
1168 #size-cells = <0>;
1173 compatible = "mediatek,mt8183-spi";
1174 #address-cells = <1>;
1175 #size-cells = <0>;
1180 <&infracfg CLK_INFRA_SPI0>;
1181 clock-names = "parent-clk", "sel-clk", "spi-clk";
1185 thermal: thermal-sensor@1100b000 {
1186 #thermal-sensor-cells = <1>;
1187 compatible = "mediatek,mt8183-thermal";
1189 clocks = <&infracfg CLK_INFRA_THERM>,
1190 <&infracfg CLK_INFRA_AUXADC>;
1191 clock-names = "therm", "auxadc";
1192 resets = <&infracfg MT8183_INFRACFG_AO_THERM_SW_RST>;
1196 nvmem-cells = <&thermal_calibration>;
1197 nvmem-cell-names = "calibration-data";
1201 compatible = "mediatek,mt8183-svs";
1204 clocks = <&infracfg CLK_INFRA_THERM>;
1205 clock-names = "main";
1206 nvmem-cells = <&svs_calibration>,
1208 nvmem-cell-names = "svs-calibration-data",
1209 "t-calibration-data";
1213 compatible = "mediatek,mt8183-disp-pwm";
1216 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1217 #pwm-cells = <2>;
1219 <&infracfg CLK_INFRA_DISP_PWM>;
1220 clock-names = "main", "mm";
1224 compatible = "mediatek,mt8183-pwm";
1226 #pwm-cells = <2>;
1227 clocks = <&infracfg CLK_INFRA_PWM>,
1228 <&infracfg CLK_INFRA_PWM_HCLK>,
1229 <&infracfg CLK_INFRA_PWM1>,
1230 <&infracfg CLK_INFRA_PWM2>,
1231 <&infracfg CLK_INFRA_PWM3>,
1232 <&infracfg CLK_INFRA_PWM4>;
1233 clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
1238 compatible = "mediatek,mt8183-i2c";
1242 clocks = <&infracfg CLK_INFRA_I2C3>,
1243 <&infracfg CLK_INFRA_AP_DMA>;
1244 clock-names = "main", "dma";
1245 clock-div = <1>;
1246 #address-cells = <1>;
1247 #size-cells = <0>;
1252 compatible = "mediatek,mt8183-spi";
1253 #address-cells = <1>;
1254 #size-cells = <0>;
1259 <&infracfg CLK_INFRA_SPI1>;
1260 clock-names = "parent-clk", "sel-clk", "spi-clk";
1265 compatible = "mediatek,mt8183-i2c";
1269 clocks = <&infracfg CLK_INFRA_I2C4>,
1270 <&infracfg CLK_INFRA_AP_DMA>;
1271 clock-names = "main", "dma";
1272 clock-div = <1>;
1273 #address-cells = <1>;
1274 #size-cells = <0>;
1279 compatible = "mediatek,mt8183-spi";
1280 #address-cells = <1>;
1281 #size-cells = <0>;
1286 <&infracfg CLK_INFRA_SPI2>;
1287 clock-names = "parent-clk", "sel-clk", "spi-clk";
1292 compatible = "mediatek,mt8183-spi";
1293 #address-cells = <1>;
1294 #size-cells = <0>;
1299 <&infracfg CLK_INFRA_SPI3>;
1300 clock-names = "parent-clk", "sel-clk", "spi-clk";
1305 compatible = "mediatek,mt8183-i2c";
1309 clocks = <&infracfg CLK_INFRA_I2C1_IMM>,
1310 <&infracfg CLK_INFRA_AP_DMA>,
1311 <&infracfg CLK_INFRA_I2C1_ARBITER>;
1312 clock-names = "main", "dma", "arb";
1313 clock-div = <1>;
1314 #address-cells = <1>;
1315 #size-cells = <0>;
1320 compatible = "mediatek,mt8183-i2c";
1324 clocks = <&infracfg CLK_INFRA_I2C2_IMM>,
1325 <&infracfg CLK_INFRA_AP_DMA>,
1326 <&infracfg CLK_INFRA_I2C2_ARBITER>;
1327 clock-names = "main", "dma", "arb";
1328 clock-div = <1>;
1329 #address-cells = <1>;
1330 #size-cells = <0>;
1335 compatible = "mediatek,mt8183-i2c";
1339 clocks = <&infracfg CLK_INFRA_I2C5>,
1340 <&infracfg CLK_INFRA_AP_DMA>,
1341 <&infracfg CLK_INFRA_I2C5_ARBITER>;
1342 clock-names = "main", "dma", "arb";
1343 clock-div = <1>;
1344 #address-cells = <1>;
1345 #size-cells = <0>;
1350 compatible = "mediatek,mt8183-i2c";
1354 clocks = <&infracfg CLK_INFRA_I2C5_IMM>,
1355 <&infracfg CLK_INFRA_AP_DMA>,
1356 <&infracfg CLK_INFRA_I2C5_ARBITER>;
1357 clock-names = "main", "dma", "arb";
1358 clock-div = <1>;
1359 #address-cells = <1>;
1360 #size-cells = <0>;
1365 compatible = "mediatek,mt8183-spi";
1366 #address-cells = <1>;
1367 #size-cells = <0>;
1372 <&infracfg CLK_INFRA_SPI4>;
1373 clock-names = "parent-clk", "sel-clk", "spi-clk";
1378 compatible = "mediatek,mt8183-spi";
1379 #address-cells = <1>;
1380 #size-cells = <0>;
1385 <&infracfg CLK_INFRA_SPI5>;
1386 clock-names = "parent-clk", "sel-clk", "spi-clk";
1391 compatible = "mediatek,mt8183-i2c";
1395 clocks = <&infracfg CLK_INFRA_I2C7>,
1396 <&infracfg CLK_INFRA_AP_DMA>;
1397 clock-names = "main", "dma";
1398 clock-div = <1>;
1399 #address-cells = <1>;
1400 #size-cells = <0>;
1405 compatible = "mediatek,mt8183-i2c";
1409 clocks = <&infracfg CLK_INFRA_I2C8>,
1410 <&infracfg CLK_INFRA_AP_DMA>;
1411 clock-names = "main", "dma";
1412 clock-div = <1>;
1413 #address-cells = <1>;
1414 #size-cells = <0>;
1419 compatible = "mediatek,mt8183-mtu3", "mediatek,mtu3";
1422 reg-names = "mac", "ippc";
1426 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
1427 <&infracfg CLK_INFRA_USB>;
1428 clock-names = "sys_ck", "ref_ck";
1429 mediatek,syscon-wakeup = <&pericfg 0x420 101>;
1430 #address-cells = <2>;
1431 #size-cells = <2>;
1436 compatible = "mediatek,mt8183-xhci",
1437 "mediatek,mtk-xhci";
1439 reg-names = "mac";
1441 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
1442 <&infracfg CLK_INFRA_USB>;
1443 clock-names = "sys_ck", "ref_ck";
1448 audiosys: audio-controller@11220000 {
1449 compatible = "mediatek,mt8183-audiosys", "syscon";
1451 #clock-cells = <1>;
1452 afe: mt8183-afe-pcm {
1453 compatible = "mediatek,mt8183-audio";
1456 reset-names = "audiosys";
1457 power-domains =
1474 <&infracfg CLK_INFRA_AUDIO>,
1475 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>,
1501 clock-names = "aud_afe_clk",
1547 compatible = "mediatek,mt8183-mmc";
1552 <&infracfg CLK_INFRA_MSDC0>,
1553 <&infracfg CLK_INFRA_MSDC0_SCK>;
1554 clock-names = "source", "hclk", "source_cg";
1559 compatible = "mediatek,mt8183-mmc";
1564 <&infracfg CLK_INFRA_MSDC1>,
1565 <&infracfg CLK_INFRA_MSDC1_SCK>;
1566 clock-names = "source", "hclk", "source_cg";
1570 mipi_tx0: dsi-phy@11e50000 {
1571 compatible = "mediatek,mt8183-mipi-tx";
1574 #clock-cells = <0>;
1575 #phy-cells = <0>;
1576 clock-output-names = "mipi_tx0_pll";
1577 nvmem-cells = <&mipi_tx_calibration>;
1578 nvmem-cell-names = "calibration-data";
1582 compatible = "mediatek,mt8183-efuse",
1585 #address-cells = <1>;
1586 #size-cells = <1>;
1588 socinfo-data1@4c {
1592 socinfo-data2@60 {
1609 u3phy: t-phy@11f40000 {
1610 compatible = "mediatek,mt8183-tphy",
1611 "mediatek,generic-tphy-v2";
1612 #address-cells = <1>;
1613 #size-cells = <1>;
1617 u2port0: usb-phy@0 {
1620 clock-names = "ref";
1621 #phy-cells = <1>;
1626 u3port0: usb-phy@700 {
1629 clock-names = "ref";
1630 #phy-cells = <1>;
1636 compatible = "mediatek,mt8183-mfgcfg", "syscon";
1638 #clock-cells = <1>;
1639 power-domains = <&spm MT8183_POWER_DOMAIN_MFG_ASYNC>;
1643 compatible = "mediatek,mt8183b-mali", "arm,mali-bifrost";
1649 interrupt-names = "job", "mmu", "gpu";
1653 power-domains =
1657 power-domain-names = "core0", "core1", "core2";
1659 operating-points-v2 = <&gpu_opp_table>;
1663 compatible = "mediatek,mt8183-mmsys", "syscon";
1665 #clock-cells = <1>;
1666 #reset-cells = <1>;
1669 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1672 dma-controller0@14001000 {
1673 compatible = "mediatek,mt8183-mdp3-rdma";
1675 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
1676 mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
1678 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1684 #dma-cells = <1>;
1687 mdp3-rsz0@14003000 {
1688 compatible = "mediatek,mt8183-mdp3-rsz";
1690 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
1691 mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>,
1696 mdp3-rsz1@14004000 {
1697 compatible = "mediatek,mt8183-mdp3-rsz";
1699 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
1700 mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ1_SOF>,
1705 dma-controller@14005000 {
1706 compatible = "mediatek,mt8183-mdp3-wrot";
1708 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
1709 mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,
1711 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1714 #dma-cells = <1>;
1717 mdp3-wdma@14006000 {
1718 compatible = "mediatek,mt8183-mdp3-wdma";
1720 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
1721 mediatek,gce-events = <CMDQ_EVENT_MDP_WDMA0_SOF>,
1723 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1729 compatible = "mediatek,mt8183-disp-ovl";
1732 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1735 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
1739 compatible = "mediatek,mt8183-disp-ovl-2l";
1742 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1745 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
1749 compatible = "mediatek,mt8183-disp-ovl-2l";
1752 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1755 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
1759 compatible = "mediatek,mt8183-disp-rdma";
1762 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1765 mediatek,rdma-fifo-size = <5120>;
1766 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
1770 compatible = "mediatek,mt8183-disp-rdma";
1773 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1776 mediatek,rdma-fifo-size = <2048>;
1777 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1781 compatible = "mediatek,mt8183-disp-color",
1782 "mediatek,mt8173-disp-color";
1785 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1787 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1791 compatible = "mediatek,mt8183-disp-ccorr";
1794 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1796 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1800 compatible = "mediatek,mt8183-disp-aal";
1803 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1805 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
1809 compatible = "mediatek,mt8183-disp-gamma";
1812 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1814 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1818 compatible = "mediatek,mt8183-disp-dither";
1821 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1823 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
1827 compatible = "mediatek,mt8183-dsi";
1830 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1834 clock-names = "engine", "digital", "hs";
1837 phy-names = "dphy";
1842 compatible = "mediatek,mt8183-dpi";
1845 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1849 clock-names = "pixel", "engine", "pll";
1858 compatible = "mediatek,mt8183-disp-mutex";
1861 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1862 mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
1864 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
1868 compatible = "mediatek,mt8183-smi-larb";
1873 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1874 clock-names = "apb", "smi";
1878 compatible = "mediatek,mt8183-smi-common";
1884 clock-names = "apb", "smi", "gals0", "gals1";
1885 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1888 mdp3-ccorr@1401c000 {
1889 compatible = "mediatek,mt8183-mdp3-ccorr";
1891 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
1892 mediatek,gce-events = <CMDQ_EVENT_MDP_CCORR_SOF>,
1898 compatible = "mediatek,mt8183-imgsys", "syscon";
1900 #clock-cells = <1>;
1904 compatible = "mediatek,mt8183-smi-larb";
1909 clock-names = "apb", "smi", "gals";
1910 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>;
1914 compatible = "mediatek,mt8183-smi-larb";
1919 clock-names = "apb", "smi", "gals";
1920 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>;
1924 compatible = "mediatek,mt8183-vdecsys", "syscon";
1926 #clock-cells = <1>;
1929 vcodec_dec: video-codec@16020000 {
1930 compatible = "mediatek,mt8183-vcodec-dec";
1942 reg-names = "misc", "ld", "top", "cm", "ad", "av", "pp",
1954 power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>;
1956 clock-names = "vdec";
1960 compatible = "mediatek,mt8183-smi-larb";
1964 clock-names = "apb", "smi";
1965 power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>;
1969 compatible = "mediatek,mt8183-vencsys", "syscon";
1971 #clock-cells = <1>;
1975 compatible = "mediatek,mt8183-smi-larb";
1980 clock-names = "apb", "smi";
1981 power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
1985 compatible = "mediatek,mt8183-vcodec-enc";
1996 power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
1998 clock-names = "venc_sel";
2001 venc_jpg: jpeg-encoder@17030000 {
2002 compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc";
2007 power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
2009 clock-names = "jpgenc";
2013 compatible = "mediatek,mt8183-ipu_conn", "syscon";
2015 #clock-cells = <1>;
2019 compatible = "mediatek,mt8183-ipu_adl", "syscon";
2021 #clock-cells = <1>;
2025 compatible = "mediatek,mt8183-ipu_core0", "syscon";
2027 #clock-cells = <1>;
2031 compatible = "mediatek,mt8183-ipu_core1", "syscon";
2033 #clock-cells = <1>;
2037 compatible = "mediatek,mt8183-camsys", "syscon";
2039 #clock-cells = <1>;
2043 compatible = "mediatek,mt8183-smi-larb";
2048 clock-names = "apb", "smi", "gals";
2049 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
2053 compatible = "mediatek,mt8183-smi-larb";
2058 clock-names = "apb", "smi", "gals";
2059 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
2063 thermal_zones: thermal-zones {
2064 cpu_thermal: cpu-thermal {
2065 polling-delay-passive = <100>;
2066 polling-delay = <500>;
2067 thermal-sensors = <&thermal 0>;
2068 sustainable-power = <5000>;
2071 threshold: trip-point0 {
2077 target: trip-point1 {
2083 cpu_crit: cpu-crit {
2090 cooling-maps {
2093 cooling-device = <&cpu0
2109 cooling-device = <&cpu4
2126 tzts1: soc-thermal {
2127 polling-delay = <1000>;
2128 polling-delay-passive = <250>;
2129 thermal-sensors = <&thermal 1>;
2130 sustainable-power = <5000>;
2132 soc_alert: trip-alert {
2138 soc_crit: trip-crit {
2146 tzts2: gpu-thermal {
2147 polling-delay = <1000>;
2148 polling-delay-passive = <250>;
2149 thermal-sensors = <&thermal 2>;
2150 sustainable-power = <5000>;
2153 gpu_alert: trip-alert {
2159 gpu_crit: trip-crit {
2167 tzts3: md1-thermal {
2168 polling-delay = <1000>;
2169 polling-delay-passive = <250>;
2170 thermal-sensors = <&thermal 3>;
2171 sustainable-power = <5000>;
2174 md1_alert: trip-alert {
2180 md1_crit: trip-crit {
2188 tzts4: cpu-little-thermal {
2189 polling-delay = <1000>;
2190 polling-delay-passive = <250>;
2191 thermal-sensors = <&thermal 4>;
2192 sustainable-power = <5000>;
2195 cpul_alert: trip-alert {
2201 cpul_crit: trip-crit {
2209 tzts5: cpu-big-thermal {
2210 polling-delay = <1000>;
2211 polling-delay-passive = <250>;
2212 thermal-sensors = <&thermal 5>;
2213 sustainable-power = <5000>;
2216 cpub_alert: trip-alert {
2222 cpub_crit: trip-crit {
2230 tztsABB: tsabb-thermal {
2231 polling-delay = <1000>;
2232 polling-delay-passive = <250>;
2233 thermal-sensors = <&thermal 6>;
2234 sustainable-power = <5000>;
2237 tsabb_alert: trip-alert {
2243 tsabb_crit: trip-crit {