Lines Matching +full:psci +full:- +full:suspend +full:- +full:param
1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/mt8173-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/memory/mt8173-larb-port.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/power/mt8173-power.h>
13 #include <dt-bindings/reset/mt8173-resets.h>
14 #include <dt-bindings/gce/mt8173-gce.h>
15 #include <dt-bindings/thermal/thermal.h>
16 #include "mt8173-pinfunc.h"
20 interrupt-parent = <&sysirq>;
21 #address-cells = <2>;
22 #size-cells = <2>;
39 mdp-rdma0 = &mdp_rdma0;
40 mdp-rdma1 = &mdp_rdma1;
41 mdp-rsz0 = &mdp_rsz0;
42 mdp-rsz1 = &mdp_rsz1;
43 mdp-rsz2 = &mdp_rsz2;
44 mdp-wdma0 = &mdp_wdma0;
45 mdp-wrot0 = &mdp_wrot0;
46 mdp-wrot1 = &mdp_wrot1;
53 cluster0_opp: opp-table-0 {
54 compatible = "operating-points-v2";
55 opp-shared;
56 opp-507000000 {
57 opp-hz = /bits/ 64 <507000000>;
58 opp-microvolt = <859000>;
60 opp-702000000 {
61 opp-hz = /bits/ 64 <702000000>;
62 opp-microvolt = <908000>;
64 opp-1001000000 {
65 opp-hz = /bits/ 64 <1001000000>;
66 opp-microvolt = <983000>;
68 opp-1105000000 {
69 opp-hz = /bits/ 64 <1105000000>;
70 opp-microvolt = <1009000>;
72 opp-1209000000 {
73 opp-hz = /bits/ 64 <1209000000>;
74 opp-microvolt = <1034000>;
76 opp-1300000000 {
77 opp-hz = /bits/ 64 <1300000000>;
78 opp-microvolt = <1057000>;
80 opp-1508000000 {
81 opp-hz = /bits/ 64 <1508000000>;
82 opp-microvolt = <1109000>;
84 opp-1703000000 {
85 opp-hz = /bits/ 64 <1703000000>;
86 opp-microvolt = <1125000>;
90 cluster1_opp: opp-table-1 {
91 compatible = "operating-points-v2";
92 opp-shared;
93 opp-507000000 {
94 opp-hz = /bits/ 64 <507000000>;
95 opp-microvolt = <828000>;
97 opp-702000000 {
98 opp-hz = /bits/ 64 <702000000>;
99 opp-microvolt = <867000>;
101 opp-1001000000 {
102 opp-hz = /bits/ 64 <1001000000>;
103 opp-microvolt = <927000>;
105 opp-1209000000 {
106 opp-hz = /bits/ 64 <1209000000>;
107 opp-microvolt = <968000>;
109 opp-1404000000 {
110 opp-hz = /bits/ 64 <1404000000>;
111 opp-microvolt = <1007000>;
113 opp-1612000000 {
114 opp-hz = /bits/ 64 <1612000000>;
115 opp-microvolt = <1049000>;
117 opp-1807000000 {
118 opp-hz = /bits/ 64 <1807000000>;
119 opp-microvolt = <1089000>;
121 opp-2106000000 {
122 opp-hz = /bits/ 64 <2106000000>;
123 opp-microvolt = <1125000>;
128 #address-cells = <1>;
129 #size-cells = <0>;
131 cpu-map {
153 compatible = "arm,cortex-a53";
155 enable-method = "psci";
156 cpu-idle-states = <&CPU_SLEEP_0>;
157 #cooling-cells = <2>;
158 dynamic-power-coefficient = <263>;
161 clock-names = "cpu", "intermediate";
162 operating-points-v2 = <&cluster0_opp>;
163 capacity-dmips-mhz = <740>;
168 compatible = "arm,cortex-a53";
170 enable-method = "psci";
171 cpu-idle-states = <&CPU_SLEEP_0>;
172 #cooling-cells = <2>;
173 dynamic-power-coefficient = <263>;
176 clock-names = "cpu", "intermediate";
177 operating-points-v2 = <&cluster0_opp>;
178 capacity-dmips-mhz = <740>;
183 compatible = "arm,cortex-a72";
185 enable-method = "psci";
186 cpu-idle-states = <&CPU_SLEEP_0>;
187 #cooling-cells = <2>;
188 dynamic-power-coefficient = <530>;
191 clock-names = "cpu", "intermediate";
192 operating-points-v2 = <&cluster1_opp>;
193 capacity-dmips-mhz = <1024>;
198 compatible = "arm,cortex-a72";
200 enable-method = "psci";
201 cpu-idle-states = <&CPU_SLEEP_0>;
202 #cooling-cells = <2>;
203 dynamic-power-coefficient = <530>;
206 clock-names = "cpu", "intermediate";
207 operating-points-v2 = <&cluster1_opp>;
208 capacity-dmips-mhz = <1024>;
211 idle-states {
212 entry-method = "psci";
214 CPU_SLEEP_0: cpu-sleep-0 {
215 compatible = "arm,idle-state";
216 local-timer-stop;
217 entry-latency-us = <639>;
218 exit-latency-us = <680>;
219 min-residency-us = <1088>;
220 arm,psci-suspend-param = <0x0010000>;
225 pmu-a53 {
226 compatible = "arm,cortex-a53-pmu";
229 interrupt-affinity = <&cpu0>, <&cpu1>;
232 pmu-a72 {
233 compatible = "arm,cortex-a72-pmu";
236 interrupt-affinity = <&cpu2>, <&cpu3>;
239 psci {
240 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
248 compatible = "fixed-clock";
249 #clock-cells = <0>;
250 clock-frequency = <26000000>;
251 clock-output-names = "clk26m";
255 compatible = "fixed-clock";
256 #clock-cells = <0>;
257 clock-frequency = <32000>;
258 clock-output-names = "clk32k";
262 compatible = "fixed-clock";
263 #clock-cells = <0>;
264 clock-frequency = <0>;
265 clock-output-names = "cpum_ck";
268 thermal-zones {
269 cpu_thermal: cpu-thermal {
270 polling-delay-passive = <1000>; /* milliseconds */
271 polling-delay = <1000>; /* milliseconds */
273 thermal-sensors = <&thermal>;
274 sustainable-power = <1500>; /* milliwatts */
277 threshold: trip-point0 {
283 target: trip-point1 {
289 cpu_crit: cpu-crit0 {
296 cooling-maps {
299 cooling-device = <&cpu0 THERMAL_NO_LIMIT
307 cooling-device = <&cpu2 THERMAL_NO_LIMIT
317 reserved-memory {
318 #address-cells = <2>;
319 #size-cells = <2>;
322 afe_dma_mem: audio-dma-pool {
323 compatible = "shared-dma-pool";
326 no-map;
329 vpu_dma_reserved: vpu-dma-mem@b7000000 {
330 compatible = "shared-dma-pool";
333 no-map;
338 compatible = "arm,armv8-timer";
339 interrupt-parent = <&gic>;
348 arm,no-tick-in-suspend;
352 #address-cells = <2>;
353 #size-cells = <2>;
354 compatible = "simple-bus";
357 topckgen: clock-controller@10000000 {
358 compatible = "mediatek,mt8173-topckgen";
360 #clock-cells = <1>;
363 infracfg: clock-controller@10001000 {
364 compatible = "mediatek,mt8173-infracfg", "syscon";
366 #clock-cells = <1>;
367 #reset-cells = <1>;
370 pericfg: clock-controller@10003000 {
371 compatible = "mediatek,mt8173-pericfg", "syscon";
373 #clock-cells = <1>;
374 #reset-cells = <1>;
378 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
383 compatible = "mediatek,mt8173-pinctrl";
385 mediatek,pctl-regmap = <&syscfg_pctl_a>;
386 gpio-controller;
387 #gpio-cells = <2>;
388 interrupt-controller;
389 #interrupt-cells = <2>;
399 input-enable;
400 bias-pull-down;
408 bias-disable;
416 bias-disable;
424 bias-disable;
432 bias-disable;
440 bias-disable;
448 bias-disable;
454 compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd";
458 spm: power-controller {
459 compatible = "mediatek,mt8173-power-controller";
460 #address-cells = <1>;
461 #size-cells = <0>;
462 #power-domain-cells = <1>;
465 power-domain@MT8173_POWER_DOMAIN_VDEC {
468 clock-names = "mm";
469 #power-domain-cells = <0>;
471 power-domain@MT8173_POWER_DOMAIN_VENC {
475 clock-names = "mm", "venc";
476 #power-domain-cells = <0>;
478 power-domain@MT8173_POWER_DOMAIN_ISP {
481 clock-names = "mm";
482 #power-domain-cells = <0>;
484 power-domain@MT8173_POWER_DOMAIN_MM {
487 clock-names = "mm";
488 #power-domain-cells = <0>;
491 power-domain@MT8173_POWER_DOMAIN_VENC_LT {
495 clock-names = "mm", "venclt";
496 #power-domain-cells = <0>;
498 power-domain@MT8173_POWER_DOMAIN_AUDIO {
500 #power-domain-cells = <0>;
502 power-domain@MT8173_POWER_DOMAIN_USB {
504 #power-domain-cells = <0>;
506 mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
509 clock-names = "mfg";
510 #address-cells = <1>;
511 #size-cells = <0>;
512 #power-domain-cells = <1>;
514 power-domain@MT8173_POWER_DOMAIN_MFG_2D {
516 #address-cells = <1>;
517 #size-cells = <0>;
518 #power-domain-cells = <1>;
520 power-domain@MT8173_POWER_DOMAIN_MFG {
522 #power-domain-cells = <0>;
531 compatible = "mediatek,mt8173-wdt",
532 "mediatek,mt6589-wdt";
537 compatible = "mediatek,mt8173-timer",
538 "mediatek,mt6577-timer";
546 compatible = "mediatek,mt8173-pwrap";
548 reg-names = "pwrap";
551 reset-names = "pwrap";
553 clock-names = "spi", "wrap";
557 compatible = "mediatek,mt8173-cec";
565 compatible = "mediatek,mt8173-vpu";
568 reg-names = "tcm", "cfg_reg";
571 clock-names = "main";
572 memory-region = <&vpu_dma_reserved>;
575 sysirq: interrupt-controller@10200620 {
576 compatible = "mediatek,mt8173-sysirq",
577 "mediatek,mt6577-sysirq";
578 interrupt-controller;
579 #interrupt-cells = <3>;
580 interrupt-parent = <&gic>;
585 compatible = "mediatek,mt8173-m4u";
589 clock-names = "bclk";
593 #iommu-cells = <1>;
597 compatible = "mediatek,mt8173-efuse";
599 #address-cells = <1>;
600 #size-cells = <1>;
602 socinfo-data1@40 {
606 socinfo-data2@44 {
615 apmixedsys: clock-controller@10209000 {
616 compatible = "mediatek,mt8173-apmixedsys";
618 #clock-cells = <1>;
621 hdmi_phy: hdmi-phy@10209100 {
622 compatible = "mediatek,mt8173-hdmi-phy";
625 clock-names = "pll_ref";
626 clock-output-names = "hdmitx_dig_cts";
629 #clock-cells = <0>;
630 #phy-cells = <0>;
635 compatible = "mediatek,mt8173-gce";
639 clock-names = "gce";
640 #mbox-cells = <2>;
643 mipi_tx0: dsi-phy@10215000 {
644 compatible = "mediatek,mt8173-mipi-tx";
647 clock-output-names = "mipi_tx0_pll";
648 #clock-cells = <0>;
649 #phy-cells = <0>;
653 mipi_tx1: dsi-phy@10216000 {
654 compatible = "mediatek,mt8173-mipi-tx";
657 clock-output-names = "mipi_tx1_pll";
658 #clock-cells = <0>;
659 #phy-cells = <0>;
663 gic: interrupt-controller@10221000 {
664 compatible = "arm,gic-400";
665 #interrupt-cells = <3>;
666 interrupt-parent = <&gic>;
667 interrupt-controller;
677 compatible = "mediatek,mt8173-auxadc";
680 clock-names = "main";
681 #io-channel-cells = <1>;
685 compatible = "mediatek,mt8173-uart",
686 "mediatek,mt6577-uart";
690 clock-names = "baud", "bus";
695 compatible = "mediatek,mt8173-uart",
696 "mediatek,mt6577-uart";
700 clock-names = "baud", "bus";
705 compatible = "mediatek,mt8173-uart",
706 "mediatek,mt6577-uart";
710 clock-names = "baud", "bus";
715 compatible = "mediatek,mt8173-uart",
716 "mediatek,mt6577-uart";
720 clock-names = "baud", "bus";
725 compatible = "mediatek,mt8173-i2c";
729 clock-div = <16>;
732 clock-names = "main", "dma";
733 pinctrl-names = "default";
734 pinctrl-0 = <&i2c0_pins_a>;
735 #address-cells = <1>;
736 #size-cells = <0>;
741 compatible = "mediatek,mt8173-i2c";
745 clock-div = <16>;
748 clock-names = "main", "dma";
749 pinctrl-names = "default";
750 pinctrl-0 = <&i2c1_pins_a>;
751 #address-cells = <1>;
752 #size-cells = <0>;
757 compatible = "mediatek,mt8173-i2c";
761 clock-div = <16>;
764 clock-names = "main", "dma";
765 pinctrl-names = "default";
766 pinctrl-0 = <&i2c2_pins_a>;
767 #address-cells = <1>;
768 #size-cells = <0>;
773 compatible = "mediatek,mt8173-spi";
774 #address-cells = <1>;
775 #size-cells = <0>;
781 clock-names = "parent-clk", "sel-clk", "spi-clk";
786 #thermal-sensor-cells = <0>;
787 compatible = "mediatek,mt8173-thermal";
791 clock-names = "therm", "auxadc";
795 nvmem-cells = <&thermal_calibration>;
796 nvmem-cell-names = "calibration-data";
800 compatible = "mediatek,mt8173-nor";
802 assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>;
803 assigned-clock-parents = <&clk26m>;
807 clock-names = "spi", "sf", "axi";
808 #address-cells = <1>;
809 #size-cells = <0>;
814 compatible = "mediatek,mt8173-i2c";
818 clock-div = <16>;
821 clock-names = "main", "dma";
822 pinctrl-names = "default";
823 pinctrl-0 = <&i2c3_pins_a>;
824 #address-cells = <1>;
825 #size-cells = <0>;
830 compatible = "mediatek,mt8173-i2c";
834 clock-div = <16>;
837 clock-names = "main", "dma";
838 pinctrl-names = "default";
839 pinctrl-0 = <&i2c4_pins_a>;
840 #address-cells = <1>;
841 #size-cells = <0>;
846 compatible = "mediatek,mt8173-hdmi-ddc";
850 clock-names = "ddc-i2c";
854 compatible = "mediatek,mt8173-i2c";
858 clock-div = <16>;
861 clock-names = "main", "dma";
862 pinctrl-names = "default";
863 pinctrl-0 = <&i2c6_pins_a>;
864 #address-cells = <1>;
865 #size-cells = <0>;
869 afe: audio-controller@11220000 {
870 compatible = "mediatek,mt8173-afe-pcm";
873 power-domains = <&spm MT8173_POWER_DOMAIN_AUDIO>;
884 clock-names = "infra_sys_audio_clk",
894 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
896 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
898 memory-region = <&afe_dma_mem>;
902 compatible = "mediatek,mt8173-mmc";
907 clock-names = "source", "hclk";
912 compatible = "mediatek,mt8173-mmc";
917 clock-names = "source", "hclk";
922 compatible = "mediatek,mt8173-mmc";
927 clock-names = "source", "hclk";
932 compatible = "mediatek,mt8173-mmc";
937 clock-names = "source", "hclk";
942 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3";
945 reg-names = "mac", "ippc";
950 power-domains = <&spm MT8173_POWER_DOMAIN_USB>;
952 clock-names = "sys_ck", "ref_ck";
953 mediatek,syscon-wakeup = <&pericfg 0x400 1>;
954 #address-cells = <2>;
955 #size-cells = <2>;
960 compatible = "mediatek,mt8173-xhci",
961 "mediatek,mtk-xhci";
963 reg-names = "mac";
965 power-domains = <&spm MT8173_POWER_DOMAIN_USB>;
967 clock-names = "sys_ck", "ref_ck";
972 u3phy: t-phy@11290000 {
973 compatible = "mediatek,mt8173-u3phy";
975 #address-cells = <2>;
976 #size-cells = <2>;
980 u2port0: usb-phy@11290800 {
983 clock-names = "ref";
984 #phy-cells = <1>;
988 u3port0: usb-phy@11290900 {
991 clock-names = "ref";
992 #phy-cells = <1>;
996 u2port1: usb-phy@11291000 {
999 clock-names = "ref";
1000 #phy-cells = <1>;
1006 compatible = "mediatek,mt8173-mmsys", "syscon";
1008 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1009 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
1010 assigned-clock-rates = <400000000>;
1011 #clock-cells = <1>;
1012 #reset-cells = <1>;
1015 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1019 compatible = "mediatek,mt8173-mdp-rdma",
1020 "mediatek,mt8173-mdp";
1024 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1030 compatible = "mediatek,mt8173-mdp-rdma";
1034 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1039 compatible = "mediatek,mt8173-mdp-rsz";
1042 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1046 compatible = "mediatek,mt8173-mdp-rsz";
1049 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1053 compatible = "mediatek,mt8173-mdp-rsz";
1056 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1060 compatible = "mediatek,mt8173-mdp-wdma";
1063 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1068 compatible = "mediatek,mt8173-mdp-wrot";
1071 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1076 compatible = "mediatek,mt8173-mdp-wrot";
1079 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1084 compatible = "mediatek,mt8173-disp-ovl";
1087 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1090 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1094 compatible = "mediatek,mt8173-disp-ovl";
1097 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1100 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1104 compatible = "mediatek,mt8173-disp-rdma";
1107 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1110 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1114 compatible = "mediatek,mt8173-disp-rdma";
1117 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1120 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1124 compatible = "mediatek,mt8173-disp-rdma";
1127 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1130 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
1134 compatible = "mediatek,mt8173-disp-wdma";
1137 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1140 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1144 compatible = "mediatek,mt8173-disp-wdma";
1147 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1150 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
1154 compatible = "mediatek,mt8173-disp-color";
1157 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1159 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
1163 compatible = "mediatek,mt8173-disp-color";
1166 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1168 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
1172 compatible = "mediatek,mt8173-disp-aal";
1175 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1177 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
1181 compatible = "mediatek,mt8173-disp-gamma";
1184 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1186 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
1190 compatible = "mediatek,mt8173-disp-merge";
1192 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1197 compatible = "mediatek,mt8173-disp-split";
1199 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1204 compatible = "mediatek,mt8173-disp-split";
1206 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1211 compatible = "mediatek,mt8173-disp-ufoe";
1214 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1216 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>;
1220 compatible = "mediatek,mt8173-dsi";
1223 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1227 clock-names = "engine", "digital", "hs";
1230 phy-names = "dphy";
1235 compatible = "mediatek,mt8173-dsi";
1238 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1242 clock-names = "engine", "digital", "hs";
1244 phy-names = "dphy";
1249 compatible = "mediatek,mt8173-dpi";
1252 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1256 clock-names = "pixel", "engine", "pll";
1261 remote-endpoint = <&hdmi0_in>;
1267 compatible = "mediatek,mt8173-disp-pwm";
1269 #pwm-cells = <2>;
1272 clock-names = "main", "mm";
1277 compatible = "mediatek,mt8173-disp-pwm";
1279 #pwm-cells = <2>;
1282 clock-names = "main", "mm";
1287 compatible = "mediatek,mt8173-disp-mutex";
1290 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1292 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>;
1293 mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
1298 compatible = "mediatek,mt8173-smi-larb";
1301 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1304 clock-names = "apb", "smi";
1308 compatible = "mediatek,mt8173-smi-common";
1310 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1313 clock-names = "apb", "smi";
1317 compatible = "mediatek,mt8173-disp-od";
1320 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>;
1324 compatible = "mediatek,mt8173-hdmi";
1331 clock-names = "pixel", "pll", "bclk", "spdif";
1332 pinctrl-names = "default";
1333 pinctrl-0 = <&hdmi_pin>;
1335 phy-names = "hdmi";
1336 mediatek,syscon-hdmi = <&mmsys 0x900>;
1337 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
1338 assigned-clock-parents = <&hdmi_phy>;
1342 #address-cells = <1>;
1343 #size-cells = <0>;
1349 remote-endpoint = <&dpi0_out>;
1356 compatible = "mediatek,mt8173-smi-larb";
1359 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1362 clock-names = "apb", "smi";
1365 imgsys: clock-controller@15000000 {
1366 compatible = "mediatek,mt8173-imgsys", "syscon";
1368 #clock-cells = <1>;
1372 compatible = "mediatek,mt8173-smi-larb";
1375 power-domains = <&spm MT8173_POWER_DOMAIN_ISP>;
1378 clock-names = "apb", "smi";
1381 vdecsys: clock-controller@16000000 {
1382 compatible = "mediatek,mt8173-vdecsys", "syscon";
1384 #clock-cells = <1>;
1388 compatible = "mediatek,mt8173-vcodec-dec";
1400 reg-names = "misc", "ld", "top", "cm", "ad", "av", "pp",
1413 power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>;
1422 clock-names = "vcodecpll",
1430 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
1435 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
1438 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
1442 compatible = "mediatek,mt8173-smi-larb";
1445 power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>;
1448 clock-names = "apb", "smi";
1451 vencsys: clock-controller@18000000 {
1452 compatible = "mediatek,mt8173-vencsys", "syscon";
1454 #clock-cells = <1>;
1458 compatible = "mediatek,mt8173-smi-larb";
1461 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
1464 clock-names = "apb", "smi";
1468 compatible = "mediatek,mt8173-vcodec-enc";
1484 clock-names = "venc_sel";
1485 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
1486 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
1487 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
1491 compatible = "mediatek,mt8173-jpgdec";
1496 clock-names = "jpgdec-smi",
1498 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
1503 vencltsys: clock-controller@19000000 {
1504 compatible = "mediatek,mt8173-vencltsys", "syscon";
1506 #clock-cells = <1>;
1510 compatible = "mediatek,mt8173-smi-larb";
1513 power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>;
1516 clock-names = "apb", "smi";
1520 compatible = "mediatek,mt8173-vcodec-enc-vp8";
1534 clock-names = "venc_lt_sel";
1535 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
1536 assigned-clock-parents =
1538 power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>;