Lines Matching +full:mt8173 +full:- +full:hdmi +full:- +full:ddc
1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/mt8173-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/memory/mt8173-larb-port.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/power/mt8173-power.h>
13 #include <dt-bindings/reset/mt8173-resets.h>
14 #include <dt-bindings/gce/mt8173-gce.h>
15 #include <dt-bindings/thermal/thermal.h>
16 #include "mt8173-pinfunc.h"
19 compatible = "mediatek,mt8173";
20 interrupt-parent = <&sysirq>;
21 #address-cells = <2>;
22 #size-cells = <2>;
39 mdp-rdma0 = &mdp_rdma0;
40 mdp-rdma1 = &mdp_rdma1;
41 mdp-rsz0 = &mdp_rsz0;
42 mdp-rsz1 = &mdp_rsz1;
43 mdp-rsz2 = &mdp_rsz2;
44 mdp-wdma0 = &mdp_wdma0;
45 mdp-wrot0 = &mdp_wrot0;
46 mdp-wrot1 = &mdp_wrot1;
53 cluster0_opp: opp-table-0 {
54 compatible = "operating-points-v2";
55 opp-shared;
56 opp-507000000 {
57 opp-hz = /bits/ 64 <507000000>;
58 opp-microvolt = <859000>;
60 opp-702000000 {
61 opp-hz = /bits/ 64 <702000000>;
62 opp-microvolt = <908000>;
64 opp-1001000000 {
65 opp-hz = /bits/ 64 <1001000000>;
66 opp-microvolt = <983000>;
68 opp-1105000000 {
69 opp-hz = /bits/ 64 <1105000000>;
70 opp-microvolt = <1009000>;
72 opp-1209000000 {
73 opp-hz = /bits/ 64 <1209000000>;
74 opp-microvolt = <1034000>;
76 opp-1300000000 {
77 opp-hz = /bits/ 64 <1300000000>;
78 opp-microvolt = <1057000>;
80 opp-1508000000 {
81 opp-hz = /bits/ 64 <1508000000>;
82 opp-microvolt = <1109000>;
84 opp-1703000000 {
85 opp-hz = /bits/ 64 <1703000000>;
86 opp-microvolt = <1125000>;
90 cluster1_opp: opp-table-1 {
91 compatible = "operating-points-v2";
92 opp-shared;
93 opp-507000000 {
94 opp-hz = /bits/ 64 <507000000>;
95 opp-microvolt = <828000>;
97 opp-702000000 {
98 opp-hz = /bits/ 64 <702000000>;
99 opp-microvolt = <867000>;
101 opp-1001000000 {
102 opp-hz = /bits/ 64 <1001000000>;
103 opp-microvolt = <927000>;
105 opp-1209000000 {
106 opp-hz = /bits/ 64 <1209000000>;
107 opp-microvolt = <968000>;
109 opp-1404000000 {
110 opp-hz = /bits/ 64 <1404000000>;
111 opp-microvolt = <1007000>;
113 opp-1612000000 {
114 opp-hz = /bits/ 64 <1612000000>;
115 opp-microvolt = <1049000>;
117 opp-1807000000 {
118 opp-hz = /bits/ 64 <1807000000>;
119 opp-microvolt = <1089000>;
121 opp-2106000000 {
122 opp-hz = /bits/ 64 <2106000000>;
123 opp-microvolt = <1125000>;
128 #address-cells = <1>;
129 #size-cells = <0>;
131 cpu-map {
153 compatible = "arm,cortex-a53";
155 enable-method = "psci";
156 cpu-idle-states = <&CPU_SLEEP_0>;
157 #cooling-cells = <2>;
158 dynamic-power-coefficient = <263>;
161 clock-names = "cpu", "intermediate";
162 operating-points-v2 = <&cluster0_opp>;
163 capacity-dmips-mhz = <740>;
168 compatible = "arm,cortex-a53";
170 enable-method = "psci";
171 cpu-idle-states = <&CPU_SLEEP_0>;
172 #cooling-cells = <2>;
173 dynamic-power-coefficient = <263>;
176 clock-names = "cpu", "intermediate";
177 operating-points-v2 = <&cluster0_opp>;
178 capacity-dmips-mhz = <740>;
183 compatible = "arm,cortex-a72";
185 enable-method = "psci";
186 cpu-idle-states = <&CPU_SLEEP_0>;
187 #cooling-cells = <2>;
188 dynamic-power-coefficient = <530>;
191 clock-names = "cpu", "intermediate";
192 operating-points-v2 = <&cluster1_opp>;
193 capacity-dmips-mhz = <1024>;
198 compatible = "arm,cortex-a72";
200 enable-method = "psci";
201 cpu-idle-states = <&CPU_SLEEP_0>;
202 #cooling-cells = <2>;
203 dynamic-power-coefficient = <530>;
206 clock-names = "cpu", "intermediate";
207 operating-points-v2 = <&cluster1_opp>;
208 capacity-dmips-mhz = <1024>;
211 idle-states {
212 entry-method = "psci";
214 CPU_SLEEP_0: cpu-sleep-0 {
215 compatible = "arm,idle-state";
216 local-timer-stop;
217 entry-latency-us = <639>;
218 exit-latency-us = <680>;
219 min-residency-us = <1088>;
220 arm,psci-suspend-param = <0x0010000>;
225 pmu-a53 {
226 compatible = "arm,cortex-a53-pmu";
229 interrupt-affinity = <&cpu0>, <&cpu1>;
232 pmu-a72 {
233 compatible = "arm,cortex-a72-pmu";
236 interrupt-affinity = <&cpu2>, <&cpu3>;
240 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
248 compatible = "fixed-clock";
249 #clock-cells = <0>;
250 clock-frequency = <26000000>;
251 clock-output-names = "clk26m";
255 compatible = "fixed-clock";
256 #clock-cells = <0>;
257 clock-frequency = <32000>;
258 clock-output-names = "clk32k";
262 compatible = "fixed-clock";
263 #clock-cells = <0>;
264 clock-frequency = <0>;
265 clock-output-names = "cpum_ck";
268 thermal-zones {
269 cpu_thermal: cpu-thermal {
270 polling-delay-passive = <1000>; /* milliseconds */
271 polling-delay = <1000>; /* milliseconds */
273 thermal-sensors = <&thermal>;
274 sustainable-power = <1500>; /* milliwatts */
277 threshold: trip-point0 {
283 target: trip-point1 {
289 cpu_crit: cpu-crit0 {
296 cooling-maps {
299 cooling-device = <&cpu0 THERMAL_NO_LIMIT
307 cooling-device = <&cpu2 THERMAL_NO_LIMIT
317 reserved-memory {
318 #address-cells = <2>;
319 #size-cells = <2>;
321 vpu_dma_reserved: vpu-dma-mem@b7000000 {
322 compatible = "shared-dma-pool";
325 no-map;
330 compatible = "arm,armv8-timer";
331 interrupt-parent = <&gic>;
340 arm,no-tick-in-suspend;
344 #address-cells = <2>;
345 #size-cells = <2>;
346 compatible = "simple-bus";
349 topckgen: clock-controller@10000000 {
350 compatible = "mediatek,mt8173-topckgen";
352 #clock-cells = <1>;
355 infracfg: power-controller@10001000 {
356 compatible = "mediatek,mt8173-infracfg", "syscon";
358 #clock-cells = <1>;
359 #reset-cells = <1>;
362 pericfg: power-controller@10003000 {
363 compatible = "mediatek,mt8173-pericfg", "syscon";
365 #clock-cells = <1>;
366 #reset-cells = <1>;
370 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
375 compatible = "mediatek,mt8173-pinctrl";
377 mediatek,pctl-regmap = <&syscfg_pctl_a>;
378 gpio-controller;
379 #gpio-cells = <2>;
380 interrupt-controller;
381 #interrupt-cells = <2>;
388 /*hdmi htplg pin*/
391 input-enable;
392 bias-pull-down;
400 bias-disable;
408 bias-disable;
416 bias-disable;
424 bias-disable;
432 bias-disable;
440 bias-disable;
446 compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd";
450 spm: power-controller {
451 compatible = "mediatek,mt8173-power-controller";
452 #address-cells = <1>;
453 #size-cells = <0>;
454 #power-domain-cells = <1>;
457 power-domain@MT8173_POWER_DOMAIN_VDEC {
460 clock-names = "mm";
461 #power-domain-cells = <0>;
463 power-domain@MT8173_POWER_DOMAIN_VENC {
467 clock-names = "mm", "venc";
468 #power-domain-cells = <0>;
470 power-domain@MT8173_POWER_DOMAIN_ISP {
473 clock-names = "mm";
474 #power-domain-cells = <0>;
476 power-domain@MT8173_POWER_DOMAIN_MM {
479 clock-names = "mm";
480 #power-domain-cells = <0>;
483 power-domain@MT8173_POWER_DOMAIN_VENC_LT {
487 clock-names = "mm", "venclt";
488 #power-domain-cells = <0>;
490 power-domain@MT8173_POWER_DOMAIN_AUDIO {
492 #power-domain-cells = <0>;
494 power-domain@MT8173_POWER_DOMAIN_USB {
496 #power-domain-cells = <0>;
498 mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
501 clock-names = "mfg";
502 #address-cells = <1>;
503 #size-cells = <0>;
504 #power-domain-cells = <1>;
506 power-domain@MT8173_POWER_DOMAIN_MFG_2D {
508 #address-cells = <1>;
509 #size-cells = <0>;
510 #power-domain-cells = <1>;
512 power-domain@MT8173_POWER_DOMAIN_MFG {
514 #power-domain-cells = <0>;
523 compatible = "mediatek,mt8173-wdt",
524 "mediatek,mt6589-wdt";
529 compatible = "mediatek,mt8173-timer",
530 "mediatek,mt6577-timer";
538 compatible = "mediatek,mt8173-pwrap";
540 reg-names = "pwrap";
543 reset-names = "pwrap";
545 clock-names = "spi", "wrap";
549 compatible = "mediatek,mt8173-cec";
557 compatible = "mediatek,mt8173-vpu";
560 reg-names = "tcm", "cfg_reg";
563 clock-names = "main";
564 memory-region = <&vpu_dma_reserved>;
567 sysirq: intpol-controller@10200620 {
568 compatible = "mediatek,mt8173-sysirq",
569 "mediatek,mt6577-sysirq";
570 interrupt-controller;
571 #interrupt-cells = <3>;
572 interrupt-parent = <&gic>;
577 compatible = "mediatek,mt8173-m4u";
581 clock-names = "bclk";
585 #iommu-cells = <1>;
589 compatible = "mediatek,mt8173-efuse";
591 #address-cells = <1>;
592 #size-cells = <1>;
594 socinfo-data1@40 {
598 socinfo-data2@44 {
607 apmixedsys: clock-controller@10209000 {
608 compatible = "mediatek,mt8173-apmixedsys";
610 #clock-cells = <1>;
613 hdmi_phy: hdmi-phy@10209100 {
614 compatible = "mediatek,mt8173-hdmi-phy";
617 clock-names = "pll_ref";
618 clock-output-names = "hdmitx_dig_cts";
621 #clock-cells = <0>;
622 #phy-cells = <0>;
627 compatible = "mediatek,mt8173-gce";
631 clock-names = "gce";
632 #mbox-cells = <2>;
635 mipi_tx0: dsi-phy@10215000 {
636 compatible = "mediatek,mt8173-mipi-tx";
639 clock-output-names = "mipi_tx0_pll";
640 #clock-cells = <0>;
641 #phy-cells = <0>;
645 mipi_tx1: dsi-phy@10216000 {
646 compatible = "mediatek,mt8173-mipi-tx";
649 clock-output-names = "mipi_tx1_pll";
650 #clock-cells = <0>;
651 #phy-cells = <0>;
655 gic: interrupt-controller@10221000 {
656 compatible = "arm,gic-400";
657 #interrupt-cells = <3>;
658 interrupt-parent = <&gic>;
659 interrupt-controller;
669 compatible = "mediatek,mt8173-auxadc";
672 clock-names = "main";
673 #io-channel-cells = <1>;
677 compatible = "mediatek,mt8173-uart",
678 "mediatek,mt6577-uart";
682 clock-names = "baud", "bus";
687 compatible = "mediatek,mt8173-uart",
688 "mediatek,mt6577-uart";
692 clock-names = "baud", "bus";
697 compatible = "mediatek,mt8173-uart",
698 "mediatek,mt6577-uart";
702 clock-names = "baud", "bus";
707 compatible = "mediatek,mt8173-uart",
708 "mediatek,mt6577-uart";
712 clock-names = "baud", "bus";
717 compatible = "mediatek,mt8173-i2c";
721 clock-div = <16>;
724 clock-names = "main", "dma";
725 pinctrl-names = "default";
726 pinctrl-0 = <&i2c0_pins_a>;
727 #address-cells = <1>;
728 #size-cells = <0>;
733 compatible = "mediatek,mt8173-i2c";
737 clock-div = <16>;
740 clock-names = "main", "dma";
741 pinctrl-names = "default";
742 pinctrl-0 = <&i2c1_pins_a>;
743 #address-cells = <1>;
744 #size-cells = <0>;
749 compatible = "mediatek,mt8173-i2c";
753 clock-div = <16>;
756 clock-names = "main", "dma";
757 pinctrl-names = "default";
758 pinctrl-0 = <&i2c2_pins_a>;
759 #address-cells = <1>;
760 #size-cells = <0>;
765 compatible = "mediatek,mt8173-spi";
766 #address-cells = <1>;
767 #size-cells = <0>;
773 clock-names = "parent-clk", "sel-clk", "spi-clk";
778 #thermal-sensor-cells = <0>;
779 compatible = "mediatek,mt8173-thermal";
783 clock-names = "therm", "auxadc";
787 nvmem-cells = <&thermal_calibration>;
788 nvmem-cell-names = "calibration-data";
792 compatible = "mediatek,mt8173-nor";
794 assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>;
795 assigned-clock-parents = <&clk26m>;
799 clock-names = "spi", "sf", "axi";
800 #address-cells = <1>;
801 #size-cells = <0>;
806 compatible = "mediatek,mt8173-i2c";
810 clock-div = <16>;
813 clock-names = "main", "dma";
814 pinctrl-names = "default";
815 pinctrl-0 = <&i2c3_pins_a>;
816 #address-cells = <1>;
817 #size-cells = <0>;
822 compatible = "mediatek,mt8173-i2c";
826 clock-div = <16>;
829 clock-names = "main", "dma";
830 pinctrl-names = "default";
831 pinctrl-0 = <&i2c4_pins_a>;
832 #address-cells = <1>;
833 #size-cells = <0>;
838 compatible = "mediatek,mt8173-hdmi-ddc";
842 clock-names = "ddc-i2c";
846 compatible = "mediatek,mt8173-i2c";
850 clock-div = <16>;
853 clock-names = "main", "dma";
854 pinctrl-names = "default";
855 pinctrl-0 = <&i2c6_pins_a>;
856 #address-cells = <1>;
857 #size-cells = <0>;
861 afe: audio-controller@11220000 {
862 compatible = "mediatek,mt8173-afe-pcm";
865 power-domains = <&spm MT8173_POWER_DOMAIN_AUDIO>;
876 clock-names = "infra_sys_audio_clk",
886 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
888 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
893 compatible = "mediatek,mt8173-mmc";
898 clock-names = "source", "hclk";
903 compatible = "mediatek,mt8173-mmc";
908 clock-names = "source", "hclk";
913 compatible = "mediatek,mt8173-mmc";
918 clock-names = "source", "hclk";
923 compatible = "mediatek,mt8173-mmc";
928 clock-names = "source", "hclk";
933 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3";
936 reg-names = "mac", "ippc";
941 power-domains = <&spm MT8173_POWER_DOMAIN_USB>;
943 clock-names = "sys_ck", "ref_ck";
944 mediatek,syscon-wakeup = <&pericfg 0x400 1>;
945 #address-cells = <2>;
946 #size-cells = <2>;
951 compatible = "mediatek,mt8173-xhci",
952 "mediatek,mtk-xhci";
954 reg-names = "mac";
956 power-domains = <&spm MT8173_POWER_DOMAIN_USB>;
958 clock-names = "sys_ck", "ref_ck";
963 u3phy: t-phy@11290000 {
964 compatible = "mediatek,mt8173-u3phy";
966 #address-cells = <2>;
967 #size-cells = <2>;
971 u2port0: usb-phy@11290800 {
974 clock-names = "ref";
975 #phy-cells = <1>;
979 u3port0: usb-phy@11290900 {
982 clock-names = "ref";
983 #phy-cells = <1>;
987 u2port1: usb-phy@11291000 {
990 clock-names = "ref";
991 #phy-cells = <1>;
997 compatible = "mediatek,mt8173-mmsys", "syscon";
999 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1000 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
1001 assigned-clock-rates = <400000000>;
1002 #clock-cells = <1>;
1003 #reset-cells = <1>;
1006 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1010 compatible = "mediatek,mt8173-mdp-rdma",
1011 "mediatek,mt8173-mdp";
1015 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1021 compatible = "mediatek,mt8173-mdp-rdma";
1025 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1030 compatible = "mediatek,mt8173-mdp-rsz";
1033 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1037 compatible = "mediatek,mt8173-mdp-rsz";
1040 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1044 compatible = "mediatek,mt8173-mdp-rsz";
1047 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1051 compatible = "mediatek,mt8173-mdp-wdma";
1054 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1059 compatible = "mediatek,mt8173-mdp-wrot";
1062 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1067 compatible = "mediatek,mt8173-mdp-wrot";
1070 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1075 compatible = "mediatek,mt8173-disp-ovl";
1078 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1081 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1085 compatible = "mediatek,mt8173-disp-ovl";
1088 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1091 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1095 compatible = "mediatek,mt8173-disp-rdma";
1098 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1101 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1105 compatible = "mediatek,mt8173-disp-rdma";
1108 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1111 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1115 compatible = "mediatek,mt8173-disp-rdma";
1118 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1121 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
1125 compatible = "mediatek,mt8173-disp-wdma";
1128 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1131 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1135 compatible = "mediatek,mt8173-disp-wdma";
1138 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1141 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
1145 compatible = "mediatek,mt8173-disp-color";
1148 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1150 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
1154 compatible = "mediatek,mt8173-disp-color";
1157 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1159 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
1163 compatible = "mediatek,mt8173-disp-aal";
1166 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1168 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
1172 compatible = "mediatek,mt8173-disp-gamma";
1175 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1177 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
1181 compatible = "mediatek,mt8173-disp-merge";
1183 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1188 compatible = "mediatek,mt8173-disp-split";
1190 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1195 compatible = "mediatek,mt8173-disp-split";
1197 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1202 compatible = "mediatek,mt8173-disp-ufoe";
1205 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1207 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>;
1211 compatible = "mediatek,mt8173-dsi";
1214 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1218 clock-names = "engine", "digital", "hs";
1221 phy-names = "dphy";
1226 compatible = "mediatek,mt8173-dsi";
1229 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1233 clock-names = "engine", "digital", "hs";
1235 phy-names = "dphy";
1240 compatible = "mediatek,mt8173-dpi";
1243 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1247 clock-names = "pixel", "engine", "pll";
1252 remote-endpoint = <&hdmi0_in>;
1258 compatible = "mediatek,mt8173-disp-pwm",
1259 "mediatek,mt6595-disp-pwm";
1261 #pwm-cells = <2>;
1264 clock-names = "main", "mm";
1269 compatible = "mediatek,mt8173-disp-pwm",
1270 "mediatek,mt6595-disp-pwm";
1272 #pwm-cells = <2>;
1275 clock-names = "main", "mm";
1280 compatible = "mediatek,mt8173-disp-mutex";
1283 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1285 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>;
1286 mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
1291 compatible = "mediatek,mt8173-smi-larb";
1294 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1297 clock-names = "apb", "smi";
1301 compatible = "mediatek,mt8173-smi-common";
1303 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1306 clock-names = "apb", "smi";
1310 compatible = "mediatek,mt8173-disp-od";
1313 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>;
1316 hdmi0: hdmi@14025000 {
1317 compatible = "mediatek,mt8173-hdmi";
1324 clock-names = "pixel", "pll", "bclk", "spdif";
1325 pinctrl-names = "default";
1326 pinctrl-0 = <&hdmi_pin>;
1328 phy-names = "hdmi";
1329 mediatek,syscon-hdmi = <&mmsys 0x900>;
1330 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
1331 assigned-clock-parents = <&hdmi_phy>;
1335 #address-cells = <1>;
1336 #size-cells = <0>;
1342 remote-endpoint = <&dpi0_out>;
1349 compatible = "mediatek,mt8173-smi-larb";
1352 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1355 clock-names = "apb", "smi";
1358 imgsys: clock-controller@15000000 {
1359 compatible = "mediatek,mt8173-imgsys", "syscon";
1361 #clock-cells = <1>;
1365 compatible = "mediatek,mt8173-smi-larb";
1368 power-domains = <&spm MT8173_POWER_DOMAIN_ISP>;
1371 clock-names = "apb", "smi";
1374 vdecsys: clock-controller@16000000 {
1375 compatible = "mediatek,mt8173-vdecsys", "syscon";
1377 #clock-cells = <1>;
1381 compatible = "mediatek,mt8173-vcodec-dec";
1393 reg-names = "misc", "ld", "top", "cm", "ad", "av", "pp",
1406 power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>;
1415 clock-names = "vcodecpll",
1423 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
1428 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
1431 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
1435 compatible = "mediatek,mt8173-smi-larb";
1438 power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>;
1441 clock-names = "apb", "smi";
1444 vencsys: clock-controller@18000000 {
1445 compatible = "mediatek,mt8173-vencsys", "syscon";
1447 #clock-cells = <1>;
1451 compatible = "mediatek,mt8173-smi-larb";
1454 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
1457 clock-names = "apb", "smi";
1461 compatible = "mediatek,mt8173-vcodec-enc";
1477 clock-names = "venc_sel";
1478 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
1479 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
1480 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
1484 compatible = "mediatek,mt8173-jpgdec";
1489 clock-names = "jpgdec-smi",
1491 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
1496 vencltsys: clock-controller@19000000 {
1497 compatible = "mediatek,mt8173-vencltsys", "syscon";
1499 #clock-cells = <1>;
1503 compatible = "mediatek,mt8173-smi-larb";
1506 power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>;
1509 clock-names = "apb", "smi";
1513 compatible = "mediatek,mt8173-vcodec-enc-vp8";
1527 clock-names = "venc_lt_sel";
1528 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
1529 assigned-clock-parents =
1531 power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>;