Lines Matching full:mmsys
996 mmsys: syscon@14000000 { label
997 compatible = "mediatek,mt8173-mmsys", "syscon";
1013 clocks = <&mmsys CLK_MM_MDP_RDMA0>,
1014 <&mmsys CLK_MM_MUTEX_32K>;
1023 clocks = <&mmsys CLK_MM_MDP_RDMA1>,
1024 <&mmsys CLK_MM_MUTEX_32K>;
1032 clocks = <&mmsys CLK_MM_MDP_RSZ0>;
1039 clocks = <&mmsys CLK_MM_MDP_RSZ1>;
1046 clocks = <&mmsys CLK_MM_MDP_RSZ2>;
1053 clocks = <&mmsys CLK_MM_MDP_WDMA>;
1061 clocks = <&mmsys CLK_MM_MDP_WROT0>;
1069 clocks = <&mmsys CLK_MM_MDP_WROT1>;
1079 clocks = <&mmsys CLK_MM_DISP_OVL0>;
1089 clocks = <&mmsys CLK_MM_DISP_OVL1>;
1099 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
1109 clocks = <&mmsys CLK_MM_DISP_RDMA1>;
1119 clocks = <&mmsys CLK_MM_DISP_RDMA2>;
1129 clocks = <&mmsys CLK_MM_DISP_WDMA0>;
1139 clocks = <&mmsys CLK_MM_DISP_WDMA1>;
1149 clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1158 clocks = <&mmsys CLK_MM_DISP_COLOR1>;
1167 clocks = <&mmsys CLK_MM_DISP_AAL>;
1176 clocks = <&mmsys CLK_MM_DISP_GAMMA>;
1184 clocks = <&mmsys CLK_MM_DISP_MERGE>;
1191 clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
1198 clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
1206 clocks = <&mmsys CLK_MM_DISP_UFOE>;
1215 clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
1216 <&mmsys CLK_MM_DSI0_DIGITAL>,
1219 resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
1230 clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
1231 <&mmsys CLK_MM_DSI1_DIGITAL>,
1244 clocks = <&mmsys CLK_MM_DPI_PIXEL>,
1245 <&mmsys CLK_MM_DPI_ENGINE>,
1262 clocks = <&mmsys CLK_MM_DISP_PWM026M>,
1263 <&mmsys CLK_MM_DISP_PWM0MM>;
1273 clocks = <&mmsys CLK_MM_DISP_PWM126M>,
1274 <&mmsys CLK_MM_DISP_PWM1MM>;
1284 clocks = <&mmsys CLK_MM_MUTEX_32K>;
1295 clocks = <&mmsys CLK_MM_SMI_LARB0>,
1296 <&mmsys CLK_MM_SMI_LARB0>;
1304 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1305 <&mmsys CLK_MM_SMI_COMMON>;
1312 clocks = <&mmsys CLK_MM_DISP_OD>;
1320 clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
1321 <&mmsys CLK_MM_HDMI_PLLCK>,
1322 <&mmsys CLK_MM_HDMI_AUDIO>,
1323 <&mmsys CLK_MM_HDMI_SPDIF>;
1329 mediatek,syscon-hdmi = <&mmsys 0x900>;
1353 clocks = <&mmsys CLK_MM_SMI_LARB4>,
1354 <&mmsys CLK_MM_SMI_LARB4>;