Lines Matching +full:0 +full:x1401d000
53 cluster0_opp: opp-table-0 {
129 #size-cells = <0>;
151 cpu0: cpu@0 {
154 reg = <0x000>;
169 reg = <0x001>;
184 reg = <0x100>;
199 reg = <0x101>;
214 CPU_SLEEP_0: cpu-sleep-0 {
220 arm,psci-suspend-param = <0x0010000>;
242 cpu_suspend = <0x84000001>;
243 cpu_off = <0x84000002>;
244 cpu_on = <0x84000003>;
249 #clock-cells = <0>;
256 #clock-cells = <0>;
263 #clock-cells = <0>;
264 clock-frequency = <0>;
323 reg = <0 0xb7000000 0 0x500000>;
324 alignment = <0x1000>;
351 reg = <0 0x10000000 0 0x1000>;
357 reg = <0 0x10001000 0 0x1000>;
364 reg = <0 0x10003000 0 0x1000>;
371 reg = <0 0x10005000 0 0x1000>;
376 reg = <0 0x1000b000 0 0x1000>;
447 reg = <0 0x10006000 0 0x1000>;
453 #size-cells = <0>;
461 #power-domain-cells = <0>;
468 #power-domain-cells = <0>;
474 #power-domain-cells = <0>;
480 #power-domain-cells = <0>;
488 #power-domain-cells = <0>;
492 #power-domain-cells = <0>;
496 #power-domain-cells = <0>;
503 #size-cells = <0>;
509 #size-cells = <0>;
514 #power-domain-cells = <0>;
525 reg = <0 0x10007000 0 0x100>;
531 reg = <0 0x10008000 0 0x1000>;
539 reg = <0 0x1000d000 0 0x1000>;
550 reg = <0 0x10013000 0 0xbc>;
558 reg = <0 0x10020000 0 0x30000>,
559 <0 0x10050000 0 0x100>;
573 reg = <0 0x10200620 0 0x20>;
578 reg = <0 0x10205000 0 0x1000>;
590 reg = <0 0x10206000 0 0x1000>;
595 reg = <0x040 0x4>;
599 reg = <0x044 0x4>;
603 reg = <0x528 0xc>;
609 reg = <0 0x10209000 0 0x1000>;
615 reg = <0 0x10209100 0 0x24>;
619 mediatek,ibias = <0xa>;
620 mediatek,ibias_up = <0x1c>;
621 #clock-cells = <0>;
622 #phy-cells = <0>;
628 reg = <0 0x10212000 0 0x1000>;
637 reg = <0 0x10215000 0 0x1000>;
640 #clock-cells = <0>;
641 #phy-cells = <0>;
647 reg = <0 0x10216000 0 0x1000>;
650 #clock-cells = <0>;
651 #phy-cells = <0>;
660 reg = <0 0x10221000 0 0x1000>,
661 <0 0x10222000 0 0x2000>,
662 <0 0x10224000 0 0x2000>,
663 <0 0x10226000 0 0x2000>;
670 reg = <0 0x11001000 0 0x1000>;
679 reg = <0 0x11002000 0 0x400>;
689 reg = <0 0x11003000 0 0x400>;
699 reg = <0 0x11004000 0 0x400>;
709 reg = <0 0x11005000 0 0x400>;
718 reg = <0 0x11007000 0 0x70>,
719 <0 0x11000100 0 0x80>;
726 pinctrl-0 = <&i2c0_pins_a>;
728 #size-cells = <0>;
734 reg = <0 0x11008000 0 0x70>,
735 <0 0x11000180 0 0x80>;
742 pinctrl-0 = <&i2c1_pins_a>;
744 #size-cells = <0>;
750 reg = <0 0x11009000 0 0x70>,
751 <0 0x11000200 0 0x80>;
758 pinctrl-0 = <&i2c2_pins_a>;
760 #size-cells = <0>;
767 #size-cells = <0>;
768 reg = <0 0x1100a000 0 0x1000>;
778 #thermal-sensor-cells = <0>;
780 reg = <0 0x1100b000 0 0x1000>;
781 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
793 reg = <0 0x1100d000 0 0xe0>;
801 #size-cells = <0>;
807 reg = <0 0x11010000 0 0x70>,
808 <0 0x11000280 0 0x80>;
815 pinctrl-0 = <&i2c3_pins_a>;
817 #size-cells = <0>;
823 reg = <0 0x11011000 0 0x70>,
824 <0 0x11000300 0 0x80>;
831 pinctrl-0 = <&i2c4_pins_a>;
833 #size-cells = <0>;
840 reg = <0 0x11012000 0 0x1C>;
847 reg = <0 0x11013000 0 0x70>,
848 <0 0x11000080 0 0x80>;
855 pinctrl-0 = <&i2c6_pins_a>;
857 #size-cells = <0>;
863 reg = <0 0x11220000 0 0x1000>;
894 reg = <0 0x11230000 0 0x1000>;
904 reg = <0 0x11240000 0 0x1000>;
914 reg = <0 0x11250000 0 0x1000>;
924 reg = <0 0x11260000 0 0x1000>;
934 reg = <0 0x11271000 0 0x3000>,
935 <0 0x11280700 0 0x0100>;
944 mediatek,syscon-wakeup = <&pericfg 0x400 1>;
953 reg = <0 0x11270000 0 0x1000>;
965 reg = <0 0x11290000 0 0x800>;
972 reg = <0 0x11290800 0 0x100>;
980 reg = <0 0x11290900 0 0x700>;
988 reg = <0 0x11291000 0 0x100>;
998 reg = <0 0x14000000 0 0x1000>;
1004 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1006 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1012 reg = <0 0x14001000 0 0x1000>;
1022 reg = <0 0x14002000 0 0x1000>;
1031 reg = <0 0x14003000 0 0x1000>;
1038 reg = <0 0x14004000 0 0x1000>;
1045 reg = <0 0x14005000 0 0x1000>;
1052 reg = <0 0x14006000 0 0x1000>;
1060 reg = <0 0x14007000 0 0x1000>;
1068 reg = <0 0x14008000 0 0x1000>;
1076 reg = <0 0x1400c000 0 0x1000>;
1081 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1086 reg = <0 0x1400d000 0 0x1000>;
1091 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1096 reg = <0 0x1400e000 0 0x1000>;
1101 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1106 reg = <0 0x1400f000 0 0x1000>;
1111 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1116 reg = <0 0x14010000 0 0x1000>;
1121 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
1126 reg = <0 0x14011000 0 0x1000>;
1131 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1136 reg = <0 0x14012000 0 0x1000>;
1141 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
1146 reg = <0 0x14013000 0 0x1000>;
1150 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
1155 reg = <0 0x14014000 0 0x1000>;
1159 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
1164 reg = <0 0x14015000 0 0x1000>;
1168 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
1173 reg = <0 0x14016000 0 0x1000>;
1177 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
1182 reg = <0 0x14017000 0 0x1000>;
1189 reg = <0 0x14018000 0 0x1000>;
1196 reg = <0 0x14019000 0 0x1000>;
1203 reg = <0 0x1401a000 0 0x1000>;
1207 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>;
1212 reg = <0 0x1401b000 0 0x1000>;
1227 reg = <0 0x1401c000 0 0x1000>;
1241 reg = <0 0x1401d000 0 0x1000>;
1260 reg = <0 0x1401e000 0 0x1000>;
1271 reg = <0 0x1401f000 0 0x1000>;
1281 reg = <0 0x14020000 0 0x1000>;
1285 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>;
1292 reg = <0 0x14021000 0 0x1000>;
1302 reg = <0 0x14022000 0 0x1000>;
1311 reg = <0 0x14023000 0 0x1000>;
1313 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>;
1318 reg = <0 0x14025000 0 0x400>;
1326 pinctrl-0 = <&hdmi_pin>;
1329 mediatek,syscon-hdmi = <&mmsys 0x900>;
1336 #size-cells = <0>;
1338 port@0 {
1339 reg = <0>;
1350 reg = <0 0x14027000 0 0x1000>;
1360 reg = <0 0x15000000 0 0x1000>;
1366 reg = <0 0x15001000 0 0x1000>;
1376 reg = <0 0x16000000 0 0x1000>;
1382 reg = <0 0x16020000 0 0x1000>, /* VDEC_MISC */
1383 <0 0x16021000 0 0x800>, /* VDEC_LD */
1384 <0 0x16021800 0 0x800>, /* VDEC_TOP */
1385 <0 0x16022000 0 0x1000>, /* VDEC_CM */
1386 <0 0x16023000 0 0x1000>, /* VDEC_AD */
1387 <0 0x16024000 0 0x1000>, /* VDEC_AV */
1388 <0 0x16025000 0 0x1000>, /* VDEC_PP */
1389 <0 0x16026800 0 0x800>, /* VDEC_HWD */
1390 <0 0x16027000 0 0x800>, /* VDEC_HWQ */
1391 <0 0x16027800 0 0x800>, /* VDEC_HWB */
1392 <0 0x16028400 0 0x400>; /* VDEC_HWG */
1431 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
1436 reg = <0 0x16010000 0 0x1000>;
1446 reg = <0 0x18000000 0 0x1000>;
1452 reg = <0 0x18001000 0 0x1000>;
1462 reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */
1485 reg = <0 0x18004000 0 0x1000>;
1498 reg = <0 0x19000000 0 0x1000>;
1504 reg = <0 0x19001000 0 0x1000>;
1514 reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */