Lines Matching +full:0 +full:x11d20000
46 #size-cells = <0>;
48 cpu0: cpu@0 {
50 reg = <0x0>;
62 reg = <0x1>;
74 reg = <0x2>;
86 reg = <0x3>;
96 cluster0_opp: opp-table-0 {
122 #clock-cells = <0>;
144 reg = <0 0x43000000 0 0x50000>;
157 reg = <0 0x0c000000 0 0x40000>, /* GICD */
158 <0 0x0c080000 0 0x200000>, /* GICR */
159 <0 0x0c400000 0 0x2000>, /* GICC */
160 <0 0x0c410000 0 0x1000>, /* GICH */
161 <0 0x0c420000 0 0x2000>; /* GICV */
170 reg = <0 0x10001000 0 0x1000>;
177 reg = <0 0x1001b000 0 0x1000>;
183 reg = <0 0x1001c000 0 0x1000>;
190 reg = <0 0x1001e000 0 0x1000>;
196 reg = <0 0x1001f000 0 0x1000>,
197 <0 0x11c10000 0 0x1000>,
198 <0 0x11d00000 0 0x1000>,
199 <0 0x11d20000 0 0x1000>,
200 <0 0x11e00000 0 0x1000>,
201 <0 0x11f00000 0 0x1000>,
202 <0 0x1000b000 0 0x1000>;
208 gpio-ranges = <&pio 0 0 84>;
263 reg = <0 0x10048000 0 0x1000>;
282 reg = <0 0x100e0000 0 0x1000>;
288 reg = <0 0x11000000 0 0x100>;
295 pinctrl-0 = <&uart0_pins>;
301 reg = <0 0x11000100 0 0x100>;
312 reg = <0 0x11000200 0 0x100>;
323 reg = <0 0x11003000 0 0x1000>,
324 <0 0x10217080 0 0x80>;
331 #size-cells = <0>;
337 reg = <0 0x11004000 0 0x1000>,
338 <0 0x10217100 0 0x80>;
345 #size-cells = <0>;
351 reg = <0 0x11005000 0 0x1000>,
352 <0 0x10217180 0 0x80>;
359 #size-cells = <0>;
365 reg = <0 0x11007000 0 0x100>;
374 #size-cells = <0>;
380 reg = <0 0x11008000 0 0x100>;
389 #size-cells = <0>;
391 pinctrl-0 = <&spi1_pins>;
397 reg = <0 0x11009000 0 0x100>;
406 #size-cells = <0>;
413 reg = <0 0x1100a000 0 0x1000>;
423 reg = <0 0x11190000 0 0x2e00>,
424 <0 0x11193e00 0 0x0100>;
440 reg = <0 0x11200000 0 0x2e00>,
441 <0 0x11203e00 0 0x0100>;
457 reg = <0 0x11230000 0 0x1000>,
458 <0 0x11D60000 0 0x1000>;
470 #size-cells = <0>;
480 reg = <0 0x11280000 0 0x2000>;
484 bus-range = <0x00 0xff>;
485 ranges = <0x81000000 0x00 0x20000000 0x00
486 0x20000000 0x00 0x00200000>,
487 <0x82000000 0x00 0x20200000 0x00
488 0x20200000 0x00 0x07e00000>;
496 pinctrl-0 = <&pcie2_pins>;
503 interrupt-map-mask = <0 0 0 0x7>;
504 interrupt-map = <0 0 0 1 &pcie_intc2 0>,
505 <0 0 0 2 &pcie_intc2 1>,
506 <0 0 0 3 &pcie_intc2 2>,
507 <0 0 0 4 &pcie_intc2 3>;
509 #address-cells = <0>;
521 reg = <0 0x11290000 0 0x2000>;
525 bus-range = <0x00 0xff>;
526 ranges = <0x81000000 0x00 0x28000000 0x00
527 0x28000000 0x00 0x00200000>,
528 <0x82000000 0x00 0x28200000 0x00
529 0x28200000 0x00 0x07e00000>;
537 pinctrl-0 = <&pcie3_pins>;
541 interrupt-map-mask = <0 0 0 0x7>;
542 interrupt-map = <0 0 0 1 &pcie_intc3 0>,
543 <0 0 0 2 &pcie_intc3 1>,
544 <0 0 0 3 &pcie_intc3 2>,
545 <0 0 0 4 &pcie_intc3 3>;
547 #address-cells = <0>;
559 reg = <0 0x11300000 0 0x2000>;
561 linux,pci-domain = <0>;
563 bus-range = <0x00 0xff>;
564 ranges = <0x81000000 0x00 0x30000000 0x00
565 0x30000000 0x00 0x00200000>,
566 <0x82000000 0x00 0x30200000 0x00
567 0x30200000 0x00 0x07e00000>;
575 pinctrl-0 = <&pcie0_pins>;
579 interrupt-map-mask = <0 0 0 0x7>;
580 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
581 <0 0 0 2 &pcie_intc0 1>,
582 <0 0 0 3 &pcie_intc0 2>,
583 <0 0 0 4 &pcie_intc0 3>;
585 #address-cells = <0>;
597 reg = <0 0x11310000 0 0x2000>;
601 bus-range = <0x00 0xff>;
602 ranges = <0x81000000 0x00 0x38000000 0x00
603 0x38000000 0x00 0x00200000>,
604 <0x82000000 0x00 0x38200000 0x00
605 0x38200000 0x00 0x07e00000>;
613 pinctrl-0 = <&pcie1_pins>;
617 interrupt-map-mask = <0 0 0 0x7>;
618 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
619 <0 0 0 2 &pcie_intc1 1>,
620 <0 0 0 3 &pcie_intc1 2>,
621 <0 0 0 4 &pcie_intc1 3>;
623 #address-cells = <0>;
638 reg = <0 0x11c50000 0 0x700>;
645 reg = <0 0x11c50700 0 0x900>;
656 reg = <0 0x11d10084 0 0xff80>;
668 reg = <0 0x11e10000 0 0x400>;
675 reg = <0 0x11e13400 0 0x500>;
679 mediatek,syscon-type = <&topmisc 0x194 0>;
685 reg = <0 0x11f40000 0 0x1000>;
692 reg = <0 0x11f50000 0 0x1000>;
697 reg = <0x918 0x28>;
701 reg = <0x940 0x10>;
705 reg = <0x954 0x10>;
709 reg = <0x968 0x10>;
713 reg = <0x97c 0x10>;
719 reg = <0 0x15000000 0 0x1000>;
726 reg = <0 0x15031000 0 0x1000>;
736 thermal-sensors = <&lvts 0>;