Lines Matching +full:mt6577 +full:- +full:uart +full:- +full:dma
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/mt7986-clk.h>
10 #include <dt-bindings/reset/mt7986-resets.h>
11 #include <dt-bindings/phy/phy.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
23 compatible = "arm,cortex-a53";
26 enable-method = "psci";
27 #cooling-cells = <2>;
31 compatible = "arm,cortex-a53";
34 enable-method = "psci";
35 #cooling-cells = <2>;
39 compatible = "arm,cortex-a53";
42 enable-method = "psci";
43 #cooling-cells = <2>;
47 compatible = "arm,cortex-a53";
50 enable-method = "psci";
51 #cooling-cells = <2>;
55 clk40m: oscillator-40m {
56 compatible = "fixed-clock";
57 clock-frequency = <40000000>;
58 #clock-cells = <0>;
59 clock-output-names = "clkxtal";
63 compatible = "arm,psci-0.2";
67 reserved-memory {
68 #address-cells = <2>;
69 #size-cells = <2>;
74 no-map;
77 wmcpu_emi: wmcpu-reserved@4fc00000 {
78 no-map;
82 wo_emi0: wo-emi@4fd00000 {
84 no-map;
87 wo_emi1: wo-emi@4fd40000 {
89 no-map;
92 wo_ilm0: wo-ilm@151e0000 {
94 no-map;
97 wo_ilm1: wo-ilm@151f0000 {
99 no-map;
102 wo_data: wo-data@4fd80000 {
104 no-map;
107 wo_dlm0: wo-dlm@151e8000 {
109 no-map;
112 wo_dlm1: wo-dlm@151f8000 {
114 no-map;
117 wo_boot: wo-boot@15194000 {
119 no-map;
125 compatible = "simple-bus";
127 #address-cells = <2>;
128 #size-cells = <2>;
130 gic: interrupt-controller@c000000 {
131 compatible = "arm,gic-v3";
137 interrupt-parent = <&gic>;
139 interrupt-controller;
140 #interrupt-cells = <3>;
144 compatible = "mediatek,mt7986-infracfg", "syscon";
146 #clock-cells = <1>;
147 #reset-cells = <1>;
150 wed_pcie: wed-pcie@10003000 {
151 compatible = "mediatek,mt7986-wed-pcie",
157 compatible = "mediatek,mt7986-topckgen", "syscon";
159 #clock-cells = <1>;
163 compatible = "mediatek,mt7986-wdt";
166 #reset-cells = <1>;
171 compatible = "mediatek,mt7986-apmixedsys";
173 #clock-cells = <1>;
177 compatible = "mediatek,mt7986a-pinctrl";
186 reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
188 gpio-controller;
189 #gpio-cells = <2>;
190 gpio-ranges = <&pio 0 0 100>;
191 interrupt-controller;
193 interrupt-parent = <&gic>;
194 #interrupt-cells = <2>;
198 compatible = "mediatek,mt7986-pwm";
200 #pwm-cells = <2>;
206 clock-names = "top", "main", "pwm1", "pwm2";
211 compatible = "mediatek,mt7986-sgmiisys_0",
214 #clock-cells = <1>;
218 compatible = "mediatek,mt7986-sgmiisys_1",
221 #clock-cells = <1>;
225 compatible = "mediatek,mt7986-rng",
226 "mediatek,mt7623-rng";
229 clock-names = "rng";
234 compatible = "inside-secure,safexcel-eip97";
240 interrupt-names = "ring0", "ring1", "ring2", "ring3";
242 assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
243 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
248 compatible = "mediatek,mt7986-uart",
249 "mediatek,mt6577-uart";
254 clock-names = "baud", "bus";
255 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
257 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
263 compatible = "mediatek,mt7986-uart",
264 "mediatek,mt6577-uart";
269 clock-names = "baud", "bus";
270 assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
271 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
276 compatible = "mediatek,mt7986-uart",
277 "mediatek,mt6577-uart";
282 clock-names = "baud", "bus";
283 assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
284 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
289 compatible = "mediatek,mt7986-i2c";
293 clock-div = <5>;
296 clock-names = "main", "dma";
297 #address-cells = <1>;
298 #size-cells = <0>;
303 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
305 #address-cells = <1>;
306 #size-cells = <0>;
312 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
317 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
319 #address-cells = <1>;
320 #size-cells = <0>;
326 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
331 compatible = "mediatek,mt7986-thermal";
336 clock-names = "therm", "auxadc";
337 nvmem-cells = <&thermal_calibration>;
338 nvmem-cell-names = "calibration-data";
339 #thermal-sensor-cells = <1>;
345 compatible = "mediatek,mt7986-auxadc";
348 clock-names = "main";
349 #io-channel-cells = <1>;
354 compatible = "mediatek,mt7986-xhci",
355 "mediatek,mtk-xhci";
358 reg-names = "mac", "ippc";
365 clock-names = "sys_ck",
377 compatible = "mediatek,mt7986-mmc";
381 assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
383 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MPLL>,
390 clock-names = "source", "hclk", "source_cg", "bus_clk",
396 compatible = "mediatek,mt7986-pcie",
397 "mediatek,mt8192-pcie";
399 reg-names = "pcie-mac";
403 #address-cells = <3>;
404 #size-cells = <2>;
406 bus-range = <0x00 0xff>;
411 clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
414 phy-names = "pcie-phy";
416 #interrupt-cells = <1>;
417 interrupt-map-mask = <0 0 0 0x7>;
418 interrupt-map = <0 0 0 1 &pcie_intc 0>,
424 pcie_intc: interrupt-controller {
425 #address-cells = <0>;
426 #interrupt-cells = <1>;
427 interrupt-controller;
431 pcie_phy: t-phy {
432 compatible = "mediatek,mt7986-tphy",
433 "mediatek,generic-tphy-v2";
435 #address-cells = <2>;
436 #size-cells = <2>;
439 pcie_port: pcie-phy@11c00000 {
442 clock-names = "ref";
443 #phy-cells = <1>;
448 compatible = "mediatek,mt7986-efuse", "mediatek,efuse";
450 #address-cells = <1>;
451 #size-cells = <1>;
458 usb_phy: t-phy@11e10000 {
459 compatible = "mediatek,mt7986-tphy",
460 "mediatek,generic-tphy-v2";
462 #address-cells = <1>;
463 #size-cells = <1>;
466 u2port0: usb-phy@0 {
470 clock-names = "ref", "da_ref";
471 #phy-cells = <1>;
474 u3port0: usb-phy@700 {
477 clock-names = "ref";
478 #phy-cells = <1>;
481 u2port1: usb-phy@1000 {
485 clock-names = "ref", "da_ref";
486 #phy-cells = <1>;
491 compatible = "mediatek,mt7986-ethsys",
494 #clock-cells = <1>;
495 #reset-cells = <1>;
499 compatible = "mediatek,mt7986-wed",
502 interrupt-parent = <&gic>;
504 memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
506 memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
507 "wo-data", "wo-boot";
508 mediatek,wo-ccif = <&wo_ccif0>;
512 compatible = "mediatek,mt7986-wed",
515 interrupt-parent = <&gic>;
517 memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
519 memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
520 "wo-data", "wo-boot";
521 mediatek,wo-ccif = <&wo_ccif1>;
525 compatible = "mediatek,mt7986-eth";
546 clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
552 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
554 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
556 #address-cells = <1>;
557 #size-cells = <0>;
560 mediatek,wed-pcie = <&wed_pcie>;
566 compatible = "mediatek,mt7986-wo-ccif", "syscon";
568 interrupt-parent = <&gic>;
573 compatible = "mediatek,mt7986-wo-ccif", "syscon";
575 interrupt-parent = <&gic>;
580 compatible = "mediatek,mt7986-wmac";
585 reset-names = "consys";
588 clock-names = "mcu", "ap2conn";
593 memory-region = <&wmcpu_emi>;
597 thermal-zones {
598 cpu_thermal: cpu-thermal {
599 polling-delay-passive = <1000>;
600 polling-delay = <1000>;
601 thermal-sensors = <&thermal 0>;
616 cpu_trip_active_high: active-high {
622 cpu_trip_active_med: active-med {
628 cpu_trip_active_low: active-low {
638 compatible = "arm,armv8-timer";
639 interrupt-parent = <&gic>;