Lines Matching +full:spi +full:- +full:pins
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/pinctrl/mt65xx.h>
14 chassis-type = "embedded";
15 compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
22 stdout-path = "serial0:115200n8";
30 reg_1p8v: regulator-1p8v {
31 compatible = "regulator-fixed";
32 regulator-name = "fixed-1.8V";
33 regulator-min-microvolt = <1800000>;
34 regulator-max-microvolt = <1800000>;
35 regulator-boot-on;
36 regulator-always-on;
39 reg_3p3v: regulator-3p3v {
40 compatible = "regulator-fixed";
41 regulator-name = "fixed-3.3V";
42 regulator-min-microvolt = <3300000>;
43 regulator-max-microvolt = <3300000>;
44 regulator-boot-on;
45 regulator-always-on;
57 compatible = "mediatek,eth-mac";
59 phy-mode = "2500base-x";
61 fixed-link {
63 full-duplex;
69 compatible = "mediatek,eth-mac";
71 phy-mode = "rgmii";
73 fixed-link {
75 full-duplex;
80 mdio: mdio-bus {
81 #address-cells = <1>;
82 #size-cells = <0>;
90 reset-gpios = <&pio 5 0>;
95 pinctrl-names = "default", "state_uhs";
96 pinctrl-0 = <&mmc0_pins_default>;
97 pinctrl-1 = <&mmc0_pins_uhs>;
98 bus-width = <8>;
99 max-frequency = <200000000>;
100 cap-mmc-highspeed;
101 mmc-hs200-1_8v;
102 mmc-hs400-1_8v;
103 hs400-ds-delay = <0x14014>;
104 vmmc-supply = <®_3p3v>;
105 vqmmc-supply = <®_1p8v>;
106 non-removable;
107 no-sd;
108 no-sdio;
112 pinctrl-names = "default";
113 pinctrl-0 = <&pcie_pins>;
122 mmc0_pins_default: mmc0-pins {
127 conf-cmd-dat {
128 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
131 input-enable;
132 drive-strength = <4>;
133 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
135 conf-clk {
136 pins = "EMMC_CK";
137 drive-strength = <6>;
138 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
140 conf-ds {
141 pins = "EMMC_DSL";
142 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
144 conf-rst {
145 pins = "EMMC_RSTB";
146 drive-strength = <4>;
147 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
151 mmc0_pins_uhs: mmc0-uhs-pins {
156 conf-cmd-dat {
157 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
160 input-enable;
161 drive-strength = <4>;
162 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
164 conf-clk {
165 pins = "EMMC_CK";
166 drive-strength = <6>;
167 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
169 conf-ds {
170 pins = "EMMC_DSL";
171 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
173 conf-rst {
174 pins = "EMMC_RSTB";
175 drive-strength = <4>;
176 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
180 pcie_pins: pcie-pins {
187 spi_flash_pins: spi-flash-pins {
189 function = "spi";
194 spic_pins: spic-pins {
196 function = "spi";
201 uart1_pins: uart1-pins {
208 uart2_pins: uart2-pins {
215 wf_2g_5g_pins: wf-2g-5g-pins {
221 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
228 drive-strength = <4>;
232 wf_dbdc_pins: wf-dbdc-pins {
238 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
242 drive-strength = <4>;
248 pinctrl-names = "default";
249 pinctrl-0 = <&spi_flash_pins>;
250 cs-gpios = <0>, <0>;
254 compatible = "spi-nand";
256 spi-max-frequency = <10000000>;
257 spi-tx-bus-width = <4>;
258 spi-rx-bus-width = <4>;
263 pinctrl-names = "default";
264 pinctrl-0 = <&spic_pins>;
265 cs-gpios = <0>, <0>;
275 #address-cells = <1>;
276 #size-cells = <0>;
306 phy-mode = "rgmii";
308 fixed-link {
310 full-duplex;
319 phy-mode = "2500base-x";
321 fixed-link {
323 full-duplex;
335 pinctrl-names = "default";
336 pinctrl-0 = <&uart1_pins>;
341 pinctrl-names = "default";
342 pinctrl-0 = <&uart2_pins>;
352 pinctrl-names = "default", "dbdc";
353 pinctrl-0 = <&wf_2g_5g_pins>;
354 pinctrl-1 = <&wf_dbdc_pins>;