Lines Matching +full:mt6577 +full:- +full:timer
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 #include <dt-bindings/clock/mediatek,mt7981-clk.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/reset/mt7986-resets.h>
9 interrupt-parent = <&gic>;
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "arm,cortex-a53";
21 enable-method = "psci";
25 compatible = "arm,cortex-a53";
28 enable-method = "psci";
32 oscillator-40m {
33 compatible = "fixed-clock";
34 clock-frequency = <40000000>;
35 clock-output-names = "clkxtal";
36 #clock-cells = <0>;
40 compatible = "arm,psci-1.0";
45 compatible = "simple-bus";
47 #address-cells = <2>;
48 #size-cells = <2>;
50 gic: interrupt-controller@c000000 {
51 compatible = "arm,gic-v3";
54 interrupt-parent = <&gic>;
56 interrupt-controller;
57 #interrupt-cells = <3>;
60 infracfg: clock-controller@10001000 {
61 compatible = "mediatek,mt7981-infracfg", "syscon";
63 #clock-cells = <1>;
66 topckgen: clock-controller@1001b000 {
67 compatible = "mediatek,mt7981-topckgen", "syscon";
69 #clock-cells = <1>;
73 compatible = "mediatek,mt7986-wdt";
76 #reset-cells = <1>;
79 clock-controller@1001e000 {
80 compatible = "mediatek,mt7981-apmixedsys";
82 #clock-cells = <1>;
86 compatible = "mediatek,mt7981-pwm";
93 clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
94 #pwm-cells = <2>;
98 compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";
101 interrupt-names = "uart", "wakeup";
104 clock-names = "baud", "bus";
109 compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";
112 interrupt-names = "uart", "wakeup";
115 clock-names = "baud", "bus";
120 compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";
123 interrupt-names = "uart", "wakeup";
126 clock-names = "baud", "bus";
131 compatible = "mediatek,mt7981-i2c";
139 clock-names = "main", "dma", "arb", "pmic";
140 #address-cells = <1>;
141 #size-cells = <0>;
146 compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";
153 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
154 #address-cells = <1>;
155 #size-cells = <0>;
160 compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";
167 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
168 #address-cells = <1>;
169 #size-cells = <0>;
174 compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";
181 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
182 #address-cells = <1>;
183 #size-cells = <0>;
188 compatible = "mediatek,mt7981-pinctrl";
198 reg-names = "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", "iocfg_lb",
200 interrupt-controller;
202 interrupt-parent = <&gic>;
203 gpio-ranges = <&pio 0 0 56>;
204 gpio-controller;
205 #gpio-cells = <2>;
206 #interrupt-cells = <2>;
210 compatible = "mediatek,mt7981-efuse", "mediatek,efuse";
212 #address-cells = <1>;
213 #size-cells = <1>;
216 clock-controller@15000000 {
217 compatible = "mediatek,mt7981-ethsys", "syscon";
219 #clock-cells = <1>;
220 #reset-cells = <1>;
224 compatible = "mediatek,mt7981-wmac";
234 clock-names = "mcu", "ap2conn";
236 reset-names = "consys";
240 timer {
241 compatible = "arm,armv8-timer";
242 interrupt-parent = <&gic>;