Lines Matching +full:mt7623 +full:- +full:hsdma
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt7622-clk.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt7622-power.h>
14 #include <dt-bindings/reset/mt7622-reset.h>
15 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
21 #size-cells = <2>;
23 cpu_opp_table: opp-table {
24 compatible = "operating-points-v2";
25 opp-shared;
26 opp-300000000 {
27 opp-hz = /bits/ 64 <30000000>;
28 opp-microvolt = <950000>;
31 opp-437500000 {
32 opp-hz = /bits/ 64 <437500000>;
33 opp-microvolt = <1000000>;
36 opp-600000000 {
37 opp-hz = /bits/ 64 <600000000>;
38 opp-microvolt = <1050000>;
41 opp-812500000 {
42 opp-hz = /bits/ 64 <812500000>;
43 opp-microvolt = <1100000>;
46 opp-1025000000 {
47 opp-hz = /bits/ 64 <1025000000>;
48 opp-microvolt = <1150000>;
51 opp-1137500000 {
52 opp-hz = /bits/ 64 <1137500000>;
53 opp-microvolt = <1200000>;
56 opp-1262500000 {
57 opp-hz = /bits/ 64 <1262500000>;
58 opp-microvolt = <1250000>;
61 opp-1350000000 {
62 opp-hz = /bits/ 64 <1350000000>;
63 opp-microvolt = <1310000>;
68 #address-cells = <2>;
69 #size-cells = <0>;
73 compatible = "arm,cortex-a53";
77 clock-names = "cpu", "intermediate";
78 operating-points-v2 = <&cpu_opp_table>;
79 #cooling-cells = <2>;
80 enable-method = "psci";
81 clock-frequency = <1300000000>;
82 cci-control-port = <&cci_control2>;
83 next-level-cache = <&L2>;
88 compatible = "arm,cortex-a53";
92 clock-names = "cpu", "intermediate";
93 operating-points-v2 = <&cpu_opp_table>;
94 #cooling-cells = <2>;
95 enable-method = "psci";
96 clock-frequency = <1300000000>;
97 cci-control-port = <&cci_control2>;
98 next-level-cache = <&L2>;
101 L2: l2-cache {
103 cache-level = <2>;
104 cache-unified;
109 compatible = "fixed-clock";
110 clock-frequency = <40000000>;
111 #clock-cells = <0>;
115 compatible = "fixed-clock";
116 #clock-cells = <0>;
117 clock-frequency = <25000000>;
118 clock-output-names = "clkxtal";
122 compatible = "arm,psci-0.2";
127 compatible = "arm,cortex-a53-pmu";
130 interrupt-affinity = <&cpu0>, <&cpu1>;
133 reserved-memory {
134 #address-cells = <2>;
135 #size-cells = <2>;
141 no-map;
145 thermal-zones {
146 cpu_thermal: cpu-thermal {
147 polling-delay-passive = <1000>;
148 polling-delay = <1000>;
150 thermal-sensors = <&thermal 0>;
153 cpu_passive: cpu-passive {
159 cpu_active: cpu-active {
165 cpu_hot: cpu-hot {
171 cpu-crit {
178 cooling-maps {
181 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
187 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
193 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
201 compatible = "arm,armv8-timer";
202 interrupt-parent = <&gic>;
214 compatible = "mediatek,mt7622-infracfg",
217 #clock-cells = <1>;
218 #reset-cells = <1>;
222 compatible = "mediatek,mt7622-pwrap";
224 reg-names = "pwrap";
226 clock-names = "spi", "wrap";
228 reset-names = "pwrap";
234 compatible = "mediatek,mt7622-pericfg",
237 #clock-cells = <1>;
238 #reset-cells = <1>;
241 scpsys: power-controller@10006000 {
242 compatible = "mediatek,mt7622-scpsys",
244 #power-domain-cells = <1>;
252 clock-names = "hif_sel";
255 cir: ir-receiver@10009000 {
256 compatible = "mediatek,mt7622-cir";
261 clock-names = "clk", "bus";
265 sysirq: interrupt-controller@10200620 {
266 compatible = "mediatek,mt7622-sysirq",
267 "mediatek,mt6577-sysirq";
268 interrupt-controller;
269 #interrupt-cells = <3>;
270 interrupt-parent = <&gic>;
275 compatible = "mediatek,mt7622-efuse",
278 #address-cells = <1>;
279 #size-cells = <1>;
286 apmixedsys: clock-controller@10209000 {
287 compatible = "mediatek,mt7622-apmixedsys";
289 #clock-cells = <1>;
292 topckgen: clock-controller@10210000 {
293 compatible = "mediatek,mt7622-topckgen";
295 #clock-cells = <1>;
299 compatible = "mediatek,mt7622-rng",
300 "mediatek,mt7623-rng";
303 clock-names = "rng";
307 compatible = "mediatek,mt7622-pinctrl";
310 reg-names = "base", "eint";
311 gpio-controller;
312 #gpio-cells = <2>;
313 gpio-ranges = <&pio 0 0 103>;
314 interrupt-controller;
316 interrupt-parent = <&gic>;
317 #interrupt-cells = <2>;
321 compatible = "mediatek,mt7622-wdt",
322 "mediatek,mt6589-wdt";
327 compatible = "mediatek,mt7622-rtc",
328 "mediatek,soc-rtc";
332 clock-names = "rtc";
335 gic: interrupt-controller@10300000 {
336 compatible = "arm,gic-400";
337 interrupt-controller;
338 #interrupt-cells = <3>;
339 interrupt-parent = <&gic>;
347 compatible = "arm,cci-400";
348 #address-cells = <1>;
349 #size-cells = <1>;
353 cci_control0: slave-if@1000 {
354 compatible = "arm,cci-400-ctrl-if";
355 interface-type = "ace-lite";
359 cci_control1: slave-if@4000 {
360 compatible = "arm,cci-400-ctrl-if";
361 interface-type = "ace";
365 cci_control2: slave-if@5000 {
366 compatible = "arm,cci-400-ctrl-if", "syscon";
367 interface-type = "ace";
372 compatible = "arm,cci-400-pmu,r1";
383 compatible = "mediatek,mt7622-auxadc";
386 clock-names = "main";
387 #io-channel-cells = <1>;
391 compatible = "mediatek,mt7622-uart",
392 "mediatek,mt6577-uart";
397 clock-names = "baud", "bus";
402 compatible = "mediatek,mt7622-uart",
403 "mediatek,mt6577-uart";
408 clock-names = "baud", "bus";
413 compatible = "mediatek,mt7622-uart",
414 "mediatek,mt6577-uart";
419 clock-names = "baud", "bus";
424 compatible = "mediatek,mt7622-uart",
425 "mediatek,mt6577-uart";
430 clock-names = "baud", "bus";
435 compatible = "mediatek,mt7622-pwm";
437 #pwm-cells = <2>;
447 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
453 compatible = "mediatek,mt7622-i2c";
457 clock-div = <16>;
460 clock-names = "main", "dma";
461 #address-cells = <1>;
462 #size-cells = <0>;
467 compatible = "mediatek,mt7622-i2c";
471 clock-div = <16>;
474 clock-names = "main", "dma";
475 #address-cells = <1>;
476 #size-cells = <0>;
481 compatible = "mediatek,mt7622-i2c";
485 clock-div = <16>;
488 clock-names = "main", "dma";
489 #address-cells = <1>;
490 #size-cells = <0>;
495 compatible = "mediatek,mt7622-spi";
501 clock-names = "parent-clk", "sel-clk", "spi-clk";
502 #address-cells = <1>;
503 #size-cells = <0>;
508 #thermal-sensor-cells = <1>;
509 compatible = "mediatek,mt7622-thermal";
514 clock-names = "therm", "auxadc";
518 nvmem-cells = <&thermal_calibration>;
519 nvmem-cell-names = "calibration-data";
523 compatible = "mediatek,mt7622-btif",
524 "mediatek,mtk-btif";
528 reg-shift = <2>;
529 reg-io-width = <4>;
533 compatible = "mediatek,mt7622-bluetooth";
534 power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
536 clock-names = "ref";
540 nandc: nand-controller@1100d000 {
541 compatible = "mediatek,mt7622-nfc";
546 clock-names = "nfi_clk", "pad_clk";
547 ecc-engine = <&bch>;
548 #address-cells = <1>;
549 #size-cells = <0>;
554 compatible = "mediatek,mt7622-snand";
558 clock-names = "nfi_clk", "pad_clk";
559 nand-ecc-engine = <&bch>;
560 #address-cells = <1>;
561 #size-cells = <0>;
566 compatible = "mediatek,mt7622-ecc";
570 clock-names = "nfiecc_clk";
575 compatible = "mediatek,mt7622-nor",
576 "mediatek,mt8173-nor";
580 clock-names = "spi", "sf";
581 #address-cells = <1>;
582 #size-cells = <0>;
587 compatible = "mediatek,mt7622-spi";
593 clock-names = "parent-clk", "sel-clk", "spi-clk";
594 #address-cells = <1>;
595 #size-cells = <0>;
600 compatible = "mediatek,mt7622-uart",
601 "mediatek,mt6577-uart";
606 clock-names = "baud", "bus";
610 audsys: clock-controller@11220000 {
611 compatible = "mediatek,mt7622-audsys", "syscon";
613 #clock-cells = <1>;
615 afe: audio-controller {
616 compatible = "mediatek,mt7622-audio";
619 interrupt-names = "afe", "asys";
655 clock-names = "infra_sys_audio_clk",
689 assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
693 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>,
695 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
700 compatible = "mediatek,mt7622-mmc";
705 clock-names = "source", "hclk";
707 reset-names = "hrst";
712 compatible = "mediatek,mt7622-mmc";
717 clock-names = "source", "hclk";
719 reset-names = "hrst";
724 compatible = "mediatek,mt7622-wmac";
731 power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
734 ssusbsys: clock-controller@1a000000 {
735 compatible = "mediatek,mt7622-ssusbsys";
737 #clock-cells = <1>;
738 #reset-cells = <1>;
742 compatible = "mediatek,mt7622-xhci",
743 "mediatek,mtk-xhci";
746 reg-names = "mac", "ippc";
748 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
753 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
761 u3phy: t-phy@1a0c4000 {
762 compatible = "mediatek,mt7622-tphy",
763 "mediatek,generic-tphy-v1";
765 #address-cells = <2>;
766 #size-cells = <2>;
770 u2port0: usb-phy@1a0c4800 {
772 #phy-cells = <1>;
774 clock-names = "ref";
777 u3port0: usb-phy@1a0c4900 {
779 #phy-cells = <1>;
781 clock-names = "ref";
784 u2port1: usb-phy@1a0c5000 {
786 #phy-cells = <1>;
788 clock-names = "ref";
792 pciesys: clock-controller@1a100800 {
793 compatible = "mediatek,mt7622-pciesys";
795 #clock-cells = <1>;
796 #reset-cells = <1>;
800 compatible = "mediatek,generic-pciecfg", "syscon";
805 compatible = "mediatek,mt7622-pcie";
808 reg-names = "port0";
809 linux,pci-domain = <0>;
810 #address-cells = <3>;
811 #size-cells = <2>;
813 interrupt-names = "pcie_irq";
820 clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
823 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
824 bus-range = <0x00 0xff>;
828 #interrupt-cells = <1>;
829 interrupt-map-mask = <0 0 0 7>;
830 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
834 pcie_intc0: interrupt-controller {
835 interrupt-controller;
836 #address-cells = <0>;
837 #interrupt-cells = <1>;
842 compatible = "mediatek,mt7622-pcie";
845 reg-names = "port1";
846 linux,pci-domain = <1>;
847 #address-cells = <3>;
848 #size-cells = <2>;
850 interrupt-names = "pcie_irq";
858 clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
861 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
862 bus-range = <0x00 0xff>;
866 #interrupt-cells = <1>;
867 interrupt-map-mask = <0 0 0 7>;
868 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
872 pcie_intc1: interrupt-controller {
873 interrupt-controller;
874 #address-cells = <0>;
875 #interrupt-cells = <1>;
880 compatible = "mediatek,mt7622-ahci",
881 "mediatek,mtk-ahci";
884 interrupt-names = "hostc";
890 clock-names = "ahb", "axi", "asic", "rbc", "pm";
892 phy-names = "sata-phy";
893 ports-implemented = <0x1>;
894 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
898 reset-names = "axi", "sw", "reg";
899 mediatek,phy-mode = <&pciesys>;
903 sata_phy: t-phy {
904 compatible = "mediatek,mt7622-tphy",
905 "mediatek,generic-tphy-v1";
906 #address-cells = <2>;
907 #size-cells = <2>;
911 sata_port: sata-phy@1a243000 {
914 clock-names = "ref";
915 #phy-cells = <1>;
919 hifsys: clock-controller@1af00000 {
920 compatible = "mediatek,mt7622-hifsys";
922 #clock-cells = <1>;
925 ethsys: clock-controller@1b000000 {
926 compatible = "mediatek,mt7622-ethsys",
929 #clock-cells = <1>;
930 #reset-cells = <1>;
933 hsdma: dma-controller@1b007000 { label
934 compatible = "mediatek,mt7622-hsdma";
938 clock-names = "hsdma";
939 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
940 #dma-cells = <1>;
941 dma-requests = <3>;
944 pcie_mirror: pcie-mirror@10000400 {
945 compatible = "mediatek,mt7622-pcie-mirror",
951 compatible = "mediatek,mt7622-wed",
958 compatible = "mediatek,mt7622-wed",
965 compatible = "mediatek,mt7622-eth";
981 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
985 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
988 cci-control-port = <&cci_control2>;
990 mediatek,pcie-mirror = <&pcie_mirror>;
992 dma-coherent;
993 #address-cells = <1>;
994 #size-cells = <0>;
999 compatible = "mediatek,mt7622-sgmiisys",
1002 #clock-cells = <1>;