Lines Matching +full:0 +full:x10212000

69 		#size-cells = <0>;
71 		cpu0: cpu@0 {
74 			reg = <0x0 0x0>;
89 			reg = <0x0 0x1>;
111 		#clock-cells = <0>;
116 		#clock-cells = <0>;
140 			reg = <0 0x43000000 0 0x30000>;
150 			thermal-sensors = <&thermal 0>;
216 		reg = <0 0x10000000 0 0x1000>;
223 		reg = <0 0x10001000 0 0x250>;
236 		reg = <0 0x10002000 0 0x1000>;
245 		reg = <0 0x10006000 0 0x1000>;
257 		reg = <0 0x10009000 0 0x1000>;
271 		reg = <0 0x10200620 0 0x20>;
277 		reg = <0 0x10206000 0 0x1000>;
282 			reg = <0x198 0xc>;
288 		reg = <0 0x10209000 0 0x1000>;
294 		reg = <0 0x10210000 0 0x1000>;
301 		reg = <0 0x1020f000 0 0x1000>;
308 		reg = <0 0x10211000 0 0x1000>,
309 		      <0 0x10005000 0 0x1000>;
313 		gpio-ranges = <&pio 0 0 103>;
323 		reg = <0 0x10212000 0 0x800>;
329 		reg = <0 0x10212800 0 0x200>;
340 		reg = <0 0x10310000 0 0x1000>,
341 		      <0 0x10320000 0 0x1000>,
342 		      <0 0x10340000 0 0x2000>,
343 		      <0 0x10360000 0 0x2000>;
350 		reg = <0 0x10390000 0 0x1000>;
351 		ranges = <0 0 0x10390000 0x10000>;
356 			reg = <0x1000 0x1000>;
362 			reg = <0x4000 0x1000>;
368 			reg = <0x5000 0x1000>;
373 			reg = <0x9000 0x5000>;
384 		reg = <0 0x11001000 0 0x1000>;
393 		reg = <0 0x11002000 0 0x400>;
404 		reg = <0 0x11003000 0 0x400>;
415 		reg = <0 0x11004000 0 0x400>;
426 		reg = <0 0x11005000 0 0x400>;
436 		reg = <0 0x11006000 0 0x1000>;
454 		reg = <0 0x11007000 0 0x90>,
455 		      <0 0x11000100 0 0x80>;
462 		#size-cells = <0>;
468 		reg = <0 0x11008000 0 0x90>,
469 		      <0 0x11000180 0 0x80>;
476 		#size-cells = <0>;
482 		reg = <0 0x11009000 0 0x90>,
483 		      <0 0x11000200 0 0x80>;
490 		#size-cells = <0>;
496 		reg = <0 0x1100a000 0 0x100>;
503 		#size-cells = <0>;
510 		reg = <0 0x1100b000 0 0x1000>;
511 		interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>;
525 		reg = <0 0x1100c000 0 0x1000>;
542 		reg = <0 0x1100D000 0 0x1000>;
549 		#size-cells = <0>;
555 		reg = <0 0x1100d000 0 0x1000>;
561 		#size-cells = <0>;
567 		reg = <0 0x1100e000 0 0x1000>;
577 		reg = <0 0x11014000 0 0xe0>;
582 		#size-cells = <0>;
588 		reg = <0 0x11016000 0 0x100>;
595 		#size-cells = <0>;
602 		reg = <0 0x11019000 0 0x400>;
612 		reg = <0 0x11220000 0 0x2000>;
695 			assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
701 		reg = <0 0x11230000 0 0x1000>;
713 		reg = <0 0x11240000 0 0x1000>;
725 		reg = <0 0x18000000 0 0x100000>;
736 		reg = <0 0x1a000000 0 0x1000>;
744 		reg = <0 0x1a0c0000 0 0x01000>,
745 		      <0 0x1a0c4700 0 0x0100>;
764 		reg = <0 0x1a0c4000 0 0x700>;
771 			reg = <0 0x1a0c4800 0 0x0100>;
778 			reg = <0 0x1a0c4900 0 0x0700>;
785 			reg = <0 0x1a0c5000 0 0x0100>;
794 		reg = <0 0x1a100800 0 0x1000>;
801 		reg = <0 0x1a140000 0 0x1000>;
807 		reg = <0 0x1a143000 0 0x1000>;
809 		linux,pci-domain = <0>;
824 		bus-range = <0x00 0xff>;
825 		ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
829 		interrupt-map-mask = <0 0 0 7>;
830 		interrupt-map = <0 0 0 1 &pcie_intc0 0>,
831 				<0 0 0 2 &pcie_intc0 1>,
832 				<0 0 0 3 &pcie_intc0 2>,
833 				<0 0 0 4 &pcie_intc0 3>;
836 			#address-cells = <0>;
844 		reg = <0 0x1a145000 0 0x1000>;
862 		bus-range = <0x00 0xff>;
863 		ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
867 		interrupt-map-mask = <0 0 0 7>;
868 		interrupt-map = <0 0 0 1 &pcie_intc1 0>,
869 				<0 0 0 2 &pcie_intc1 1>,
870 				<0 0 0 3 &pcie_intc1 2>,
871 				<0 0 0 4 &pcie_intc1 3>;
874 			#address-cells = <0>;
882 		reg = <0 0x1a200000 0 0x1100>;
893 		ports-implemented = <0x1>;
912 			reg = <0 0x1a243000 0 0x0100>;
921 		reg = <0 0x1af00000 0 0x70>;
928 		reg = <0 0x1b000000 0 0x1000>;
935 		reg = <0 0x1b007000 0 0x1000>;
947 		reg = <0 0x10000400 0 0x10>;
953 		reg = <0 0x1020a000 0 0x1000>;
960 		reg = <0 0x1020b000 0 0x1000>;
966 		reg = <0 0x1b100000 0 0x20000>;
994 		#size-cells = <0>;
1001 		reg = <0 0x1b128000 0 0x3000>;