Lines Matching +full:fixed +full:- +full:up
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
18 chassis-type = "embedded";
19 compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
26 stdout-path = "serial0:115200n8";
32 proc-supply = <&mt6380_vcpu_reg>;
33 sram-supply = <&mt6380_vm_reg>;
37 proc-supply = <&mt6380_vcpu_reg>;
38 sram-supply = <&mt6380_vm_reg>;
42 gpio-keys {
43 compatible = "gpio-keys";
45 key-factory {
51 key-wps {
63 reg_1p8v: regulator-1p8v {
64 compatible = "regulator-fixed";
65 regulator-name = "fixed-1.8V";
66 regulator-min-microvolt = <1800000>;
67 regulator-max-microvolt = <1800000>;
68 regulator-always-on;
71 reg_3p3v: regulator-3p3v {
72 compatible = "regulator-fixed";
73 regulator-name = "fixed-3.3V";
74 regulator-min-microvolt = <3300000>;
75 regulator-max-microvolt = <3300000>;
76 regulator-boot-on;
77 regulator-always-on;
80 reg_5v: regulator-5v {
81 compatible = "regulator-fixed";
82 regulator-name = "fixed-5V";
83 regulator-min-microvolt = <5000000>;
84 regulator-max-microvolt = <5000000>;
85 regulator-boot-on;
86 regulator-always-on;
99 pinctrl-names = "default";
100 pinctrl-0 = <&irrx_pins>;
105 pinctrl-names = "default";
106 pinctrl-0 = <ð_pins>;
110 compatible = "mediatek,eth-mac";
112 phy-mode = "2500base-x";
114 fixed-link {
116 full-duplex;
122 compatible = "mediatek,eth-mac";
124 phy-mode = "rgmii";
126 fixed-link {
128 full-duplex;
133 mdio-bus {
134 #address-cells = <1>;
135 #size-cells = <0>;
140 reset-gpios = <&pio 54 0>;
143 #address-cells = <1>;
144 #size-cells = <0>;
174 phy-mode = "rgmii";
176 fixed-link {
178 full-duplex;
187 phy-mode = "2500base-x";
189 fixed-link {
191 full-duplex;
202 pinctrl-names = "default";
203 pinctrl-0 = <&i2c1_pins>;
208 pinctrl-names = "default";
209 pinctrl-0 = <&i2c2_pins>;
214 pinctrl-names = "default", "state_uhs";
215 pinctrl-0 = <&emmc_pins_default>;
216 pinctrl-1 = <&emmc_pins_uhs>;
218 bus-width = <8>;
219 max-frequency = <50000000>;
220 cap-mmc-highspeed;
221 mmc-hs200-1_8v;
222 vmmc-supply = <®_3p3v>;
223 vqmmc-supply = <®_1p8v>;
224 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
225 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
226 non-removable;
230 pinctrl-names = "default", "state_uhs";
231 pinctrl-0 = <&sd0_pins_default>;
232 pinctrl-1 = <&sd0_pins_uhs>;
234 bus-width = <4>;
235 max-frequency = <50000000>;
236 cap-sd-highspeed;
237 cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
238 vmmc-supply = <®_3p3v>;
239 vqmmc-supply = <®_3p3v>;
240 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
241 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
245 pinctrl-names = "default";
246 pinctrl-0 = <¶llel_nand_pins>;
251 pinctrl-names = "default";
252 pinctrl-0 = <&spi_nor_pins>;
256 compatible = "jedec,spi-nor";
262 pinctrl-names = "default";
263 pinctrl-0 = <&pcie0_pins>;
269 emmc_pins_default: emmc-pins-default {
279 conf-cmd-dat {
283 input-enable;
284 bias-pull-up;
287 conf-clk {
289 bias-pull-down;
293 emmc_pins_uhs: emmc-pins-uhs {
299 conf-cmd-dat {
303 input-enable;
304 drive-strength = <4>;
305 bias-pull-up;
308 conf-clk {
310 drive-strength = <4>;
311 bias-pull-down;
315 eth_pins: eth-pins {
322 i2c1_pins: i2c1-pins {
329 i2c2_pins: i2c2-pins {
336 i2s1_pins: i2s1-pins {
347 drive-strength = <12>;
348 bias-pull-down;
352 irrx_pins: irrx-pins {
359 irtx_pins: irtx-pins {
367 parallel_nand_pins: parallel-nand-pins {
374 pcie0_pins: pcie0-pins {
383 pcie1_pins: pcie1-pins {
392 pmic_bus_pins: pmic-bus-pins {
399 pwm7_pins: pwm1-2-pins {
406 wled_pins: wled-pins {
413 sd0_pins_default: sd0-pins-default {
423 conf-cmd-data {
426 input-enable;
427 drive-strength = <8>;
428 bias-pull-up;
430 conf-clk {
432 drive-strength = <12>;
433 bias-pull-down;
435 conf-cd {
437 bias-pull-up;
441 sd0_pins_uhs: sd0-pins-uhs {
447 conf-cmd-data {
450 input-enable;
451 bias-pull-up;
454 conf-clk {
456 bias-pull-down;
460 /* Serial NAND is shared pin with SPI-NOR */
461 serial_nand_pins: serial-nand-pins {
468 spic0_pins: spic0-pins {
475 spic1_pins: spic1-pins {
482 /* SPI-NOR is shared pin with serial NAND */
483 spi_nor_pins: spi-nor-pins {
490 /* serial NAND is shared pin with SPI-NOR */
491 serial_nand_pins: serial-nand-pins {
498 uart0_pins: uart0-pins {
505 uart2_pins: uart2-pins {
512 watchdog_pins: watchdog-pins {
519 wmac_pins: wmac-pins {
531 pinctrl-names = "default";
532 pinctrl-0 = <&pwm7_pins>;
537 pinctrl-names = "default";
538 pinctrl-0 = <&pmic_bus_pins>;
552 pinctrl-names = "default";
553 pinctrl-0 = <&spic0_pins>;
558 pinctrl-names = "default";
559 pinctrl-0 = <&spic1_pins>;
564 vusb33-supply = <®_3p3v>;
565 vbus-supply = <®_5v>;
574 pinctrl-names = "default";
575 pinctrl-0 = <&uart0_pins>;
580 pinctrl-names = "default";
581 pinctrl-0 = <&uart2_pins>;
586 pinctrl-names = "default";
587 pinctrl-0 = <&watchdog_pins>;
592 pinctrl-names = "default";
593 pinctrl-0 = <&wmac_pins>;