Lines Matching +full:mt6577 +full:- +full:timer
1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mediatek,mt6795-clk.h>
12 #include <dt-bindings/gce/mediatek,mt6795-gce.h>
13 #include <dt-bindings/memory/mt6795-larb-port.h>
14 #include <dt-bindings/pinctrl/mt6795-pinfunc.h>
15 #include <dt-bindings/power/mt6795-power.h>
16 #include <dt-bindings/reset/mediatek,mt6795-resets.h>
20 interrupt-parent = <&sysirq>;
21 #address-cells = <2>;
22 #size-cells = <2>;
42 compatible = "arm,psci-0.2";
47 #address-cells = <1>;
48 #size-cells = <0>;
52 compatible = "arm,cortex-a53";
53 enable-method = "psci";
55 cci-control-port = <&cci_control2>;
56 next-level-cache = <&l2_0>;
61 compatible = "arm,cortex-a53";
62 enable-method = "psci";
64 cci-control-port = <&cci_control2>;
65 i-cache-size = <32768>;
66 i-cache-line-size = <64>;
67 i-cache-sets = <256>;
68 d-cache-size = <32768>;
69 d-cache-line-size = <64>;
70 d-cache-sets = <128>;
71 next-level-cache = <&l2_0>;
76 compatible = "arm,cortex-a53";
77 enable-method = "psci";
79 cci-control-port = <&cci_control2>;
80 i-cache-size = <32768>;
81 i-cache-line-size = <64>;
82 i-cache-sets = <256>;
83 d-cache-size = <32768>;
84 d-cache-line-size = <64>;
85 d-cache-sets = <128>;
86 next-level-cache = <&l2_0>;
91 compatible = "arm,cortex-a53";
92 enable-method = "psci";
94 cci-control-port = <&cci_control2>;
95 i-cache-size = <32768>;
96 i-cache-line-size = <64>;
97 i-cache-sets = <256>;
98 d-cache-size = <32768>;
99 d-cache-line-size = <64>;
100 d-cache-sets = <128>;
101 next-level-cache = <&l2_0>;
106 compatible = "arm,cortex-a53";
107 enable-method = "psci";
109 cci-control-port = <&cci_control1>;
110 i-cache-size = <32768>;
111 i-cache-line-size = <64>;
112 i-cache-sets = <256>;
113 d-cache-size = <32768>;
114 d-cache-line-size = <64>;
115 d-cache-sets = <128>;
116 next-level-cache = <&l2_1>;
121 compatible = "arm,cortex-a53";
122 enable-method = "psci";
124 cci-control-port = <&cci_control1>;
125 i-cache-size = <32768>;
126 i-cache-line-size = <64>;
127 i-cache-sets = <256>;
128 d-cache-size = <32768>;
129 d-cache-line-size = <64>;
130 d-cache-sets = <128>;
131 next-level-cache = <&l2_1>;
136 compatible = "arm,cortex-a53";
137 enable-method = "psci";
139 cci-control-port = <&cci_control1>;
140 i-cache-size = <32768>;
141 i-cache-line-size = <64>;
142 i-cache-sets = <256>;
143 d-cache-size = <32768>;
144 d-cache-line-size = <64>;
145 d-cache-sets = <128>;
146 next-level-cache = <&l2_1>;
151 compatible = "arm,cortex-a53";
152 enable-method = "psci";
154 cci-control-port = <&cci_control1>;
155 i-cache-size = <32768>;
156 i-cache-line-size = <64>;
157 i-cache-sets = <256>;
158 d-cache-size = <32768>;
159 d-cache-line-size = <64>;
160 d-cache-sets = <128>;
161 next-level-cache = <&l2_1>;
164 cpu-map {
202 l2_0: l2-cache0 {
204 cache-level = <2>;
205 cache-size = <1048576>;
206 cache-line-size = <64>;
207 cache-sets = <1024>;
208 cache-unified;
211 l2_1: l2-cache1 {
213 cache-level = <2>;
214 cache-size = <1048576>;
215 cache-line-size = <64>;
216 cache-sets = <1024>;
217 cache-unified;
221 clk26m: oscillator-26m {
222 compatible = "fixed-clock";
223 #clock-cells = <0>;
224 clock-frequency = <26000000>;
225 clock-output-names = "clk26m";
228 clk32k: oscillator-32k {
229 compatible = "fixed-clock";
230 #clock-cells = <0>;
231 clock-frequency = <32000>;
232 clock-output-names = "clk32k";
236 compatible = "fixed-clock";
237 clock-frequency = <13000000>;
238 #clock-cells = <0>;
242 compatible = "arm,cortex-a53-pmu";
247 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
250 timer {
251 compatible = "arm,armv8-timer";
252 interrupt-parent = <&gic>;
264 #address-cells = <2>;
265 #size-cells = <2>;
266 compatible = "simple-bus";
270 compatible = "mediatek,mt6795-topckgen", "syscon";
272 #clock-cells = <1>;
276 compatible = "mediatek,mt6795-infracfg", "syscon";
278 #clock-cells = <1>;
279 #reset-cells = <1>;
283 compatible = "mediatek,mt6795-pericfg", "syscon";
285 #clock-cells = <1>;
286 #reset-cells = <1>;
290 compatible = "syscon", "simple-mfd";
292 #power-domain-cells = <1>;
295 spm: power-controller {
296 compatible = "mediatek,mt6795-power-controller";
297 #address-cells = <1>;
298 #size-cells = <0>;
299 #power-domain-cells = <1>;
302 power-domain@MT6795_POWER_DOMAIN_VDEC {
305 clock-names = "mm";
306 #power-domain-cells = <0>;
308 power-domain@MT6795_POWER_DOMAIN_VENC {
312 clock-names = "mm", "venc";
313 #power-domain-cells = <0>;
315 power-domain@MT6795_POWER_DOMAIN_ISP {
318 clock-names = "mm";
319 #power-domain-cells = <0>;
322 power-domain@MT6795_POWER_DOMAIN_MM {
325 clock-names = "mm";
326 #power-domain-cells = <0>;
330 power-domain@MT6795_POWER_DOMAIN_MJC {
334 clock-names = "mm", "mjc";
335 #power-domain-cells = <0>;
338 power-domain@MT6795_POWER_DOMAIN_AUDIO {
340 #power-domain-cells = <0>;
343 mfg_async: power-domain@MT6795_POWER_DOMAIN_MFG_ASYNC {
346 clock-names = "mfg";
347 #address-cells = <1>;
348 #size-cells = <0>;
349 #power-domain-cells = <1>;
351 power-domain@MT6795_POWER_DOMAIN_MFG_2D {
353 #address-cells = <1>;
354 #size-cells = <0>;
355 #power-domain-cells = <1>;
357 power-domain@MT6795_POWER_DOMAIN_MFG {
359 #power-domain-cells = <0>;
368 compatible = "mediatek,mt6795-pinctrl";
370 reg-names = "base", "eint";
373 gpio-controller;
374 #gpio-cells = <2>;
375 gpio-ranges = <&pio 0 0 196>;
376 interrupt-controller;
377 #interrupt-cells = <2>;
381 compatible = "mediatek,mt6795-wdt";
384 #reset-cells = <1>;
385 timeout-sec = <20>;
388 timer: timer@10008000 { label
389 compatible = "mediatek,mt6795-timer",
390 "mediatek,mt6577-timer";
397 compatible = "mediatek,mt6795-pwrap";
399 reg-names = "pwrap";
402 reset-names = "pwrap";
404 clock-names = "spi", "wrap";
407 sysirq: intpol-controller@10200620 {
408 compatible = "mediatek,mt6795-sysirq",
409 "mediatek,mt6577-sysirq";
410 interrupt-controller;
411 #interrupt-cells = <3>;
412 interrupt-parent = <&gic>;
416 systimer: timer@10200670 {
417 compatible = "mediatek,mt6795-systimer";
421 clock-names = "clk13m";
425 compatible = "mediatek,mt6795-m4u";
428 clock-names = "bclk";
431 power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
432 #iommu-cells = <1>;
436 compatible = "mediatek,mt6795-apmixedsys", "syscon";
438 #clock-cells = <1>;
441 fhctl: clock-controller@10209f00 {
442 compatible = "mediatek,mt6795-fhctl";
448 compatible = "mediatek,mt6795-gce", "mediatek,mt8173-gce";
452 clock-names = "gce";
453 #mbox-cells = <2>;
456 mipi_tx0: dsi-phy@10215000 {
457 compatible = "mediatek,mt8173-mipi-tx";
460 clock-output-names = "mipi_tx0_pll";
461 #clock-cells = <0>;
462 #phy-cells = <0>;
466 mipi_tx1: dsi-phy@10216000 {
467 compatible = "mediatek,mt8173-mipi-tx";
470 clock-output-names = "mipi_tx1_pll";
471 #clock-cells = <0>;
472 #phy-cells = <0>;
476 gic: interrupt-controller@10221000 {
477 compatible = "arm,gic-400";
478 #interrupt-cells = <3>;
479 interrupt-parent = <&gic>;
480 interrupt-controller;
490 compatible = "arm,cci-400";
491 #address-cells = <1>;
492 #size-cells = <1>;
496 cci_control0: slave-if@1000 {
497 compatible = "arm,cci-400-ctrl-if";
498 interface-type = "ace-lite";
502 cci_control1: slave-if@4000 {
503 compatible = "arm,cci-400-ctrl-if";
504 interface-type = "ace";
508 cci_control2: slave-if@5000 {
509 compatible = "arm,cci-400-ctrl-if";
510 interface-type = "ace";
515 compatible = "arm,cci-400-pmu,r1";
526 compatible = "mediatek,mt6795-uart",
527 "mediatek,mt6577-uart";
531 clock-names = "baud", "bus";
533 dma-names = "tx", "rx";
538 compatible = "mediatek,mt6795-uart",
539 "mediatek,mt6577-uart";
543 clock-names = "baud", "bus";
545 dma-names = "tx", "rx";
549 apdma: dma-controller@11000380 {
550 compatible = "mediatek,mt6795-uart-dma",
551 "mediatek,mt6577-uart-dma";
568 dma-requests = <8>;
570 clock-names = "apdma";
571 mediatek,dma-33bits;
572 #dma-cells = <1>;
576 compatible = "mediatek,mt6795-uart",
577 "mediatek,mt6577-uart";
581 clock-names = "baud", "bus";
583 dma-names = "tx", "rx";
588 compatible = "mediatek,mt6795-uart",
589 "mediatek,mt6577-uart";
593 clock-names = "baud", "bus";
595 dma-names = "tx", "rx";
600 compatible = "mediatek,mt6795-pwm";
602 #pwm-cells = <2>;
613 clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
619 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
622 clock-div = <16>;
624 clock-names = "main", "dma";
625 #address-cells = <1>;
626 #size-cells = <0>;
631 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
634 clock-div = <16>;
636 clock-names = "main", "dma";
637 #address-cells = <1>;
638 #size-cells = <0>;
643 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
646 clock-div = <16>;
648 clock-names = "main", "dma";
649 #address-cells = <1>;
650 #size-cells = <0>;
655 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
658 clock-div = <16>;
660 clock-names = "main", "dma";
661 #address-cells = <1>;
662 #size-cells = <0>;
667 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
670 clock-div = <16>;
672 clock-names = "main", "dma";
673 #address-cells = <1>;
674 #size-cells = <0>;
679 compatible = "mediatek,mt6795-mmc";
685 clock-names = "source", "hclk", "source_cg";
690 compatible = "mediatek,mt6795-mmc";
695 clock-names = "source", "hclk";
700 compatible = "mediatek,mt6795-mmc";
705 clock-names = "source", "hclk";
710 compatible = "mediatek,mt6795-mmc";
715 clock-names = "source", "hclk";
720 compatible = "mediatek,mt6795-mmsys", "syscon";
722 power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
723 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
724 assigned-clock-rates = <400000000>;
725 #clock-cells = <1>;
726 #reset-cells = <1>;
729 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
733 compatible = "mediatek,mt6795-disp-ovl", "mediatek,mt8173-disp-ovl";
736 power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
739 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
743 compatible = "mediatek,mt6795-disp-ovl", "mediatek,mt8173-disp-ovl";
746 power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
749 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
753 compatible = "mediatek,mt6795-disp-rdma", "mediatek,mt8173-disp-rdma";
756 power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
759 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
763 compatible = "mediatek,mt6795-disp-rdma", "mediatek,mt8173-disp-rdma";
766 power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
769 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
773 compatible = "mediatek,mt6795-disp-rdma", "mediatek,mt8173-disp-rdma";
776 power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
779 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
783 compatible = "mediatek,mt6795-disp-wdma", "mediatek,mt8173-disp-wdma";
786 power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
789 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
793 compatible = "mediatek,mt6795-disp-wdma", "mediatek,mt8173-disp-wdma";
796 power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
799 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
803 compatible = "mediatek,mt6795-disp-color", "mediatek,mt8173-disp-color";
806 power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
808 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
812 compatible = "mediatek,mt6795-disp-color", "mediatek,mt8173-disp-color";
815 power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
817 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
821 compatible = "mediatek,mt6795-disp-aal", "mediatek,mt8173-disp-aal";
824 power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
826 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
830 compatible = "mediatek,mt6795-disp-gamma", "mediatek,mt8173-disp-gamma";
833 power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
835 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
839 compatible = "mediatek,mt6795-disp-merge", "mediatek,mt8173-disp-merge";
841 power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
846 compatible = "mediatek,mt6795-disp-split", "mediatek,mt8173-disp-split";
848 power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
853 compatible = "mediatek,mt6795-disp-split", "mediatek,mt8173-disp-split";
855 power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
860 compatible = "mediatek,mt6795-disp-ufoe", "mediatek,mt8173-disp-ufoe";
863 power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
865 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>;
869 compatible = "mediatek,mt6795-dsi", "mediatek,mt8173-dsi";
872 power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
876 clock-names = "engine", "digital", "hs";
878 phy-names = "dphy";
883 compatible = "mediatek,mt6795-dsi", "mediatek,mt8173-dsi";
886 power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
890 clock-names = "engine", "digital", "hs";
892 phy-names = "dphy";
897 compatible = "mediatek,mt6795-dpi", "mediatek,mt8183-dpi";
900 power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
904 clock-names = "pixel", "engine", "pll";
909 compatible = "mediatek,mt6795-disp-pwm", "mediatek,mt8173-disp-pwm";
911 #pwm-cells = <2>;
913 clock-names = "main", "mm";
918 compatible = "mediatek,mt6795-disp-pwm", "mediatek,mt8173-disp-pwm";
920 #pwm-cells = <2>;
922 clock-names = "main", "mm";
927 compatible = "mediatek,mt8173-disp-mutex";
930 power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
932 mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
934 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>;
938 compatible = "mediatek,mt6795-smi-larb";
941 clock-names = "apb", "smi";
943 mediatek,larb-id = <0>;
944 power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
948 compatible = "mediatek,mt6795-smi-common";
950 power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
952 clock-names = "apb", "smi";
956 compatible = "mediatek,mt6795-disp-od", "mediatek,mt8173-disp-od";
959 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>;
963 compatible = "mediatek,mt6795-smi-larb";
966 clock-names = "apb", "smi";
968 mediatek,larb-id = <2>;
969 power-domains = <&spm MT6795_POWER_DOMAIN_ISP>;
972 vdecsys: clock-controller@16000000 {
973 compatible = "mediatek,mt6795-vdecsys";
975 #clock-cells = <1>;
979 compatible = "mediatek,mt6795-smi-larb";
982 mediatek,larb-id = <1>;
984 clock-names = "apb", "smi";
985 power-domains = <&spm MT6795_POWER_DOMAIN_VDEC>;
988 vencsys: clock-controller@18000000 {
989 compatible = "mediatek,mt6795-vencsys";
991 #clock-cells = <1>;
995 compatible = "mediatek,mt6795-smi-larb";
998 clock-names = "apb", "smi";
1000 mediatek,larb-id = <3>;
1001 power-domains = <&spm MT6795_POWER_DOMAIN_VENC>;