Lines Matching +full:0 +full:x10212000
48 #size-cells = <0>;
50 cpu0: cpu@0 {
54 reg = <0x000>;
63 reg = <0x001>;
78 reg = <0x002>;
93 reg = <0x003>;
108 reg = <0x100>;
123 reg = <0x101>;
138 reg = <0x102>;
153 reg = <0x103>;
223 #clock-cells = <0>;
230 #clock-cells = <0>;
238 #clock-cells = <0>;
271 reg = <0 0x10000000 0 0x1000>;
277 reg = <0 0x10001000 0 0x1000>;
284 reg = <0 0x10003000 0 0x1000>;
291 reg = <0 0x10006000 0 0x1000>;
298 #size-cells = <0>;
306 #power-domain-cells = <0>;
313 #power-domain-cells = <0>;
319 #power-domain-cells = <0>;
326 #power-domain-cells = <0>;
335 #power-domain-cells = <0>;
340 #power-domain-cells = <0>;
348 #size-cells = <0>;
354 #size-cells = <0>;
359 #power-domain-cells = <0>;
369 reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
375 gpio-ranges = <&pio 0 0 196>;
382 reg = <0 0x10007000 0 0x100>;
391 reg = <0 0x10008000 0 0x1000>;
398 reg = <0 0x1000d000 0 0x1000>;
413 reg = <0 0x10200620 0 0x20>;
418 reg = <0 0x10200670 0 0x10>;
426 reg = <0 0x10205000 0 0x1000>;
437 reg = <0 0x10209000 0 0x1000>;
443 reg = <0 0x10209f00 0 0x100>;
449 reg = <0 0x10212000 0 0x1000>;
458 reg = <0 0x10215000 0 0x1000>;
461 #clock-cells = <0>;
462 #phy-cells = <0>;
468 reg = <0 0x10216000 0 0x1000>;
471 #clock-cells = <0>;
472 #phy-cells = <0>;
481 reg = <0 0x10221000 0 0x1000>,
482 <0 0x10222000 0 0x2000>,
483 <0 0x10224000 0 0x2000>,
484 <0 0x10226000 0 0x2000>;
493 reg = <0 0x10390000 0 0x1000>;
494 ranges = <0 0 0x10390000 0x10000>;
499 reg = <0x1000 0x1000>;
505 reg = <0x4000 0x1000>;
511 reg = <0x5000 0x1000>;
516 reg = <0x9000 0x5000>;
528 reg = <0 0x11002000 0 0x400>;
532 dmas = <&apdma 0>, <&apdma 1>;
540 reg = <0 0x11003000 0 0x400>;
552 reg = <0 0x11000380 0 0x60>,
553 <0 0x11000400 0 0x60>,
554 <0 0x11000480 0 0x60>,
555 <0 0x11000500 0 0x60>,
556 <0 0x11000580 0 0x60>,
557 <0 0x11000600 0 0x60>,
558 <0 0x11000680 0 0x60>,
559 <0 0x11000700 0 0x60>;
578 reg = <0 0x11004000 0 0x400>;
590 reg = <0 0x11005000 0 0x400>;
601 reg = <0 0x11006000 0 0x1000>;
620 reg = <0 0x11007000 0 0x70>, <0 0x11000100 0 0x80>;
626 #size-cells = <0>;
632 reg = <0 0x11008000 0 0x70>, <0 0x11000180 0 0x80>;
638 #size-cells = <0>;
644 reg = <0 0x11009000 0 0x70>, <0 0x11000200 0 0x80>;
650 #size-cells = <0>;
656 reg = <0 0x11010000 0 0x70>, <0 0x11000280 0 0x80>;
662 #size-cells = <0>;
668 reg = <0 0x11011000 0 0x70>, <0 0x11000300 0 0x80>;
674 #size-cells = <0>;
680 reg = <0 0x11230000 0 0x1000>;
691 reg = <0 0x11240000 0 0x1000>;
701 reg = <0 0x11250000 0 0x1000>;
711 reg = <0 0x11260000 0 0x1000>;
721 reg = <0 0x14000000 0 0x1000>;
727 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
729 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
734 reg = <0 0x1400c000 0 0x1000>;
739 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
744 reg = <0 0x1400d000 0 0x1000>;
749 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
754 reg = <0 0x1400e000 0 0x1000>;
759 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
764 reg = <0 0x1400f000 0 0x1000>;
769 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
774 reg = <0 0x14010000 0 0x1000>;
779 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
784 reg = <0 0x14011000 0 0x1000>;
789 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
794 reg = <0 0x14012000 0 0x1000>;
799 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
804 reg = <0 0x14013000 0 0x1000>;
808 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
813 reg = <0 0x14014000 0 0x1000>;
817 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
822 reg = <0 0x14015000 0 0x1000>;
826 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
831 reg = <0 0x14016000 0 0x1000>;
835 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
840 reg = <0 0x14017000 0 0x1000>;
847 reg = <0 0x14018000 0 0x1000>;
854 reg = <0 0x14019000 0 0x1000>;
861 reg = <0 0x1401a000 0 0x1000>;
865 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>;
870 reg = <0 0x1401b000 0 0x1000>;
884 reg = <0 0x1401c000 0 0x1000>;
898 reg = <0 0x1401d000 0 0x1000>;
910 reg = <0 0x1401e000 0 0x1000>;
919 reg = <0 0x1401f000 0 0x1000>;
928 reg = <0 0x14020000 0 0x1000>;
934 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>;
939 reg = <0 0x14021000 0 0x1000>;
943 mediatek,larb-id = <0>;
949 reg = <0 0x14022000 0 0x1000>;
957 reg = <0 0x14023000 0 0x1000>;
959 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>;
964 reg = <0 0x15001000 0 0x1000>;
974 reg = <0 0x16000000 0 0x1000>;
980 reg = <0 0x16010000 0 0x1000>;
990 reg = <0 0x18000000 0 0x1000>;
996 reg = <0 0x18001000 0 0x1000>;