Lines Matching +full:jpgdec +full:- +full:smi
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt2712-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/memory/mt2712-larb-port.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt2712-power.h>
14 #include "mt2712-pinfunc.h"
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
20 #size-cells = <2>;
22 cluster0_opp: opp-table-0 {
23 compatible = "operating-points-v2";
24 opp-shared;
26 opp-hz = /bits/ 64 <598000000>;
27 opp-microvolt = <1000000>;
30 opp-hz = /bits/ 64 <702000000>;
31 opp-microvolt = <1000000>;
34 opp-hz = /bits/ 64 <793000000>;
35 opp-microvolt = <1000000>;
39 cluster1_opp: opp-table-1 {
40 compatible = "operating-points-v2";
41 opp-shared;
43 opp-hz = /bits/ 64 <598000000>;
44 opp-microvolt = <1000000>;
47 opp-hz = /bits/ 64 <702000000>;
48 opp-microvolt = <1000000>;
51 opp-hz = /bits/ 64 <793000000>;
52 opp-microvolt = <1000000>;
55 opp-hz = /bits/ 64 <897000000>;
56 opp-microvolt = <1000000>;
59 opp-hz = /bits/ 64 <1001000000>;
60 opp-microvolt = <1000000>;
65 #address-cells = <1>;
66 #size-cells = <0>;
68 cpu-map {
87 compatible = "arm,cortex-a35";
91 clock-names = "cpu", "intermediate";
92 proc-supply = <&cpus_fixed_vproc0>;
93 operating-points-v2 = <&cluster0_opp>;
94 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
99 compatible = "arm,cortex-a35";
101 enable-method = "psci";
104 clock-names = "cpu", "intermediate";
105 proc-supply = <&cpus_fixed_vproc0>;
106 operating-points-v2 = <&cluster0_opp>;
107 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
112 compatible = "arm,cortex-a72";
114 enable-method = "psci";
117 clock-names = "cpu", "intermediate";
118 proc-supply = <&cpus_fixed_vproc1>;
119 operating-points-v2 = <&cluster1_opp>;
120 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
123 idle-states {
124 entry-method = "psci";
126 CPU_SLEEP_0: cpu-sleep-0 {
127 compatible = "arm,idle-state";
128 local-timer-stop;
129 entry-latency-us = <100>;
130 exit-latency-us = <80>;
131 min-residency-us = <2000>;
132 arm,psci-suspend-param = <0x0010000>;
135 CLUSTER_SLEEP_0: cluster-sleep-0 {
136 compatible = "arm,idle-state";
137 local-timer-stop;
138 entry-latency-us = <350>;
139 exit-latency-us = <80>;
140 min-residency-us = <3000>;
141 arm,psci-suspend-param = <0x1010000>;
147 compatible = "arm,psci-0.2";
152 compatible = "fixed-clock";
153 clock-frequency = <26000000>;
154 #clock-cells = <0>;
158 compatible = "fixed-clock";
159 clock-frequency = <26000000>;
160 #clock-cells = <0>;
163 clk26m: oscillator-26m {
164 compatible = "fixed-clock";
165 #clock-cells = <0>;
166 clock-frequency = <26000000>;
167 clock-output-names = "clk26m";
170 clk32k: oscillator-32k {
171 compatible = "fixed-clock";
172 #clock-cells = <0>;
173 clock-frequency = <32768>;
174 clock-output-names = "clk32k";
177 clkfpc: oscillator-50m {
178 compatible = "fixed-clock";
179 #clock-cells = <0>;
180 clock-frequency = <50000000>;
181 clock-output-names = "clkfpc";
184 clkaud_ext_i_0: oscillator-aud0 {
185 compatible = "fixed-clock";
186 #clock-cells = <0>;
187 clock-frequency = <6500000>;
188 clock-output-names = "clkaud_ext_i_0";
191 clkaud_ext_i_1: oscillator-aud1 {
192 compatible = "fixed-clock";
193 #clock-cells = <0>;
194 clock-frequency = <196608000>;
195 clock-output-names = "clkaud_ext_i_1";
198 clkaud_ext_i_2: oscillator-aud2 {
199 compatible = "fixed-clock";
200 #clock-cells = <0>;
201 clock-frequency = <180633600>;
202 clock-output-names = "clkaud_ext_i_2";
205 clki2si0_mck_i: oscillator-i2s0 {
206 compatible = "fixed-clock";
207 #clock-cells = <0>;
208 clock-frequency = <30000000>;
209 clock-output-names = "clki2si0_mck_i";
212 clki2si1_mck_i: oscillator-i2s1 {
213 compatible = "fixed-clock";
214 #clock-cells = <0>;
215 clock-frequency = <30000000>;
216 clock-output-names = "clki2si1_mck_i";
219 clki2si2_mck_i: oscillator-i2s2 {
220 compatible = "fixed-clock";
221 #clock-cells = <0>;
222 clock-frequency = <30000000>;
223 clock-output-names = "clki2si2_mck_i";
226 clktdmin_mclk_i: oscillator-mclk {
227 compatible = "fixed-clock";
228 #clock-cells = <0>;
229 clock-frequency = <30000000>;
230 clock-output-names = "clktdmin_mclk_i";
234 compatible = "arm,armv8-timer";
235 interrupt-parent = <&gic>;
247 compatible = "mediatek,mt2712-topckgen", "syscon";
249 #clock-cells = <1>;
252 infracfg: clock-controller@10001000 {
253 compatible = "mediatek,mt2712-infracfg", "syscon";
255 #clock-cells = <1>;
256 #reset-cells = <1>;
260 compatible = "mediatek,mt2712-pericfg", "syscon";
262 #clock-cells = <1>;
266 compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon";
271 compatible = "mediatek,mt2712-pinctrl";
273 mediatek,pctl-regmap = <&syscfg_pctl_a>;
274 gpio-controller;
275 #gpio-cells = <2>;
276 interrupt-controller;
277 #interrupt-cells = <2>;
281 scpsys: power-controller@10006000 {
282 compatible = "mediatek,mt2712-scpsys", "syscon";
283 #power-domain-cells = <1>;
291 clock-names = "mm", "mfg", "venc",
292 "jpgdec", "audio", "vdec";
297 compatible = "mediatek,mt2712-uart",
298 "mediatek,mt6577-uart";
302 clock-names = "baud", "bus";
305 dma-names = "tx", "rx";
310 compatible = "mediatek,mt2712-rtc";
316 compatible = "mediatek,mt2712-spi-slave";
320 clock-names = "spi";
321 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
322 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
327 compatible = "mediatek,mt2712-m4u";
331 clock-names = "bclk";
335 #iommu-cells = <1>;
339 compatible = "mediatek,mt2712-apmixedsys", "syscon";
341 #clock-cells = <1>;
345 compatible = "mediatek,mt2712-m4u";
349 clock-names = "bclk";
352 #iommu-cells = <1>;
356 compatible = "mediatek,mt2712-mcucfg", "syscon";
358 #clock-cells = <1>;
361 sysirq: interrupt-controller@10220a80 {
362 compatible = "mediatek,mt2712-sysirq",
363 "mediatek,mt6577-sysirq";
364 interrupt-controller;
365 #interrupt-cells = <3>;
366 interrupt-parent = <&gic>;
370 gic: interrupt-controller@10510000 {
371 compatible = "arm,gic-400";
372 #interrupt-cells = <3>;
373 interrupt-parent = <&gic>;
374 interrupt-controller;
383 apdma: dma-controller@11000400 {
384 compatible = "mediatek,mt2712-uart-dma",
385 "mediatek,mt6577-uart-dma";
410 dma-requests = <12>;
412 clock-names = "apdma";
413 #dma-cells = <1>;
417 compatible = "mediatek,mt2712-auxadc";
420 clock-names = "main";
421 #io-channel-cells = <1>;
426 compatible = "mediatek,mt2712-uart",
427 "mediatek,mt6577-uart";
431 clock-names = "baud", "bus";
434 dma-names = "tx", "rx";
439 compatible = "mediatek,mt2712-uart",
440 "mediatek,mt6577-uart";
444 clock-names = "baud", "bus";
447 dma-names = "tx", "rx";
452 compatible = "mediatek,mt2712-uart",
453 "mediatek,mt6577-uart";
457 clock-names = "baud", "bus";
460 dma-names = "tx", "rx";
465 compatible = "mediatek,mt2712-uart",
466 "mediatek,mt6577-uart";
470 clock-names = "baud", "bus";
473 dma-names = "tx", "rx";
478 compatible = "mediatek,mt2712-pwm";
480 #pwm-cells = <2>;
492 clock-names = "top",
506 compatible = "mediatek,mt2712-i2c";
510 clock-div = <4>;
513 clock-names = "main",
515 #address-cells = <1>;
516 #size-cells = <0>;
521 compatible = "mediatek,mt2712-i2c";
525 clock-div = <4>;
528 clock-names = "main",
530 #address-cells = <1>;
531 #size-cells = <0>;
536 compatible = "mediatek,mt2712-i2c";
540 clock-div = <4>;
543 clock-names = "main",
545 #address-cells = <1>;
546 #size-cells = <0>;
551 compatible = "mediatek,mt2712-spi";
552 #address-cells = <1>;
553 #size-cells = <0>;
559 clock-names = "parent-clk", "sel-clk", "spi-clk";
563 nandc: nand-controller@1100e000 {
564 compatible = "mediatek,mt2712-nfc";
568 clock-names = "nfi_clk", "pad_clk";
569 ecc-engine = <&bch>;
570 #address-cells = <1>;
571 #size-cells = <0>;
576 compatible = "mediatek,mt2712-ecc";
580 clock-names = "nfiecc_clk";
585 compatible = "mediatek,mt2712-i2c";
589 clock-div = <4>;
592 clock-names = "main",
594 #address-cells = <1>;
595 #size-cells = <0>;
600 compatible = "mediatek,mt2712-i2c";
604 clock-div = <4>;
607 clock-names = "main",
609 #address-cells = <1>;
610 #size-cells = <0>;
615 compatible = "mediatek,mt2712-i2c";
619 clock-div = <4>;
622 clock-names = "main",
624 #address-cells = <1>;
625 #size-cells = <0>;
630 compatible = "mediatek,mt2712-spi";
631 #address-cells = <1>;
632 #size-cells = <0>;
638 clock-names = "parent-clk", "sel-clk", "spi-clk";
643 compatible = "mediatek,mt2712-spi";
644 #address-cells = <1>;
645 #size-cells = <0>;
651 clock-names = "parent-clk", "sel-clk", "spi-clk";
656 compatible = "mediatek,mt2712-spi";
657 #address-cells = <1>;
658 #size-cells = <0>;
664 clock-names = "parent-clk", "sel-clk", "spi-clk";
669 compatible = "mediatek,mt2712-spi";
670 #address-cells = <1>;
671 #size-cells = <0>;
677 clock-names = "parent-clk", "sel-clk", "spi-clk";
682 compatible = "mediatek,mt2712-uart",
683 "mediatek,mt6577-uart";
687 clock-names = "baud", "bus";
690 dma-names = "tx", "rx";
694 stmmac_axi_setup: stmmac-axi-config {
700 mtl_rx_setup: rx-queues-config {
701 snps,rx-queues-to-use = <1>;
702 snps,rx-sched-sp;
704 snps,dcb-algorithm;
705 snps,map-to-dma-channel = <0x0>;
710 mtl_tx_setup: tx-queues-config {
711 snps,tx-queues-to-use = <3>;
712 snps,tx-sched-wrr;
715 snps,dcb-algorithm;
720 snps,dcb-algorithm;
725 snps,dcb-algorithm;
731 compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a";
734 interrupt-names = "macirq";
735 mac-address = [00 55 7b b5 7d f7];
736 clock-names = "axi",
746 assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
749 assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
752 power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
754 snps,axi-config = <&stmmac_axi_setup>;
755 snps,mtl-rx-config = <&mtl_rx_setup>;
756 snps,mtl-tx-config = <&mtl_tx_setup>;
759 snps,clk-csr = <0>;
764 compatible = "mediatek,mt2712-mmc";
771 clock-names = "source", "hclk", "source_cg", "bus_clk";
776 compatible = "mediatek,mt2712-mmc";
782 clock-names = "source", "hclk", "source_cg";
787 compatible = "mediatek,mt2712-mmc";
793 clock-names = "source", "hclk", "source_cg";
798 compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3";
801 reg-names = "mac", "ippc";
805 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>;
807 clock-names = "sys_ck";
808 mediatek,syscon-wakeup = <&pericfg 0x510 2>;
809 #address-cells = <2>;
810 #size-cells = <2>;
815 compatible = "mediatek,mt2712-xhci",
816 "mediatek,mtk-xhci";
818 reg-names = "mac";
820 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>;
822 clock-names = "sys_ck", "ref_ck";
827 u3phy0: t-phy@11290000 {
828 compatible = "mediatek,mt2712-tphy",
829 "mediatek,generic-tphy-v2";
830 #address-cells = <1>;
831 #size-cells = <1>;
835 u2port0: usb-phy@0 {
838 clock-names = "ref";
839 #phy-cells = <1>;
843 u2port1: usb-phy@8000 {
846 clock-names = "ref";
847 #phy-cells = <1>;
851 u3port0: usb-phy@8700 {
854 clock-names = "ref";
855 #phy-cells = <1>;
861 compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3";
864 reg-names = "mac", "ippc";
869 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>;
871 clock-names = "sys_ck";
872 mediatek,syscon-wakeup = <&pericfg 0x514 2>;
873 #address-cells = <2>;
874 #size-cells = <2>;
879 compatible = "mediatek,mt2712-xhci",
880 "mediatek,mtk-xhci";
882 reg-names = "mac";
884 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>;
886 clock-names = "sys_ck", "ref_ck";
891 u3phy1: t-phy@112e0000 {
892 compatible = "mediatek,mt2712-tphy",
893 "mediatek,generic-tphy-v2";
894 #address-cells = <1>;
895 #size-cells = <1>;
899 u2port2: usb-phy@0 {
902 clock-names = "ref";
903 #phy-cells = <1>;
907 u2port3: usb-phy@8000 {
910 clock-names = "ref";
911 #phy-cells = <1>;
915 u3port1: usb-phy@8700 {
918 clock-names = "ref";
919 #phy-cells = <1>;
925 compatible = "mediatek,mt2712-pcie";
928 reg-names = "port1";
929 linux,pci-domain = <1>;
930 #address-cells = <3>;
931 #size-cells = <2>;
933 interrupt-names = "pcie_irq";
936 clock-names = "sys_ck1", "ahb_ck1";
938 phy-names = "pcie-phy1";
939 bus-range = <0x00 0xff>;
943 #interrupt-cells = <1>;
944 interrupt-map-mask = <0 0 0 7>;
945 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
949 pcie_intc1: interrupt-controller {
950 interrupt-controller;
951 #address-cells = <0>;
952 #interrupt-cells = <1>;
957 compatible = "mediatek,mt2712-pcie";
960 reg-names = "port0";
961 linux,pci-domain = <0>;
962 #address-cells = <3>;
963 #size-cells = <2>;
965 interrupt-names = "pcie_irq";
968 clock-names = "sys_ck0", "ahb_ck0";
970 phy-names = "pcie-phy0";
971 bus-range = <0x00 0xff>;
975 #interrupt-cells = <1>;
976 interrupt-map-mask = <0 0 0 7>;
977 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
981 pcie_intc0: interrupt-controller {
982 interrupt-controller;
983 #address-cells = <0>;
984 #interrupt-cells = <1>;
989 compatible = "mediatek,mt2712-mfgcfg", "syscon";
991 #clock-cells = <1>;
995 compatible = "mediatek,mt2712-mmsys", "syscon";
997 #clock-cells = <1>;
1001 compatible = "mediatek,mt2712-smi-larb";
1003 mediatek,smi = <&smi_common0>;
1004 mediatek,larb-id = <0>;
1005 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1008 clock-names = "apb", "smi";
1011 smi_common0: smi@14022000 {
1012 compatible = "mediatek,mt2712-smi-common";
1014 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1017 clock-names = "apb", "smi";
1021 compatible = "mediatek,mt2712-smi-larb";
1023 mediatek,smi = <&smi_common1>;
1024 mediatek,larb-id = <4>;
1025 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1028 clock-names = "apb", "smi";
1032 compatible = "mediatek,mt2712-smi-larb";
1034 mediatek,smi = <&smi_common1>;
1035 mediatek,larb-id = <5>;
1036 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1039 clock-names = "apb", "smi";
1042 smi_common1: smi@14031000 {
1043 compatible = "mediatek,mt2712-smi-common";
1045 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1048 clock-names = "apb", "smi";
1052 compatible = "mediatek,mt2712-smi-larb";
1054 mediatek,smi = <&smi_common1>;
1055 mediatek,larb-id = <7>;
1056 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1059 clock-names = "apb", "smi";
1063 compatible = "mediatek,mt2712-imgsys", "syscon";
1065 #clock-cells = <1>;
1069 compatible = "mediatek,mt2712-smi-larb";
1071 mediatek,smi = <&smi_common0>;
1072 mediatek,larb-id = <2>;
1073 power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>;
1076 clock-names = "apb", "smi";
1080 compatible = "mediatek,mt2712-bdpsys", "syscon";
1082 #clock-cells = <1>;
1086 compatible = "mediatek,mt2712-vdecsys", "syscon";
1088 #clock-cells = <1>;
1092 compatible = "mediatek,mt2712-smi-larb";
1094 mediatek,smi = <&smi_common0>;
1095 mediatek,larb-id = <1>;
1096 power-domains = <&scpsys MT2712_POWER_DOMAIN_VDEC>;
1099 clock-names = "apb", "smi";
1103 compatible = "mediatek,mt2712-vencsys", "syscon";
1105 #clock-cells = <1>;
1109 compatible = "mediatek,mt2712-smi-larb";
1111 mediatek,smi = <&smi_common0>;
1112 mediatek,larb-id = <3>;
1113 power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>;
1116 clock-names = "apb", "smi";
1120 compatible = "mediatek,mt2712-smi-larb";
1122 mediatek,smi = <&smi_common0>;
1123 mediatek,larb-id = <6>;
1124 power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>;
1127 clock-names = "apb", "smi";
1131 compatible = "mediatek,mt2712-jpgdecsys", "syscon";
1133 #clock-cells = <1>;