Lines Matching +full:0 +full:x1010000
22 cluster0_opp: opp-table-0 {
66 #size-cells = <0>;
85 cpu0: cpu@0 {
88 reg = <0x000>;
100 reg = <0x001>;
113 reg = <0x200>;
126 CPU_SLEEP_0: cpu-sleep-0 {
132 arm,psci-suspend-param = <0x0010000>;
135 CLUSTER_SLEEP_0: cluster-sleep-0 {
141 arm,psci-suspend-param = <0x1010000>;
154 #clock-cells = <0>;
160 #clock-cells = <0>;
165 #clock-cells = <0>;
172 #clock-cells = <0>;
179 #clock-cells = <0>;
186 #clock-cells = <0>;
193 #clock-cells = <0>;
200 #clock-cells = <0>;
207 #clock-cells = <0>;
214 #clock-cells = <0>;
221 #clock-cells = <0>;
228 #clock-cells = <0>;
237 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
239 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
241 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
243 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
248 reg = <0 0x10000000 0 0x1000>;
254 reg = <0 0x10001000 0 0x1000>;
261 reg = <0 0x10003000 0 0x1000>;
267 reg = <0 0x10005000 0 0x1000>;
272 reg = <0 0x1000b000 0 0x1000>;
284 reg = <0 0x10006000 0 0x1000>;
299 reg = <0 0x1000f000 0 0x400>;
311 reg = <0 0x10011000 0 0x1000>;
317 reg = <0 0x10013000 0 0x100>;
328 reg = <0 0x10205000 0 0x1000>;
340 reg = <0 0x10209000 0 0x1000>;
346 reg = <0 0x1020a000 0 0x1000>;
357 reg = <0 0x10220000 0 0x1000>;
367 reg = <0 0x10220a80 0 0x40>;
375 reg = <0 0x10510000 0 0x10000>,
376 <0 0x10520000 0 0x20000>,
377 <0 0x10540000 0 0x20000>,
378 <0 0x10560000 0 0x20000>;
380 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;
386 reg = <0 0x11000400 0 0x80>,
387 <0 0x11000480 0 0x80>,
388 <0 0x11000500 0 0x80>,
389 <0 0x11000580 0 0x80>,
390 <0 0x11000600 0 0x80>,
391 <0 0x11000680 0 0x80>,
392 <0 0x11000700 0 0x80>,
393 <0 0x11000780 0 0x80>,
394 <0 0x11000800 0 0x80>,
395 <0 0x11000880 0 0x80>,
396 <0 0x11000900 0 0x80>,
397 <0 0x11000980 0 0x80>;
418 reg = <0 0x11001000 0 0x1000>;
428 reg = <0 0x11002000 0 0x400>;
432 dmas = <&apdma 0
441 reg = <0 0x11003000 0 0x400>;
454 reg = <0 0x11004000 0 0x400>;
467 reg = <0 0x11005000 0 0x400>;
479 reg = <0 0x11006000 0 0x1000>;
507 reg = <0 0x11007000 0 0x90>,
508 <0 0x11000180 0 0x80>;
516 #size-cells = <0>;
522 reg = <0 0x11008000 0 0x90>,
523 <0 0x11000200 0 0x80>;
531 #size-cells = <0>;
537 reg = <0 0x11009000 0 0x90>,
538 <0 0x11000280 0 0x80>;
546 #size-cells = <0>;
553 #size-cells = <0>;
554 reg = <0 0x1100a000 0 0x100>;
565 reg = <0 0x1100e000 0 0x1000>;
571 #size-cells = <0>;
577 reg = <0 0x1100f000 0 0x1000>;
586 reg = <0 0x11010000 0 0x90>,
587 <0 0x11000300 0 0x80>;
595 #size-cells = <0>;
601 reg = <0 0x11011000 0 0x90>,
602 <0 0x11000380 0 0x80>;
610 #size-cells = <0>;
616 reg = <0 0x11013000 0 0x90>,
617 <0 0x11000100 0 0x80>;
625 #size-cells = <0>;
632 #size-cells = <0>;
633 reg = <0 0x11015000 0 0x100>;
645 #size-cells = <0>;
646 reg = <0 0x11016000 0 0x100>;
658 #size-cells = <0>;
659 reg = <0 0x10012000 0 0x100>;
671 #size-cells = <0>;
672 reg = <0 0x11018000 0 0x100>;
684 reg = <0 0x11019000 0 0x400>;
695 snps,wr_osr_lmt = <0x7>;
696 snps,rd_osr_lmt = <0x7>;
697 snps,blen = <0 0 0 0 16 8 4>;
705 snps,map-to-dma-channel = <0x0>;
706 snps,priority = <0x0>;
714 snps,weight = <0x10>;
716 snps,priority = <0x0>;
719 snps,weight = <0x11>;
721 snps,priority = <0x1>;
724 snps,weight = <0x12>;
726 snps,priority = <0x2>;
732 reg = <0 0x1101c000 0 0x1300>;
759 snps,clk-csr = <0>;
765 reg = <0 0x11230000 0 0x1000>;
777 reg = <0 0x11240000 0 0x1000>;
788 reg = <0 0x11250000 0 0x1000>;
799 reg = <0 0x11271000 0 0x3000>,
800 <0 0x11280700 0 0x0100>;
808 mediatek,syscon-wakeup = <&pericfg 0x510 2>;
817 reg = <0 0x11270000 0 0x1000>;
832 ranges = <0 0 0x11290000 0x9000>;
835 u2port0: usb-phy@0 {
836 reg = <0x0 0x700>;
844 reg = <0x8000 0x700>;
852 reg = <0x8700 0x900>;
862 reg = <0 0x112c1000 0 0x3000>,
863 <0 0x112d0700 0 0x0100>;
872 mediatek,syscon-wakeup = <&pericfg 0x514 2>;
881 reg = <0 0x112c0000 0 0x1000>;
896 ranges = <0 0 0x112e0000 0x9000>;
899 u2port2: usb-phy@0 {
900 reg = <0x0 0x700>;
908 reg = <0x8000 0x700>;
916 reg = <0x8700 0x900>;
927 reg = <0 0x112ff000 0 0x1000>;
939 bus-range = <0x00 0xff>;
940 ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
944 interrupt-map-mask = <0 0 0 7>;
945 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
946 <0 0 0 2 &pcie_intc1 1>,
947 <0 0 0 3 &pcie_intc1 2>,
948 <0 0 0 4 &pcie_intc1 3>;
951 #address-cells = <0>;
959 reg = <0 0x11700000 0 0x1000>;
961 linux,pci-domain = <0>;
971 bus-range = <0x00 0xff>;
972 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
976 interrupt-map-mask = <0 0 0 7>;
977 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
978 <0 0 0 2 &pcie_intc0 1>,
979 <0 0 0 3 &pcie_intc0 2>,
980 <0 0 0 4 &pcie_intc0 3>;
983 #address-cells = <0>;
990 reg = <0 0x13000000 0 0x1000>;
996 reg = <0 0x14000000 0 0x1000>;
1002 reg = <0 0x14021000 0 0x1000>;
1004 mediatek,larb-id = <0>;
1013 reg = <0 0x14022000 0 0x1000>;
1022 reg = <0 0x14027000 0 0x1000>;
1033 reg = <0 0x14030000 0 0x1000>;
1044 reg = <0 0x14031000 0 0x1000>;
1053 reg = <0 0x14032000 0 0x1000>;
1064 reg = <0 0x15000000 0 0x1000>;
1070 reg = <0 0x15001000 0 0x1000>;
1081 reg = <0 0x15010000 0 0x1000>;
1087 reg = <0 0x16000000 0 0x1000>;
1093 reg = <0 0x16010000 0 0x1000>;
1104 reg = <0 0x18000000 0 0x1000>;
1110 reg = <0 0x18001000 0 0x1000>;
1121 reg = <0 0x18002000 0 0x1000>;
1132 reg = <0 0x19000000 0 0x1000>;