Lines Matching +full:10 +full:gbase +full:- +full:r
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Device tree for the CN9131-DB board.
8 #include "cn9130-db.dtsi"
12 "marvell,armada-ap807-quad", "marvell,armada-ap807";
21 cp1_reg_usb3_vbus0: regulator-6 {
22 compatible = "regulator-fixed";
23 pinctrl-names = "default";
24 pinctrl-0 = <&cp1_xhci0_vbus_pins>;
25 regulator-name = "cp1-xhci0-vbus";
26 regulator-min-microvolt = <5000000>;
27 regulator-max-microvolt = <5000000>;
28 enable-active-high;
32 cp1_usb3_0_phy0: usb-phy-3 {
33 compatible = "usb-nop-xceiv";
34 vcc-supply = <&cp1_reg_usb3_vbus0>;
37 cp1_sfp_eth1: sfp-eth-2 {
39 i2c-bus = <&cp1_i2c0>;
40 los-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>;
41 mod-def0-gpios = <&cp1_gpio1 10 GPIO_ACTIVE_LOW>;
42 tx-disable-gpios = <&cp1_gpio1 9 GPIO_ACTIVE_HIGH>;
43 tx-fault-gpios = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
44 pinctrl-names = "default";
45 pinctrl-0 = <&cp1_sfp_pins>;
67 #include "armada-cp115.dtsi"
88 phy-mode = "10gbase-r";
91 managed = "in-band-status";
105 pinctrl-names = "default";
106 pinctrl-0 = <&cp1_i2c0_pins>;
107 clock-frequency = <100000>;
112 pinctrl-names = "default";
113 pinctrl-0 = <&cp1_pcie_reset_pins>;
114 num-lanes = <2>;
115 num-viewport = <8>;
116 marvell,reset-gpio = <&cp1_gpio1 0 GPIO_ACTIVE_HIGH>;
127 sata-port@1 {
136 pinctrl-names = "default";
137 pinctrl-0 = <&cp1_spi0_pins>;
141 compatible = "jedec,spi-nor";
143 /* On-board MUX does not allow higher frequencies */
144 spi-max-frequency = <40000000>;
147 compatible = "fixed-partitions";
148 #address-cells = <1>;
149 #size-cells = <1>;
152 label = "U-Boot-1";
157 label = "Filesystem-1";
167 compatible = "marvell,cp115-standalone-pinctrl";
169 cp1_i2c0_pins: cp1-i2c-pins-0 {
173 cp1_spi0_pins: cp1-spi-pins-0 {
177 cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
181 cp1_sfp_pins: sfp-pins {
185 cp1_pcie_reset_pins: cp1-pcie-reset-pins {
199 usb-phy = <&cp1_usb3_0_phy0>;
202 phy-names = "usb", "utmi";