Lines Matching +full:hog +full:-
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
9 /dts-v1/;
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
15 #include "cn9130-sr-som.dtsi"
29 #include "armada-cp115.dtsi"
41 compatible = "solidrun,cn9131-solidwan",
42 "solidrun,cn9130-sr-som", "marvell,cn9130";
67 compatible = "gpio-leds";
68 pinctrl-names = "default";
69 pinctrl-0 = <&cp0_led_pins &cp1_led_pins>;
71 /* for sfp-1 (J42) */
72 led-sfp1-activity {
77 /* for sfp-1 (J42) */
78 led-sfp1-link {
84 led-sfp0-activity {
90 led-sfp0-link {
96 /* Type-A port on J53 */
97 reg_usb_a_vbus0: regulator-usb-a-vbus0 {
98 compatible = "regulator-fixed";
99 pinctrl-0 = <&cp0_reg_usb_a_vbus0_pins>;
100 pinctrl-names = "default";
101 regulator-name = "vbus0";
102 regulator-min-microvolt = <5000000>;
103 regulator-max-microvolt = <5000000>;
105 enable-active-high;
106 regulator-always-on;
109 reg_usb_a_vbus1: regulator-usb-a-vbus1 {
110 compatible = "regulator-fixed";
111 pinctrl-0 = <&cp0_reg_usb_a_vbus1_pins>;
112 pinctrl-names = "default";
113 regulator-name = "vbus1";
114 regulator-min-microvolt = <5000000>;
115 regulator-max-microvolt = <5000000>;
117 enable-active-high;
118 regulator-always-on;
121 sfp0: sfp-0 {
123 pinctrl-0 = <&cp0_sfp0_pins>;
124 pinctrl-names = "default";
125 i2c-bus = <&cp0_i2c1>;
126 los-gpios = <&cp0_gpio2 2 GPIO_ACTIVE_HIGH>;
127 mod-def0-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
128 tx-disable-gpios = <&cp0_gpio2 1 GPIO_ACTIVE_HIGH>;
129 tx-fault-gpios = <&cp0_gpio1 31 GPIO_ACTIVE_HIGH>;
130 maximum-power-milliwatt = <2000>;
133 sfp1: sfp-1 {
135 pinctrl-0 = <&cp1_sfp1_pins>;
136 pinctrl-names = "default";
137 i2c-bus = <&cp1_i2c1>;
138 los-gpios = <&cp1_gpio2 2 GPIO_ACTIVE_HIGH>;
139 mod-def0-gpios = <&cp1_gpio2 18 GPIO_ACTIVE_LOW>;
140 tx-disable-gpios = <&cp1_gpio2 1 GPIO_ACTIVE_HIGH>;
141 tx-fault-gpios = <&cp1_gpio2 17 GPIO_ACTIVE_HIGH>;
142 maximum-power-milliwatt = <2000>;
150 /* SRDS #2 - SFP+ 10GE */
152 managed = "in-band-status";
153 phy-mode = "10gbase-r";
159 /* SRDS #3 - SGMII 1GE */
161 managed = "in-band-status";
162 phy-mode = "sgmii";
163 /* Without mdio phy access rely on sgmii auto-negotiation. */
168 /* SRDS #1 - SGMII */
170 /delete-property/ pinctrl-0;
171 /delete-property/ pinctrl-names;
172 managed = "in-band-status";
173 phy-mode = "sgmii";
179 pcie0-0-w-disable-hog {
180 gpio-hog;
182 output-low;
183 line-name = "pcie0.0-w-disable";
187 m2-full-card-power-off-hog {
188 gpio-hog;
190 output-low;
191 line-name = "m2-full-card-power-off";
197 fan-controller@18 {
206 usb-a-vbus0-ilimit-hog {
207 gpio-hog;
210 line-name = "vbus0-ilimit";
214 usb-vbus0-enable-hog {
215 gpio-hog;
218 line-name = "vbus0-enable";
221 usb-a-vbus1-ilimit-hog {
222 gpio-hog;
225 line-name = "vbus1-ilimit";
229 usb-vbus1-enable-hog {
230 gpio-hog;
233 line-name = "vbus1-enable";
243 /* usb-hub@60 */
249 pinctrl-0 = <&cp1_rtc_pins>;
250 pinctrl-names = "default";
251 interrupt-parent = <&cp1_gpio1>;
253 reset-gpios = <&cp1_gpio1 13 GPIO_ACTIVE_LOW>;
263 clock-frequency = <100000>;
264 pinctrl-0 = <&cp0_i2c1_pins>;
265 pinctrl-names = "default";
273 * SGMII Auto-Negotation is enabled by bootloader for
276 /delete-node/ ethernet-phy@0;
279 cp0_phy1: ethernet-phy@1 {
283 * - LED[0]: link is 1000Mbps: On (yellow)
284 * - LED[1]: link/activity: On/blink (green)
285 * - LED[2]: high impedance (floating)
287 marvell,reg-init = <3 16 0xf000 0x0a17>;
290 #address-cells = <1>;
291 #size-cells = <0>;
297 default-state = "keep";
304 default-state = "keep";
310 /* SRDS #0 - miniPCIe */
312 num-lanes = <1>;
317 /* SRDS #5 - M.2 B-Key (J34) */
319 num-lanes = <1>;
325 pinctrl-0 = <&cp0_m2_0_shutdown_pins &cp0_mpcie_rfkill_pins>;
326 pinctrl-names = "default";
328 cp0_i2c1_pins: cp0-i2c1-pins {
333 cp0_led_pins: cp0-led-pins {
338 cp0_m2_0_shutdown_pins: cp0-m2-0-shutdown-pins {
343 cp0_mmc0_pins: cp0-mmc0-pins {
349 cp0_mpcie_rfkill_pins: cp0-mpcie-rfkill-pins {
354 cp0_reg_usb_a_vbus0_pins: cp0-reg-usb-a-vbus0-pins {
359 cp0_reg_usb_a_vbus1_pins: cp0-reg-usb-a-vbus1-pins {
364 cp0_sfp0_pins: cp0-sfp0-pins {
369 cp0_spi1_cs1_pins: cp0-spi1-cs1-pins {
377 pinctrl-0 = <&cp0_mmc0_pins>;
378 pinctrl-names = "default";
379 bus-width = <4>;
380 no-1-8-v;
385 /* add pin for chip-select 1 */
386 pinctrl-0 = <&cp0_spi1_pins &cp0_spi1_cs1_pins>;
389 compatible = "jedec,spi-nor";
392 spi-max-frequency = <50000000>;
396 /* USB-2.0 Host to USB-Hub */
399 phy-names = "utmi";
404 /* SRDS #4 - USB-3.0 Host to USB-Hub */
407 phy-names = "comphy", "utmi";
424 /* SRDS #4 - SFP+ 10GE */
426 managed = "in-band-status";
427 phy-mode = "10gbase-r";
433 /* SRDS #3 - SGMII 1GE */
435 managed = "in-band-status";
436 phy-mode = "sgmii";
442 /* SRDS #5 - SGMII 1GE */
444 managed = "in-band-status";
445 phy-mode = "sgmii";
455 m2-full-card-power-off-hog-0 {
456 gpio-hog;
458 output-low;
459 line-name = "m2-full-card-power-off";
463 m2-full-card-power-off-hog-1 {
464 gpio-hog;
466 output-low;
467 line-name = "m2-full-card-power-off";
481 clock-frequency = <100000>;
482 pinctrl-0 = <&cp1_i2c1_pins>;
483 pinctrl-names = "default";
488 pinctrl-0 = <&cp1_mdio_pins>;
489 pinctrl-names = "default";
492 cp1_phy0: ethernet-phy@0 {
496 * - LED[0]: link is 1000Mbps: On (yellow)
497 * - LED[1]: link/activity: On/blink (green)
498 * - LED[2]: high impedance (floating)
500 marvell,reg-init = <3 16 0xf000 0x0a17>;
503 #address-cells = <1>;
504 #size-cells = <0>;
510 default-state = "keep";
517 default-state = "keep";
522 cp1_phy1: ethernet-phy@1 {
526 * - LED[0]: link is 1000Mbps: On (yellow)
527 * - LED[1]: link/activity: On/blink (green)
528 * - LED[2]: high impedance (floating)
530 marvell,reg-init = <3 16 0xf000 0x0a17>;
533 #address-cells = <1>;
534 #size-cells = <0>;
540 default-state = "keep";
547 default-state = "keep";
553 /* SRDS #0 - M.2 (J30) */
555 num-lanes = <1>;
564 /* SRDS #1 - SATA on M.2 (J44) */
570 /delete-node/ sata-port@1;
575 compatible = "marvell,cp115-standalone-pinctrl";
576 pinctrl-0 = <&cp1_m2_1_shutdown_pins &cp1_m2_2_shutdown_pins>;
577 pinctrl-names = "default";
579 cp1_i2c1_pins: cp0-i2c1-pins {
584 cp1_led_pins: cp1-led-pins {
589 cp1_m2_1_shutdown_pins: cp1-m2-1-shutdown-pins {
594 cp1_m2_2_shutdown_pins: cp1-m2-2-shutdown-pins {
599 cp1_mdio_pins: cp1-mdio-pins {
604 cp1_rtc_pins: cp1-rtc-pins {
609 cp1_sfp1_pins: cp1-sfp1-pins {
617 * SRDS #2 - USB-3.0 Host to M.2 (J44)
618 * USB-2.0 Host to M.2 (J30)
622 phy-names = "comphy", "utmi";
627 /* USB-2.0 Host to M.2 (J44) */
630 phy-names = "utmi";