Lines Matching +full:10 +full:gbase +full:- +full:r
1 // SPDX-License-Identifier: GPL-2.0+
8 #include <dt-bindings/gpio/gpio.h>
12 stdout-path = "serial0:115200n8";
29 ap0_reg_mmc_vccq: regulator-1 {
30 compatible = "regulator-gpio";
31 regulator-name = "ap0_mmc_vccq";
32 regulator-min-microvolt = <1800000>;
33 regulator-max-microvolt = <3300000>;
39 cp0_reg_usb3_vbus1: regulator-2 {
40 compatible = "regulator-fixed";
41 regulator-name = "cp0-xhci1-vbus";
42 regulator-min-microvolt = <5000000>;
43 regulator-max-microvolt = <5000000>;
44 enable-active-high;
48 cp0_usb3_0_phy0: usb-phy-1 {
49 compatible = "usb-nop-xceiv";
52 cp0_usb3_0_phy1: usb-phy-2 {
53 compatible = "usb-nop-xceiv";
54 vcc-supply = <&cp0_reg_usb3_vbus1>;
57 cp0_reg_sd_vccq: regulator-3 {
58 compatible = "regulator-gpio";
59 regulator-name = "cp0_sd_vccq";
60 regulator-min-microvolt = <1800000>;
61 regulator-max-microvolt = <3300000>;
67 cp0_reg_sd_vcc: regulator-4 {
68 compatible = "regulator-fixed";
69 regulator-name = "cp0_sd_vcc";
70 regulator-min-microvolt = <3300000>;
71 regulator-max-microvolt = <3300000>;
73 enable-active-high;
74 regulator-always-on;
79 i2c-bus = <&cp0_i2c1>;
80 mod-def0-gpios = <&expander0 3 GPIO_ACTIVE_LOW>;
81 los-gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
82 tx-disable-gpios = <&expander0 2 GPIO_ACTIVE_HIGH>;
83 tx-fault-gpios = <&cp0_gpio1 24 GPIO_ACTIVE_HIGH>;
84 maximum-power-milliwatt = <3000>;
92 /* on-board eMMC U6 */
94 pinctrl-names = "default";
95 bus-width = <8>;
97 mmc-ddr-1_8v;
98 vqmmc-supply = <&ap0_reg_mmc_vccq>;
103 compatible = "marvell,cp115-standalone-pinctrl";
105 cp0_i2c0_pins: cp0-i2c-pins-0 {
109 cp0_i2c1_pins: cp0-i2c-pins-1 {
113 cp0_sdhci_cd_pins_crb: cp0-sdhci-cd-pins-crb {
117 cp0_sdhci_pins: cp0-sdhi-pins-0 {
122 cp0_spi1_pins: cp0-spi-pins-1 {
138 pinctrl-names = "default";
139 pinctrl-0 = <&cp0_i2c0_pins>;
141 clock-frequency = <100000>;
144 gpio-controller;
145 #gpio-cells = <2>;
152 pinctrl-names = "default";
153 pinctrl-0 = <&cp0_i2c1_pins>;
154 clock-frequency = <100000>;
160 pinctrl-names = "default";
161 pinctrl-0 = <&cp0_sdhci_pins
163 bus-width = <4>;
164 cd-gpios = <&cp0_gpio2 23 GPIO_ACTIVE_HIGH>;
165 vqmmc-supply = <&cp0_reg_sd_vccq>;
166 vmmc-supply = <&cp0_reg_sd_vcc>;
171 pinctrl-names = "default";
172 pinctrl-0 = <&cp0_spi1_pins>;
178 #address-cells = <0x1>;
179 #size-cells = <0x1>;
180 compatible = "jedec,spi-nor";
182 /* On-board MUX does not allow higher frequencies */
183 spi-max-frequency = <40000000>;
186 compatible = "fixed-partitions";
187 #address-cells = <1>;
188 #size-cells = <1>;
191 label = "U-Boot";
205 phy0: ethernet-phy@0 {
209 switch6: ethernet-switch@6 {
213 interrupt-parent = <&cp0_gpio1>;
215 interrupt-controller;
216 #interrupt-cells = <2>;
220 ethernet-ports {
221 #address-cells = <1>;
222 #size-cells = <0>;
224 ethernet-port@1 {
227 phy-handle = <&switch0phy1>;
230 ethernet-port@2 {
233 phy-handle = <&switch0phy2>;
236 ethernet-port@3 {
239 phy-handle = <&switch0phy3>;
242 ethernet-port@4 {
245 phy-handle = <&switch0phy4>;
248 ethernet-port@5 {
251 phy-handle = <&switch0phy5>;
254 ethernet-port@6 {
257 phy-handle = <&switch0phy6>;
260 ethernet-port@7 {
263 phy-handle = <&switch0phy7>;
266 ethernet-port@8 {
269 phy-handle = <&switch0phy8>;
272 ethernet-port@9 {
275 phy-mode = "10gbase-r";
277 managed = "in-band-status";
280 ethernet-port@a {
281 reg = <10>;
283 phy-mode = "10gbase-r";
284 managed = "in-band-status";
290 #address-cells = <1>;
291 #size-cells = <0>;
293 switch0phy1: ethernet-phy@1 {
297 switch0phy2: ethernet-phy@2 {
301 switch0phy3: ethernet-phy@3 {
305 switch0phy4: ethernet-phy@4 {
309 switch0phy5: ethernet-phy@5 {
313 switch0phy6: ethernet-phy@6 {
317 switch0phy7: ethernet-phy@7 {
321 switch0phy8: ethernet-phy@8 {
330 nbaset_phy0: ethernet-phy@0 {
331 compatible = "ethernet-phy-ieee802.3-c45";
343 phy-mode = "10gbase-r";
344 managed = "in-band-status";
351 phy-mode = "rgmii-id";
355 /* This port uses "2500base-t" phy-mode */