Lines Matching +full:0 +full:x129000
29 polling-delay-passive = <0>; /* Interrupt driven */
30 polling-delay = <0>; /* Interrupt driven */
32 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
58 ranges = <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>;
60 CP11X_LABEL(ethernet): ethernet@0 {
62 #size-cells = <0>;
64 reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>;
74 CP11X_LABEL(eth0): ethernet-port@0 {
88 reg = <0>;
89 port-id = <0>; /* For backward compatibility. */
90 gop-port-id = <0>;
137 reg = <0x120000 0x6000>;
143 #size-cells = <0>;
145 CP11X_LABEL(comphy0): phy@0 {
146 reg = <0>;
178 #size-cells = <0>;
180 reg = <0x12a200 0x10>;
188 #size-cells = <0>;
190 reg = <0x12a600 0x10>;
198 reg = <0x1e0000 0x440>;
204 reg = <0x10 0x20>;
212 reg = <0x50 0x10>;
221 reg = <0x284000 0x20>, <0x284080 0x24>;
228 reg = <0x440000 0x2000>;
237 offset = <0x100>;
241 gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>;
242 marvell,pwm-offset = <0x1f0>;
258 offset = <0x140>;
262 gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>;
263 marvell,pwm-offset = <0x1f0>;
280 reg = <0x400000 0x1000>;
286 reg = <0x70 0x10>;
295 reg = <0x580000 0x2000>;
298 #size-cells = <0>;
301 CP11X_LABEL(utmi0): usb-phy@0 {
302 reg = <0>;
303 #phy-cells = <0>;
308 #phy-cells = <0>;
315 reg = <0x500000 0x4000>;
327 reg = <0x510000 0x4000>;
339 reg = <0x540000 0x30000>;
345 #size-cells = <0>;
348 sata-port@0 {
349 reg = <0>;
359 reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
369 reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
379 reg = <0x700600 0x50>;
380 #address-cells = <0x1>;
381 #size-cells = <0x0>;
390 reg = <0x700680 0x50>;
392 #size-cells = <0>;
401 reg = <0x701000 0x20>;
403 #size-cells = <0>;
413 reg = <0x701100 0x20>;
415 #size-cells = <0>;
425 reg = <0x702000 0x100>;
437 reg = <0x702100 0x100>;
449 reg = <0x702200 0x100>;
461 reg = <0x702300 0x100>;
479 reg = <0x720000 0x54>;
481 #size-cells = <0>;
493 reg = <0x760000 0x7d>;
503 reg = <0x780000 0x300>;
513 reg = <0x800000 0x200000>;
531 reg = <0 ADDRESSIFY(CP11X_PCIE0_BASE) 0 0x10000>,
532 <0 CP11X_PCIEx_CONF_BASE(0) 0 0x80000>;
541 bus-range = <0 0xff>;
543 …ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0…
544 interrupt-map-mask = <0 0 0 0>;
545 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
555 reg = <0 ADDRESSIFY(CP11X_PCIE1_BASE) 0 0x10000>,
556 <0 CP11X_PCIEx_CONF_BASE(1) 0 0x80000>;
565 bus-range = <0 0xff>;
567 …ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1…
568 interrupt-map-mask = <0 0 0 0>;
569 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
580 reg = <0 ADDRESSIFY(CP11X_PCIE2_BASE) 0 0x10000>,
581 <0 CP11X_PCIEx_CONF_BASE(2) 0 0x80000>;
590 bus-range = <0 0xff>;
592 …ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2…
593 interrupt-map-mask = <0 0 0 0>;
594 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;