Lines Matching +full:generic +full:- +full:names
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-8040.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
14 compatible = "marvell,armada8040-mcbin", "marvell,armada8040",
15 "marvell,armada-ap806-quad", "marvell,armada-ap806";
18 stdout-path = "serial0:115200n8";
34 v_3_3: regulator-3-3v {
35 compatible = "regulator-fixed";
36 regulator-name = "v_3_3";
37 regulator-min-microvolt = <3300000>;
38 regulator-max-microvolt = <3300000>;
39 regulator-always-on;
43 v_vddo_h: regulator-1-8v {
44 compatible = "regulator-fixed";
45 regulator-name = "v_vddo_h";
46 regulator-min-microvolt = <1800000>;
47 regulator-max-microvolt = <1800000>;
48 regulator-always-on;
52 v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
53 compatible = "regulator-fixed";
54 enable-active-high;
56 pinctrl-names = "default";
57 pinctrl-0 = <&cp0_xhci_vbus_pins>;
58 regulator-name = "v_5v0_usb3_hst_vbus";
59 regulator-min-microvolt = <5000000>;
60 regulator-max-microvolt = <5000000>;
64 sfp_eth0: sfp-eth0 {
65 /* CON15,16 - CPM lane 4 */
67 i2c-bus = <&sfpp0_i2c>;
68 los-gpios = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>;
69 mod-def0-gpios = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>;
70 tx-disable-gpios = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
71 tx-fault-gpios = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&cp1_sfpp0_pins>;
74 maximum-power-milliwatt = <2000>;
77 sfp_eth1: sfp-eth1 {
78 /* CON17,18 - CPS lane 4 */
80 i2c-bus = <&sfpp1_i2c>;
81 los-gpios = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
82 mod-def0-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;
83 tx-disable-gpios = <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>;
84 tx-fault-gpios = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>;
85 pinctrl-names = "default";
86 pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>;
87 maximum-power-milliwatt = <2000>;
90 sfp_eth3: sfp-eth3 {
91 /* CON13,14 - CPS lane 5 */
93 i2c-bus = <&sfp_1g_i2c>;
94 los-gpios = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>;
95 mod-def0-gpios = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>;
96 tx-disable-gpios = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>;
97 tx-fault-gpios = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
98 pinctrl-names = "default";
99 pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>;
100 maximum-power-milliwatt = <2000>;
106 pinctrl-0 = <&uart0_pins>;
107 pinctrl-names = "default";
111 bus-width = <8>;
113 * Not stable in HS modes - phy needs "more calibration", so add
114 * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
116 marvell,xenon-phy-slow-mode;
117 no-1-8-v;
118 no-sd;
119 no-sdio;
120 non-removable;
122 vqmmc-supply = <&v_vddo_h>;
126 clock-frequency = <100000>;
127 pinctrl-names = "default";
128 pinctrl-0 = <&cp0_i2c0_pins>;
133 clock-frequency = <100000>;
134 pinctrl-names = "default";
135 pinctrl-0 = <&cp0_i2c1_pins>;
138 i2c-mux@70 {
140 #address-cells = <1>;
141 #size-cells = <0>;
145 #address-cells = <1>;
146 #size-cells = <0>;
150 #address-cells = <1>;
151 #size-cells = <0>;
155 #address-cells = <1>;
156 #size-cells = <0>;
164 pinctrl-names = "default";
165 pinctrl-0 = <&cp0_uart1_pins>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&cp0_ge_mdio_pins>;
174 ge_phy: ethernet-phy@0 {
180 pinctrl-names = "default";
181 pinctrl-0 = <&cp0_pcie_pins>;
182 num-lanes = <4>;
183 num-viewport = <8>;
184 reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;
188 phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
189 "cp0-pcie0-x4-lane2-phy", "cp0-pcie0-x4-lane3-phy";
194 cp0_ge_mdio_pins: ge-mdio-pins {
198 cp0_i2c1_pins: i2c1-pins {
202 cp0_i2c0_pins: i2c0-pins {
206 cp0_uart1_pins: uart1-pins {
210 cp0_xhci_vbus_pins: xhci0-vbus-pins {
214 cp0_sfp_1g_pins: sfp-1g-pins {
218 cp0_pcie_pins: pcie-pins {
222 cp0_sdhci_pins: sdhci-pins {
227 cp0_sfpp1_pins: sfpp1-pins {
238 /* Generic PHY, providing serdes lanes */
245 /* CPM Lane 5 - U29 */
246 sata-port@1 {
248 phy-names = "cp0-sata0-1-phy";
254 broken-cd;
255 bus-width = <4>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&cp0_sdhci_pins>;
259 vqmmc-supply = <&v_3_3>;
267 /* J38? - USB2.0 only */
269 phy-names = "utmi";
275 /* J38? - USB2.0 only */
277 phy-names = "utmi";
287 /* Generic PHY, providing serdes lanes */
292 /* CPS Lane 0 - J5 (Gigabit RJ45) */
296 phy-mode = "sgmii";
297 /* Generic PHY, providing serdes lanes */
305 phy-mode = "2500base-x";
306 managed = "in-band-status";
307 /* Generic PHY, providing serdes lanes */
313 cp1_sfpp1_pins: sfpp1-pins {
317 cp1_spi1_pins: spi1-pins {
321 cp1_uart0_pins: uart0-pins {
325 cp1_sfp_1g_pins: sfp-1g-pins {
329 cp1_sfpp0_pins: sfpp0-pins {
337 pinctrl-names = "default";
338 pinctrl-0 = <&cp1_uart0_pins>;
345 /* CPS Lane 1 - U32 */
346 sata-port@0 {
348 phy-names = "cp1-sata0-0-phy";
351 /* CPS Lane 3 - U31 */
352 sata-port@1 {
354 phy-names = "cp1-sata0-1-phy";
359 pinctrl-names = "default";
360 pinctrl-0 = <&cp1_spi1_pins>;
365 spi-max-frequency = <50000000>;
372 compatible = "usb-a-connector";
373 phy-supply = <&v_5v0_usb3_hst_vbus>;
382 /* CPS Lane 2 - CON7 */
384 phy-names = "cp1-usb3h0-comphy", "utmi";