Lines Matching +full:phy +full:- +full:reset +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include "armada-7040.dtsi"
17 "marvell,armada-ap806-quad", "marvell,armada-ap806";
20 stdout-path = "serial0:115200n8";
34 sfp_eth0: sfp-eth0 {
36 i2c-bus = <&cp0_i2c1>;
37 los-gpios = <&sfp_gpio 3 GPIO_ACTIVE_HIGH>;
38 mod-def0-gpios = <&sfp_gpio 2 GPIO_ACTIVE_LOW>;
39 tx-disable-gpios = <&sfp_gpio 1 GPIO_ACTIVE_HIGH>;
40 tx-fault-gpios = <&sfp_gpio 0 GPIO_ACTIVE_HIGH>;
44 sfp_eth2: sfp-eth2 {
46 i2c-bus = <&cp0_i2c0>;
47 los-gpios = <&sfp_gpio 7 GPIO_ACTIVE_HIGH>;
48 mod-def0-gpios = <&sfp_gpio 6 GPIO_ACTIVE_LOW>;
49 tx-disable-gpios = <&sfp_gpio 5 GPIO_ACTIVE_HIGH>;
50 tx-fault-gpios = <&sfp_gpio 4 GPIO_ACTIVE_HIGH>;
58 pinctrl-0 = <&uart0_pins>;
59 pinctrl-names = "default";
66 bus-width = <4>;
67 non-removable;
68 /delete-property/ marvell,xenon-phy-slow-mode;
69 no-1-8-v;
73 cp0_uart0_pins: cp0-uart0-pins {
78 cp0_spi0_pins: cp0-spi0-pins {
83 cp0_spi1_pins: cp0-spi1-pins {
88 cp0_i2c0_pins: cp0-i2c0-pins {
93 cp0_i2c1_pins: cp0-i2c1-pins {
98 pca9554_int_pins: pca9554-int-pins {
103 cp0_rgmii1_pins: cp0-rgmii1-pins {
109 is31_sdb_pins: is31-sdb-pins {
114 cp0_pcie_reset_pins: cp0-pcie-reset-pins {
119 cp0_pcie_clkreq_pins: cp0-pcie-clkreq-pins {
124 cp0_switch_pins: cp0-switch-pins {
129 cp0_phy_pins: cp0-phy-pins {
139 pinctrl-names = "default";
140 pinctrl-0 = <&cp0_uart0_pins>;
147 pinctrl-names = "default";
148 pinctrl-0 = <&cp0_spi0_pins>;
151 /* SPI-NOR */
155 pinctrl-names = "default";
156 pinctrl-0 = <&cp0_spi1_pins>;
159 #address-cells = <1>;
160 #size-cells = <1>;
161 compatible = "jedec,spi-nor";
163 spi-max-frequency = <20000000>;
166 compatible = "fixed-partitions";
167 #address-cells = <1>;
168 #size-cells = <1>;
173 read-only;
177 label = "hw-info";
179 read-only;
183 label = "u-boot-env";
194 pinctrl-names = "default";
195 pinctrl-0 = <&cp0_i2c0_pins>;
196 clock-frequency = <100000>;
200 pinctrl-names = "default";
201 pinctrl-0 = <&pca9554_int_pins>;
204 interrupt-parent = <&cp0_gpio1>;
206 interrupt-controller;
207 #interrupt-cells = <2>;
209 gpio-controller;
210 #gpio-cells = <2>;
225 /* IS31FL3199, mini-PCIe and 10G SFP+ */
229 pinctrl-names = "default";
230 pinctrl-0 = <&cp0_i2c1_pins>;
231 clock-frequency = <100000>;
235 #address-cells = <1>;
236 #size-cells = <0>;
237 pinctrl-names = "default";
238 pinctrl-0 = <&is31_sdb_pins>;
239 shutdown-gpios = <&cp0_gpio1 30 GPIO_ACTIVE_HIGH>;
245 led-max-microamp = <20000>;
293 /* 88E1512 PHY */
294 eth2phy: ethernet-phy@1 {
298 pinctrl-names = "default";
299 pinctrl-0 = <&cp0_phy_pins>;
300 reset-gpios = <&cp0_gpio1 12 GPIO_ACTIVE_LOW>;
304 switch: ethernet-switch@3 {
308 pinctrl-names = "default";
309 pinctrl-0 = <&cp0_switch_pins>;
310 reset-gpios = <&cp0_gpio1 0 GPIO_ACTIVE_LOW>;
312 interrupt-parent = <&cp0_gpio1>;
315 ethernet-ports {
316 #address-cells = <1>;
317 #size-cells = <0>;
319 swport1: ethernet-port@1 {
322 phy-handle = <&swphy1>;
325 swport2: ethernet-port@2 {
328 phy-handle = <&swphy2>;
331 swport3: ethernet-port@3 {
334 phy-handle = <&swphy3>;
337 swport4: ethernet-port@4 {
340 phy-handle = <&swphy4>;
343 ethernet-port@5 {
347 phy-mode = "2500base-x";
348 managed = "in-band-status";
353 #address-cells = <1>;
354 #size-cells = <0>;
356 swphy1: ethernet-phy@17 {
360 swphy2: ethernet-phy@18 {
364 swphy3: ethernet-phy@19 {
368 swphy4: ethernet-phy@20 {
383 phy-mode = "10gbase-r";
385 managed = "in-band-status";
393 phy-mode = "2500base-x";
396 fixed-link {
398 full-duplex;
406 pinctrl-names = "default";
407 pinctrl-0 = <&cp0_rgmii1_pins>;
409 phy = <ð2phy>;
410 phy-mode = "rgmii-id";
422 phy-names = "cp0-usb3h0-comphy", "utmi";
425 /* miniPCI-E USB */
434 sata-port@0 {
436 phy-names = "cp0-sata0-0-phy";
439 /* M.2-2250 B-key (J39) */
440 sata-port@1 {
442 phy-names = "cp0-sata0-1-phy";
446 /* miniPCI-E (J5) */
450 pinctrl-names = "default", "clkreq";
451 pinctrl-0 = <&cp0_pcie_reset_pins>;
452 pinctrl-1 = <&cp0_pcie_clkreq_pins>;
454 phy-names = "cp0-pcie2-x1-phy";
455 reset-gpios = <&cp0_gpio1 9 GPIO_ACTIVE_LOW>;