Lines Matching +full:0 +full:x5f800
33 reg = <0 0x4000000 0 0x200000>;
38 reg = <0 0x4400000 0 0x1000000>;
45 #size-cells = <0>;
46 cpu0: cpu@0 {
49 reg = <0>;
83 /* 32M internal register @ 0xd000_0000 */
84 ranges = <0x0 0x0 0xd0000000 0x2000000>;
88 reg = <0x8300 0x40>;
96 reg = <0xd000 0x1000>;
102 #size-cells = <0>;
103 reg = <0x10600 0xA00>;
105 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
112 reg = <0x11000 0x24>;
114 #size-cells = <0>;
123 reg = <0x11080 0x24>;
125 #size-cells = <0>;
135 reg = <0x11500 0x40>;
140 reg = <0x12010 0x4>, <0x12210 0x4>;
141 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
150 reg = <0x12000 0x18>;
151 clocks = <&uartclk 0>;
162 reg = <0x12200 0x30>;
174 reg = <0x13000 0x100>;
175 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
182 reg = <0x18000 0x100>;
183 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
190 reg = <0x13200 0x100>;
198 reg = <0x13800 0x100>, <0x13C00 0x20>;
199 /* MPP1[19:0] */
202 gpio-ranges = <&pinctrl_nb 0 0 36>;
224 #clock-cells = <0>;
266 reg = <0x14000 0x60>;
271 reg = <0x18300 0x300>,
272 <0x1F000 0x400>,
273 <0x5C000 0x400>,
274 <0xe0178 0x8>;
280 #size-cells = <0>;
284 comphy0: phy@0 {
285 reg = <0>;
303 reg = <0x18800 0x100>, <0x18C00 0x20>;
304 /* MPP2[23:0] */
307 gpio-ranges = <&pinctrl_sb 0 0 30>;
347 reg = <0x30000 0x4000>;
355 #size-cells = <0>;
357 reg = <0x32004 0x4>;
362 reg = <0x40000 0x4000>;
371 reg = <0x58000 0x4000>;
375 phys = <&comphy0 0>, <&usb2_utmi_otg_phy>;
382 reg = <0x5d000 0x800>;
384 #phy-cells = <0>;
390 reg = <0x5d800 0x800>;
395 reg = <0x5e000 0x1000>;
405 reg = <0x5f000 0x800>;
407 #phy-cells = <0>;
413 reg = <0x5f800 0x800>;
418 reg = <0x60900 0x100>,
419 <0x60b00 0x100>;
431 reg = <0x90000 0x20000>;
445 reg = <0xb0000 0x100>;
453 reg = <0xd0000 0x300>,
454 <0x1e808 0x4>;
456 clocks = <&nb_periph_clk 0>;
464 reg = <0xd8000 0x300>,
465 <0x17808 0x4>;
467 clocks = <&nb_periph_clk 0>;
474 reg = <0xe0000 0x178>;
477 phys = <&comphy2 0>;
486 reg = <0x1d00000 0x10000>, /* GICD */
487 <0x1d40000 0x40000>, /* GICR */
488 <0x1d80000 0x2000>, /* GICC */
489 <0x1d90000 0x2000>, /* GICH */
490 <0x1da0000 0x20000>; /* GICV */
499 reg = <0 0xd0070000 0 0x20000>;
502 bus-range = <0x00 0xff>;
509 * The 128 MiB address range [0xe8000000-0xf0000000] is
515 ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x07f00000 /* Port 0 MEM */
516 0x81000000 0 0x00000000 0 0xefff0000 0 0x00010000>; /* Port 0 IO */
517 interrupt-map-mask = <0 0 0 7>;
518 interrupt-map = <0 0 0 1 &pcie_intc 0>,
519 <0 0 0 2 &pcie_intc 1>,
520 <0 0 0 3 &pcie_intc 2>,
521 <0 0 0 4 &pcie_intc 3>;
523 phys = <&comphy1 0>;
534 mboxes = <&rwtm 0>;