Lines Matching +full:0 +full:x1f0
21 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0x0 0x0>;
45 reg = <0x0 0x100>;
85 /* 16M internal register @ 0x7f00_0000 */
86 ranges = <0x0 0x0 0x7f000000 0x1000000>;
91 reg = <0x12000 0x100>;
101 reg = <0x12100 0x100>;
111 reg = <0x12200 0x100>;
121 reg = <0x12300 0x100>;
131 #size-cells = <0>;
133 reg = <0x22004 0x4>;
139 reg = <0x11000 0x20>;
141 #size-cells = <0>;
149 pinctrl-0 = <&i2c0_pins>;
158 reg = <0x11100 0x20>;
160 #size-cells = <0>;
168 pinctrl-0 = <&i2c1_pins>;
177 reg = <0x18100 0x40>;
181 gpio-ranges = <&pinctrl0 0 0 32>;
182 marvell,pwm-offset = <0x1f0>;
192 reg = <0x18140 0x40>;
197 gpio-ranges = <&pinctrl0 0 32 14>;
198 marvell,pwm-offset = <0x1f0>;
209 #address-cells = <0x2>;
210 #size-cells = <0x2>;
211 reg = <0x0 0x80500000 0x0 0x100000>;
212 dma-ranges = <0x0 0x0 0x2 0x0 0x0 0x80000000>;
218 reg = <0x0 0x805c0000 0x0 0x1000>;
236 #address-cells = <0x2>;
237 #size-cells = <0x2>;
238 ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>;
239 /* Host phy ram starts at 0x200M */
240 dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>;
245 reg = <0x0 0x20000 0x0 0x4000>;
254 reg = <0x0 0x24000 0x0 0x4000>;
263 reg = <0x0 0x80000 0x0 0x500>;
270 reg = <0x0 0xa0000 0x0 0x500>;
278 reg = <0 0x80020100 0 0x20>;
303 reg = <0x0 0x805a0000 0x0 0x50>;
304 #address-cells = <0x1>;
305 #size-cells = <0x0>;
314 reg = <0x0 0x805a8000 0x0 0x50>;
315 #address-cells = <0x1>;
316 #size-cells = <0x0>;
325 reg = <0x0 0x805b0000 0x0 0x00000054>;
326 #address-cells = <0x1>;
327 #size-cells = <0x0>;
337 reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */
338 <0x0 0x80660000 0x0 0x40000>; /* GICR */
346 #clock-cells = <0>;
352 #clock-cells = <0>;
358 #clock-cells = <0>;
364 #clock-cells = <0>;