Lines Matching +full:coe +full:- +full:unsupported
1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
14 compatible = "intel,socfpga-agilex5";
15 #address-cells = <2>;
16 #size-cells = <2>;
18 reserved-memory {
19 #address-cells = <2>;
20 #size-cells = <2>;
24 compatible = "shared-dma-pool";
27 no-map;
32 #address-cells = <1>;
33 #size-cells = <0>;
36 compatible = "arm,cortex-a55";
39 enable-method = "psci";
40 next-level-cache = <&L2>;
44 compatible = "arm,cortex-a55";
47 enable-method = "psci";
48 next-level-cache = <&L2>;
52 compatible = "arm,cortex-a76";
55 enable-method = "psci";
56 next-level-cache = <&L2>;
60 compatible = "arm,cortex-a76";
63 enable-method = "psci";
64 next-level-cache = <&L2>;
67 L2: l2-cache {
69 cache-level = <2>;
70 next-level-cache = <&L3>;
71 cache-unified;
74 L3: l3-cache {
76 cache-level = <3>;
77 cache-unified;
84 compatible = "intel,agilex5-svc";
86 memory-region = <&service_reserved>;
92 compatible = "arm,psci-0.2";
96 intc: interrupt-controller@1d000000 {
97 compatible = "arm,gic-v3";
101 #interrupt-cells = <3>;
102 #address-cells = <2>;
103 #size-cells = <2>;
104 interrupt-controller;
105 interrupt-parent = <&intc>;
106 #redistributor-regions = <1>;
107 redistributor-stride = <0x0 0x20000>;
111 its: msi-controller@1d040000 {
112 compatible = "arm,gic-v3-its";
114 msi-controller;
115 #msi-cells = <1>;
121 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
122 #clock-cells = <0>;
123 compatible = "fixed-clock";
124 clock-frequency = <0>;
127 cb_intosc_ls_clk: cb-intosc-ls-clk {
128 #clock-cells = <0>;
129 compatible = "fixed-clock";
130 clock-frequency = <0>;
133 f2s_free_clk: f2s-free-clk {
134 #clock-cells = <0>;
135 compatible = "fixed-clock";
136 clock-frequency = <0>;
140 #clock-cells = <0>;
141 compatible = "fixed-clock";
142 clock-frequency = <0>;
145 qspi_clk: qspi-clk {
146 #clock-cells = <0>;
147 compatible = "fixed-clock";
148 clock-frequency = <200000000>;
153 compatible = "arm,armv8-timer";
154 interrupt-parent = <&intc>;
162 #phy-cells = <0>;
163 compatible = "usb-nop-xceiv";
167 compatible = "arm,armv8-pmuv3";
168 interrupt-parent = <&intc>;
173 compatible = "simple-bus";
175 #address-cells = <1>;
176 #size-cells = <1>;
178 interrupt-parent = <&intc>;
180 clkmgr: clock-controller@10d10000 {
181 compatible = "intel,agilex5-clkmgr";
183 #clock-cells = <1>;
187 compatible = "snps,designware-i2c";
189 #address-cells = <1>;
190 #size-cells = <0>;
198 compatible = "snps,designware-i2c";
200 #address-cells = <1>;
201 #size-cells = <0>;
209 compatible = "snps,designware-i2c";
211 #address-cells = <1>;
212 #size-cells = <0>;
220 compatible = "snps,designware-i2c";
222 #address-cells = <1>;
223 #size-cells = <0>;
231 compatible = "snps,designware-i2c";
233 #address-cells = <1>;
234 #size-cells = <0>;
242 compatible = "altr,agilex5-dw-i3c-master",
243 "snps,dw-i3c-master-1.00a";
245 #address-cells = <3>;
246 #size-cells = <0>;
253 compatible = "altr,agilex5-dw-i3c-master",
254 "snps,dw-i3c-master-1.00a";
256 #address-cells = <3>;
257 #size-cells = <0>;
264 compatible = "snps,dw-apb-gpio";
266 #address-cells = <1>;
267 #size-cells = <0>;
271 porta: gpio-controller@0 {
272 compatible = "snps,dw-apb-gpio-port";
274 gpio-controller;
275 #gpio-cells = <2>;
276 snps,nr-gpios = <24>;
277 interrupt-controller;
278 #interrupt-cells = <2>;
284 compatible = "snps,dw-apb-gpio";
286 #address-cells = <1>;
287 #size-cells = <0>;
291 portb: gpio-controller@0 {
292 compatible = "snps,dw-apb-gpio-port";
294 gpio-controller;
295 #gpio-cells = <2>;
296 snps,nr-gpios = <24>;
297 interrupt-controller;
298 #interrupt-cells = <2>;
303 nand: nand-controller@10b80000 {
304 compatible = "cdns,hp-nfc";
307 reg-names = "reg", "sdma";
308 #address-cells = <1>;
309 #size-cells = <0>;
312 clock-names = "nf_clk";
313 cdns,board-delay-ps = <4830>;
319 compatible = "mmio-sram";
322 #address-cells = <1>;
323 #size-cells = <1>;
326 dmac0: dma-controller@10db0000 {
327 compatible = "snps,axi-dma-1.01a";
331 clock-names = "core-clk", "cfgr-clk";
332 interrupt-parent = <&intc>;
334 #dma-cells = <1>;
335 dma-channels = <4>;
336 snps,dma-masters = <1>;
337 snps,data-width = <2>;
338 snps,block-size = <32767 32767 32767 32767>;
340 snps,axi-max-burst-len = <8>;
344 dmac1: dma-controller@10dc0000 {
345 compatible = "snps,axi-dma-1.01a";
349 clock-names = "core-clk", "cfgr-clk";
350 interrupt-parent = <&intc>;
352 #dma-cells = <1>;
353 dma-channels = <4>;
354 snps,dma-masters = <1>;
355 snps,data-width = <2>;
356 snps,block-size = <32767 32767 32767 32767>;
358 snps,axi-max-burst-len = <8>;
363 compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr";
365 #reset-cells = <1>;
369 compatible = "arm,smmu-v3";
374 interrupt-names = "eventq", "gerror", "priq";
375 dma-coherent;
376 #iommu-cells = <1>;
381 compatible = "snps,dw-apb-ssi";
383 #address-cells = <1>;
384 #size-cells = <0>;
387 reset-names = "spi";
388 reg-io-width = <4>;
389 num-cs = <4>;
392 dma-names = "tx", "rx";
398 compatible = "snps,dw-apb-ssi";
400 #address-cells = <1>;
401 #size-cells = <0>;
404 reset-names = "spi";
405 reg-io-width = <4>;
406 num-cs = <4>;
409 dma-names = "tx", "rx";
414 compatible = "altr,sys-mgr-s10","altr,sys-mgr";
419 compatible = "snps,dw-apb-timer";
423 clock-names = "timer";
427 compatible = "snps,dw-apb-timer";
431 clock-names = "timer";
435 compatible = "snps,dw-apb-timer";
439 clock-names = "timer";
443 compatible = "snps,dw-apb-timer";
447 clock-names = "timer";
451 compatible = "snps,dw-apb-uart";
454 reg-shift = <2>;
455 reg-io-width = <4>;
462 compatible = "snps,dw-apb-uart";
465 reg-shift = <2>;
466 reg-io-width = <4>;
477 phy-names = "usb2-phy";
479 reset-names = "dwc2", "dwc2-ecc";
482 clock-names = "otg";
487 compatible = "snps,dw-wdt";
496 compatible = "snps,dw-wdt";
505 compatible = "snps,dw-wdt";
514 compatible = "snps,dw-wdt";
523 compatible = "snps,dw-wdt";
532 compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
535 #address-cells = <1>;
536 #size-cells = <0>;
538 cdns,fifo-depth = <128>;
539 cdns,fifo-width = <4>;
540 cdns,trigger-address = <0x00000000>;
546 compatible = "altr,socfpga-stmmac-agilex5",
547 "snps,dwxgmac-2.10";
550 interrupt-names = "macirq";
552 reset-names = "stmmaceth", "ahb";
555 clock-names = "stmmaceth", "ptp_ref";
556 mac-address = [00 00 00 00 00 00];
557 tx-fifo-depth = <32768>;
558 rx-fifo-depth = <16384>;
559 snps,multicast-filter-bins = <64>;
560 snps,perfect-filter-entries = <64>;
561 snps,axi-config = <&stmmac_axi_emac0_setup>;
562 snps,mtl-rx-config = <&mtl_rx_emac0_setup>;
563 snps,mtl-tx-config = <&mtl_tx_emac0_setup>;
566 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
567 snps,clk-csr = <0>;
570 stmmac_axi_emac0_setup: stmmac-axi-config {
576 mtl_rx_emac0_setup: rx-queues-config {
577 snps,rx-queues-to-use = <8>;
578 snps,rx-sched-sp;
580 snps,dcb-algorithm;
581 snps,map-to-dma-channel = <0x0>;
584 snps,dcb-algorithm;
585 snps,map-to-dma-channel = <0x1>;
588 snps,dcb-algorithm;
589 snps,map-to-dma-channel = <0x2>;
592 snps,dcb-algorithm;
593 snps,map-to-dma-channel = <0x3>;
596 snps,dcb-algorithm;
597 snps,map-to-dma-channel = <0x4>;
600 snps,dcb-algorithm;
601 snps,map-to-dma-channel = <0x5>;
604 snps,dcb-algorithm;
605 snps,map-to-dma-channel = <0x6>;
608 snps,dcb-algorithm;
609 snps,map-to-dma-channel = <0x7>;
613 mtl_tx_emac0_setup: tx-queues-config {
614 snps,tx-queues-to-use = <8>;
615 snps,tx-sched-wrr;
618 snps,dcb-algorithm;
622 snps,dcb-algorithm;
626 snps,coe-unsupported;
627 snps,dcb-algorithm;
631 snps,coe-unsupported;
632 snps,dcb-algorithm;
636 snps,coe-unsupported;
637 snps,dcb-algorithm;
641 snps,coe-unsupported;
642 snps,dcb-algorithm;
646 snps,coe-unsupported;
647 snps,dcb-algorithm;
651 snps,coe-unsupported;
652 snps,dcb-algorithm;
658 compatible = "altr,socfpga-stmmac-agilex5",
659 "snps,dwxgmac-2.10";
662 interrupt-names = "macirq";
664 reset-names = "stmmaceth", "ahb";
667 clock-names = "stmmaceth", "ptp_ref";
668 mac-address = [00 00 00 00 00 00];
669 tx-fifo-depth = <32768>;
670 rx-fifo-depth = <16384>;
671 snps,multicast-filter-bins = <64>;
672 snps,perfect-filter-entries = <64>;
673 snps,axi-config = <&stmmac_axi_emac1_setup>;
674 snps,mtl-rx-config = <&mtl_rx_emac1_setup>;
675 snps,mtl-tx-config = <&mtl_tx_emac1_setup>;
678 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
679 snps,clk-csr = <0>;
682 stmmac_axi_emac1_setup: stmmac-axi-config {
688 mtl_rx_emac1_setup: rx-queues-config {
689 snps,rx-queues-to-use = <8>;
690 snps,rx-sched-sp;
692 snps,dcb-algorithm;
693 snps,map-to-dma-channel = <0x0>;
696 snps,dcb-algorithm;
697 snps,map-to-dma-channel = <0x1>;
700 snps,dcb-algorithm;
701 snps,map-to-dma-channel = <0x2>;
704 snps,dcb-algorithm;
705 snps,map-to-dma-channel = <0x3>;
708 snps,dcb-algorithm;
709 snps,map-to-dma-channel = <0x4>;
712 snps,dcb-algorithm;
713 snps,map-to-dma-channel = <0x5>;
716 snps,dcb-algorithm;
717 snps,map-to-dma-channel = <0x6>;
720 snps,dcb-algorithm;
721 snps,map-to-dma-channel = <0x7>;
725 mtl_tx_emac1_setup: tx-queues-config {
726 snps,tx-queues-to-use = <8>;
727 snps,tx-sched-wrr;
730 snps,dcb-algorithm;
734 snps,dcb-algorithm;
738 snps,coe-unsupported;
739 snps,dcb-algorithm;
743 snps,coe-unsupported;
744 snps,dcb-algorithm;
748 snps,coe-unsupported;
749 snps,dcb-algorithm;
753 snps,coe-unsupported;
754 snps,dcb-algorithm;
758 snps,coe-unsupported;
759 snps,dcb-algorithm;
763 snps,coe-unsupported;
764 snps,dcb-algorithm;
770 compatible = "altr,socfpga-stmmac-agilex5",
771 "snps,dwxgmac-2.10";
774 interrupt-names = "macirq";
776 reset-names = "stmmaceth", "ahb";
779 clock-names = "stmmaceth", "ptp_ref";
780 mac-address = [00 00 00 00 00 00];
781 tx-fifo-depth = <32768>;
782 rx-fifo-depth = <16384>;
783 snps,multicast-filter-bins = <64>;
784 snps,perfect-filter-entries = <64>;
785 snps,axi-config = <&stmmac_axi_emac2_setup>;
786 snps,mtl-rx-config = <&mtl_rx_emac2_setup>;
787 snps,mtl-tx-config = <&mtl_tx_emac2_setup>;
790 altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
791 snps,clk-csr = <0>;
794 stmmac_axi_emac2_setup: stmmac-axi-config {
800 mtl_rx_emac2_setup: rx-queues-config {
801 snps,rx-queues-to-use = <8>;
802 snps,rx-sched-sp;
804 snps,dcb-algorithm;
805 snps,map-to-dma-channel = <0x0>;
808 snps,dcb-algorithm;
809 snps,map-to-dma-channel = <0x1>;
812 snps,dcb-algorithm;
813 snps,map-to-dma-channel = <0x2>;
816 snps,dcb-algorithm;
817 snps,map-to-dma-channel = <0x3>;
820 snps,dcb-algorithm;
821 snps,map-to-dma-channel = <0x4>;
824 snps,dcb-algorithm;
825 snps,map-to-dma-channel = <0x5>;
828 snps,dcb-algorithm;
829 snps,map-to-dma-channel = <0x6>;
832 snps,dcb-algorithm;
833 snps,map-to-dma-channel = <0x7>;
837 mtl_tx_emac2_setup: tx-queues-config {
838 snps,tx-queues-to-use = <8>;
839 snps,tx-sched-wrr;
842 snps,dcb-algorithm;
846 snps,dcb-algorithm;
850 snps,coe-unsupported;
851 snps,dcb-algorithm;
855 snps,coe-unsupported;
856 snps,dcb-algorithm;
860 snps,coe-unsupported;
861 snps,dcb-algorithm;
865 snps,coe-unsupported;
866 snps,dcb-algorithm;
870 snps,coe-unsupported;
871 snps,dcb-algorithm;
875 snps,coe-unsupported;
876 snps,dcb-algorithm;
882 compatible = "arm,smmu-v3-pmcg";
885 interrupt-parent = <&intc>;
890 compatible = "arm,smmu-v3-pmcg";
893 interrupt-parent = <&intc>;
898 compatible = "arm,smmu-v3-pmcg";
901 interrupt-parent = <&intc>;
906 compatible = "arm,smmu-v3-pmcg";
909 interrupt-parent = <&intc>;
914 compatible = "arm,smmu-v3-pmcg";
917 interrupt-parent = <&intc>;
922 compatible = "arm,smmu-v3-pmcg";
925 interrupt-parent = <&intc>;
930 compatible = "arm,smmu-v3-pmcg";
933 interrupt-parent = <&intc>;