Lines Matching +full:socfpga +full:- +full:stmmac
1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
18 #address-cells = <2>;
19 #size-cells = <2>;
23 compatible = "shared-dma-pool";
26 no-map;
31 #address-cells = <1>;
32 #size-cells = <0>;
35 compatible = "arm,cortex-a53";
37 enable-method = "psci";
42 compatible = "arm,cortex-a53";
44 enable-method = "psci";
49 compatible = "arm,cortex-a53";
51 enable-method = "psci";
56 compatible = "arm,cortex-a53";
58 enable-method = "psci";
65 compatible = "intel,agilex-svc";
67 memory-region = <&service_reserved>;
69 fpga_mgr: fpga-mgr {
70 compatible = "intel,agilex-soc-fpga-mgr";
75 fpga-region {
76 compatible = "fpga-region";
77 #address-cells = <0x2>;
78 #size-cells = <0x2>;
79 fpga-mgr = <&fpga_mgr>;
83 compatible = "arm,cortex-a53-pmu";
88 interrupt-affinity = <&cpu0>,
92 interrupt-parent = <&intc>;
96 compatible = "arm,psci-0.2";
100 intc: interrupt-controller@fffc1000 {
101 compatible = "arm,gic-400", "arm,cortex-a15-gic";
102 #interrupt-cells = <3>;
103 interrupt-controller;
104 interrupt-parent = <&intc>;
114 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
115 #clock-cells = <0>;
116 compatible = "fixed-clock";
117 clock-frequency = <200000000>;
120 cb_intosc_ls_clk: cb-intosc-ls-clk {
121 #clock-cells = <0>;
122 compatible = "fixed-clock";
123 clock-frequency = <400000000>;
126 f2s_free_clk: f2s-free-clk {
127 #clock-cells = <0>;
128 compatible = "fixed-clock";
129 clock-frequency = <100000000>;
133 #clock-cells = <0>;
134 compatible = "fixed-clock";
137 qspi_clk: qspi-clk {
138 #clock-cells = <0>;
139 compatible = "fixed-clock";
140 clock-frequency = <200000000>;
145 compatible = "arm,armv8-timer";
146 interrupt-parent = <&intc>;
154 #phy-cells = <0>;
155 compatible = "usb-nop-xceiv";
159 #address-cells = <1>;
160 #size-cells = <1>;
161 compatible = "simple-bus";
163 interrupt-parent = <&intc>;
166 clkmgr: clock-controller@ffd10000 {
167 compatible = "intel,agilex-clkmgr";
169 #clock-cells = <1>;
173 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
176 interrupt-names = "macirq";
177 mac-address = [00 00 00 00 00 00];
179 reset-names = "stmmaceth", "ahb";
180 tx-fifo-depth = <16384>;
181 rx-fifo-depth = <16384>;
182 snps,multicast-filter-bins = <256>;
184 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
186 clock-names = "stmmaceth", "ptp_ref";
191 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
194 interrupt-names = "macirq";
195 mac-address = [00 00 00 00 00 00];
197 reset-names = "stmmaceth", "ahb";
198 tx-fifo-depth = <16384>;
199 rx-fifo-depth = <16384>;
200 snps,multicast-filter-bins = <256>;
202 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
204 clock-names = "stmmaceth", "ptp_ref";
209 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
212 interrupt-names = "macirq";
213 mac-address = [00 00 00 00 00 00];
215 reset-names = "stmmaceth", "ahb";
216 tx-fifo-depth = <16384>;
217 rx-fifo-depth = <16384>;
218 snps,multicast-filter-bins = <256>;
220 altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
222 clock-names = "stmmaceth", "ptp_ref";
227 #address-cells = <1>;
228 #size-cells = <0>;
229 compatible = "snps,dw-apb-gpio";
234 porta: gpio-controller@0 {
235 compatible = "snps,dw-apb-gpio-port";
236 gpio-controller;
237 #gpio-cells = <2>;
238 snps,nr-gpios = <24>;
240 interrupt-controller;
241 #interrupt-cells = <2>;
247 #address-cells = <1>;
248 #size-cells = <0>;
249 compatible = "snps,dw-apb-gpio";
254 portb: gpio-controller@0 {
255 compatible = "snps,dw-apb-gpio-port";
256 gpio-controller;
257 #gpio-cells = <2>;
258 snps,nr-gpios = <24>;
260 interrupt-controller;
261 #interrupt-cells = <2>;
267 #address-cells = <1>;
268 #size-cells = <0>;
269 compatible = "snps,designware-i2c";
278 #address-cells = <1>;
279 #size-cells = <0>;
280 compatible = "snps,designware-i2c";
289 #address-cells = <1>;
290 #size-cells = <0>;
291 compatible = "snps,designware-i2c";
300 #address-cells = <1>;
301 #size-cells = <0>;
302 compatible = "snps,designware-i2c";
311 #address-cells = <1>;
312 #size-cells = <0>;
313 compatible = "snps,designware-i2c";
322 #address-cells = <1>;
323 #size-cells = <0>;
324 compatible = "altr,socfpga-dw-mshc";
327 fifo-depth = <0x400>;
329 reset-names = "reset";
332 clock-names = "biu", "ciu";
334 altr,sysmgr-syscon = <&sysmgr 0x28 4>;
338 nand: nand-controller@ffb90000 {
339 #address-cells = <1>;
340 #size-cells = <0>;
341 compatible = "altr,socfpga-denali-nand";
344 reg-names = "nand_data", "denali_reg";
349 clock-names = "nand", "nand_x", "ecc";
355 compatible = "mmio-sram";
357 #address-cells = <1>;
358 #size-cells = <1>;
362 pdma: dma-controller@ffda0000 {
374 #dma-cells = <1>;
376 reset-names = "dma", "dma-ocp";
378 clock-names = "apb_pclk";
382 compatible = "pinctrl-single";
383 #pinctrl-cells = <1>;
385 pinctrl-single,register-width = <32>;
386 pinctrl-single,function-mask = <0x0000000f>;
390 compatible = "pinctrl-single";
391 #pinctrl-cells = <1>;
393 pinctrl-single,register-width = <32>;
397 compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr";
399 #reset-cells = <1>;
403 compatible = "arm,mmu-500", "arm,smmu-v2";
405 #global-interrupts = <2>;
406 #iommu-cells = <1>;
407 interrupt-parent = <&intc>;
410 /* Global Non-secure Fault */
412 /* Non-secure Context Interrupts (32) */
445 stream-match-mask = <0x7ff0>;
453 compatible = "snps,dw-apb-ssi";
454 #address-cells = <1>;
455 #size-cells = <0>;
459 reset-names = "spi";
460 reg-io-width = <4>;
461 num-cs = <4>;
464 dma-names = "tx", "rx";
469 compatible = "snps,dw-apb-ssi";
470 #address-cells = <1>;
471 #size-cells = <0>;
475 reset-names = "spi";
476 reg-io-width = <4>;
477 num-cs = <4>;
480 dma-names = "tx", "rx";
485 compatible = "altr,sys-mgr-s10","altr,sys-mgr";
490 compatible = "snps,dw-apb-timer";
494 clock-names = "timer";
498 compatible = "snps,dw-apb-timer";
502 clock-names = "timer";
506 compatible = "snps,dw-apb-timer";
510 clock-names = "timer";
514 compatible = "snps,dw-apb-timer";
518 clock-names = "timer";
522 compatible = "snps,dw-apb-uart";
525 reg-shift = <2>;
526 reg-io-width = <4>;
533 compatible = "snps,dw-apb-uart";
536 reg-shift = <2>;
537 reg-io-width = <4>;
544 compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
548 phy-names = "usb2-phy";
550 reset-names = "dwc2", "dwc2-ecc";
552 clock-names = "otg";
558 compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
562 phy-names = "usb2-phy";
564 reset-names = "dwc2", "dwc2-ecc";
571 compatible = "snps,dw-wdt";
580 compatible = "snps,dw-wdt";
589 compatible = "snps,dw-wdt";
598 compatible = "snps,dw-wdt";
607 compatible = "altr,sdr-ctl", "syscon";
612 compatible = "altr,socfpga-s10-ecc-manager",
613 "altr,socfpga-a10-ecc-manager";
614 altr,sysmgr-syscon = <&sysmgr>;
615 #address-cells = <1>;
616 #size-cells = <1>;
618 interrupt-controller;
619 #interrupt-cells = <2>;
623 compatible = "altr,sdram-edac-s10";
624 altr,sdr-syscon = <&sdr>;
628 ocram-ecc@ff8cc000 {
629 compatible = "altr,socfpga-s10-ocram-ecc",
630 "altr,socfpga-a10-ocram-ecc";
632 altr,ecc-parent = <&ocram>;
636 usb0-ecc@ff8c4000 {
637 compatible = "altr,socfpga-s10-usb-ecc",
638 "altr,socfpga-usb-ecc";
640 altr,ecc-parent = <&usb0>;
644 emac0-rx-ecc@ff8c0000 {
645 compatible = "altr,socfpga-s10-eth-mac-ecc",
646 "altr,socfpga-eth-mac-ecc";
648 altr,ecc-parent = <&gmac0>;
652 emac0-tx-ecc@ff8c0400 {
653 compatible = "altr,socfpga-s10-eth-mac-ecc",
654 "altr,socfpga-eth-mac-ecc";
656 altr,ecc-parent = <&gmac0>;
660 sdmmca-ecc@ff8c8c00 {
661 compatible = "altr,socfpga-s10-sdmmc-ecc",
662 "altr,socfpga-sdmmc-ecc";
664 altr,ecc-parent = <&mmc>;
671 compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
672 #address-cells = <1>;
673 #size-cells = <0>;
677 cdns,fifo-depth = <128>;
678 cdns,fifo-width = <4>;
679 cdns,trigger-address = <0x00000000>;