Lines Matching +full:rst +full:- +full:mgr
1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
18 #address-cells = <2>;
19 #size-cells = <2>;
23 compatible = "shared-dma-pool";
26 no-map;
31 #address-cells = <1>;
32 #size-cells = <0>;
35 compatible = "arm,cortex-a53";
37 enable-method = "psci";
42 compatible = "arm,cortex-a53";
44 enable-method = "psci";
49 compatible = "arm,cortex-a53";
51 enable-method = "psci";
56 compatible = "arm,cortex-a53";
58 enable-method = "psci";
65 compatible = "intel,agilex-svc";
67 memory-region = <&service_reserved>;
69 fpga_mgr: fpga-mgr {
70 compatible = "intel,agilex-soc-fpga-mgr";
75 fpga-region {
76 compatible = "fpga-region";
77 #address-cells = <0x2>;
78 #size-cells = <0x2>;
79 fpga-mgr = <&fpga_mgr>;
83 compatible = "arm,cortex-a53-pmu";
88 interrupt-affinity = <&cpu0>,
92 interrupt-parent = <&intc>;
96 compatible = "arm,psci-0.2";
100 intc: interrupt-controller@fffc1000 {
101 compatible = "arm,gic-400", "arm,cortex-a15-gic";
102 #interrupt-cells = <3>;
103 interrupt-controller;
111 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
112 #clock-cells = <0>;
113 compatible = "fixed-clock";
116 cb_intosc_ls_clk: cb-intosc-ls-clk {
117 #clock-cells = <0>;
118 compatible = "fixed-clock";
121 f2s_free_clk: f2s-free-clk {
122 #clock-cells = <0>;
123 compatible = "fixed-clock";
127 #clock-cells = <0>;
128 compatible = "fixed-clock";
131 qspi_clk: qspi-clk {
132 #clock-cells = <0>;
133 compatible = "fixed-clock";
134 clock-frequency = <200000000>;
139 compatible = "arm,armv8-timer";
140 interrupt-parent = <&intc>;
148 #phy-cells = <0>;
149 compatible = "usb-nop-xceiv";
153 #address-cells = <1>;
154 #size-cells = <1>;
155 compatible = "simple-bus";
157 interrupt-parent = <&intc>;
160 clkmgr: clock-controller@ffd10000 {
161 compatible = "intel,agilex-clkmgr";
163 #clock-cells = <1>;
167 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
170 interrupt-names = "macirq";
171 mac-address = [00 00 00 00 00 00];
172 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
173 reset-names = "stmmaceth", "ahb";
174 tx-fifo-depth = <16384>;
175 rx-fifo-depth = <16384>;
176 snps,multicast-filter-bins = <256>;
178 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
180 clock-names = "stmmaceth", "ptp_ref";
185 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
188 interrupt-names = "macirq";
189 mac-address = [00 00 00 00 00 00];
190 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
191 reset-names = "stmmaceth", "ahb";
192 tx-fifo-depth = <16384>;
193 rx-fifo-depth = <16384>;
194 snps,multicast-filter-bins = <256>;
196 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
198 clock-names = "stmmaceth", "ptp_ref";
203 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
206 interrupt-names = "macirq";
207 mac-address = [00 00 00 00 00 00];
208 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
209 reset-names = "stmmaceth", "ahb";
210 tx-fifo-depth = <16384>;
211 rx-fifo-depth = <16384>;
212 snps,multicast-filter-bins = <256>;
214 altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
216 clock-names = "stmmaceth", "ptp_ref";
221 #address-cells = <1>;
222 #size-cells = <0>;
223 compatible = "snps,dw-apb-gpio";
225 resets = <&rst GPIO0_RESET>;
228 porta: gpio-controller@0 {
229 compatible = "snps,dw-apb-gpio-port";
230 gpio-controller;
231 #gpio-cells = <2>;
232 snps,nr-gpios = <24>;
234 interrupt-controller;
235 #interrupt-cells = <2>;
241 #address-cells = <1>;
242 #size-cells = <0>;
243 compatible = "snps,dw-apb-gpio";
245 resets = <&rst GPIO1_RESET>;
248 portb: gpio-controller@0 {
249 compatible = "snps,dw-apb-gpio-port";
250 gpio-controller;
251 #gpio-cells = <2>;
252 snps,nr-gpios = <24>;
254 interrupt-controller;
255 #interrupt-cells = <2>;
261 #address-cells = <1>;
262 #size-cells = <0>;
263 compatible = "snps,designware-i2c";
266 resets = <&rst I2C0_RESET>;
272 #address-cells = <1>;
273 #size-cells = <0>;
274 compatible = "snps,designware-i2c";
277 resets = <&rst I2C1_RESET>;
283 #address-cells = <1>;
284 #size-cells = <0>;
285 compatible = "snps,designware-i2c";
288 resets = <&rst I2C2_RESET>;
294 #address-cells = <1>;
295 #size-cells = <0>;
296 compatible = "snps,designware-i2c";
299 resets = <&rst I2C3_RESET>;
305 #address-cells = <1>;
306 #size-cells = <0>;
307 compatible = "snps,designware-i2c";
310 resets = <&rst I2C4_RESET>;
316 #address-cells = <1>;
317 #size-cells = <0>;
318 compatible = "altr,socfpga-dw-mshc";
321 fifo-depth = <0x400>;
322 resets = <&rst SDMMC_RESET>;
323 reset-names = "reset";
326 clock-names = "biu", "ciu";
328 altr,sysmgr-syscon = <&sysmgr 0x28 4>;
332 nand: nand-controller@ffb90000 {
333 #address-cells = <1>;
334 #size-cells = <0>;
335 compatible = "altr,socfpga-denali-nand";
338 reg-names = "nand_data", "denali_reg";
343 clock-names = "nand", "nand_x", "ecc";
344 resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
349 compatible = "mmio-sram";
351 #address-cells = <1>;
352 #size-cells = <1>;
356 pdma: dma-controller@ffda0000 {
368 #dma-cells = <1>;
369 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
370 reset-names = "dma", "dma-ocp";
372 clock-names = "apb_pclk";
376 compatible = "pinctrl-single";
377 #pinctrl-cells = <1>;
379 pinctrl-single,register-width = <32>;
380 pinctrl-single,function-mask = <0x0000000f>;
384 compatible = "pinctrl-single";
385 #pinctrl-cells = <1>;
387 pinctrl-single,register-width = <32>;
390 rst: rstmgr@ffd11000 { label
391 compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr";
393 #reset-cells = <1>;
397 compatible = "arm,mmu-500", "arm,smmu-v2";
399 #global-interrupts = <2>;
400 #iommu-cells = <1>;
401 interrupt-parent = <&intc>;
404 /* Global Non-secure Fault */
406 /* Non-secure Context Interrupts (32) */
439 stream-match-mask = <0x7ff0>;
447 compatible = "snps,dw-apb-ssi";
448 #address-cells = <1>;
449 #size-cells = <0>;
452 resets = <&rst SPIM0_RESET>;
453 reset-names = "spi";
454 reg-io-width = <4>;
455 num-cs = <4>;
461 compatible = "snps,dw-apb-ssi";
462 #address-cells = <1>;
463 #size-cells = <0>;
466 resets = <&rst SPIM1_RESET>;
467 reset-names = "spi";
468 reg-io-width = <4>;
469 num-cs = <4>;
475 compatible = "altr,sys-mgr-s10","altr,sys-mgr";
480 compatible = "snps,dw-apb-timer";
484 clock-names = "timer";
488 compatible = "snps,dw-apb-timer";
492 clock-names = "timer";
496 compatible = "snps,dw-apb-timer";
500 clock-names = "timer";
504 compatible = "snps,dw-apb-timer";
508 clock-names = "timer";
512 compatible = "snps,dw-apb-uart";
515 reg-shift = <2>;
516 reg-io-width = <4>;
517 resets = <&rst UART0_RESET>;
523 compatible = "snps,dw-apb-uart";
526 reg-shift = <2>;
527 reg-io-width = <4>;
528 resets = <&rst UART1_RESET>;
534 compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
538 phy-names = "usb2-phy";
539 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
540 reset-names = "dwc2", "dwc2-ecc";
542 clock-names = "otg";
548 compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
552 phy-names = "usb2-phy";
553 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
554 reset-names = "dwc2", "dwc2-ecc";
561 compatible = "snps,dw-wdt";
564 resets = <&rst WATCHDOG0_RESET>;
570 compatible = "snps,dw-wdt";
573 resets = <&rst WATCHDOG1_RESET>;
579 compatible = "snps,dw-wdt";
582 resets = <&rst WATCHDOG2_RESET>;
588 compatible = "snps,dw-wdt";
591 resets = <&rst WATCHDOG3_RESET>;
597 compatible = "altr,sdr-ctl", "syscon";
602 compatible = "altr,socfpga-s10-ecc-manager",
603 "altr,socfpga-a10-ecc-manager";
604 altr,sysmgr-syscon = <&sysmgr>;
605 #address-cells = <1>;
606 #size-cells = <1>;
608 interrupt-controller;
609 #interrupt-cells = <2>;
613 compatible = "altr,sdram-edac-s10";
614 altr,sdr-syscon = <&sdr>;
618 ocram-ecc@ff8cc000 {
619 compatible = "altr,socfpga-s10-ocram-ecc",
620 "altr,socfpga-a10-ocram-ecc";
622 altr,ecc-parent = <&ocram>;
626 usb0-ecc@ff8c4000 {
627 compatible = "altr,socfpga-s10-usb-ecc",
628 "altr,socfpga-usb-ecc";
630 altr,ecc-parent = <&usb0>;
634 emac0-rx-ecc@ff8c0000 {
635 compatible = "altr,socfpga-s10-eth-mac-ecc",
636 "altr,socfpga-eth-mac-ecc";
638 altr,ecc-parent = <&gmac0>;
642 emac0-tx-ecc@ff8c0400 {
643 compatible = "altr,socfpga-s10-eth-mac-ecc",
644 "altr,socfpga-eth-mac-ecc";
646 altr,ecc-parent = <&gmac0>;
650 sdmmca-ecc@ff8c8c00 {
651 compatible = "altr,socfpga-s10-sdmmc-ecc",
652 "altr,socfpga-sdmmc-ecc";
654 altr,ecc-parent = <&mmc>;
661 compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
662 #address-cells = <1>;
663 #size-cells = <0>;
667 cdns,fifo-depth = <128>;
668 cdns,fifo-width = <4>;
669 cdns,trigger-address = <0x00000000>;