Lines Matching +full:smmu +full:- +full:v3
1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
269 compatible = "arm,cortex-a72";
271 enable-method = "psci";
272 next-level-cache = <&cluster0_l2>;
273 numa-node-id = <0>;
278 compatible = "arm,cortex-a72";
280 enable-method = "psci";
281 next-level-cache = <&cluster0_l2>;
282 numa-node-id = <0>;
287 compatible = "arm,cortex-a72";
289 enable-method = "psci";
290 next-level-cache = <&cluster0_l2>;
291 numa-node-id = <0>;
296 compatible = "arm,cortex-a72";
298 enable-method = "psci";
299 next-level-cache = <&cluster0_l2>;
300 numa-node-id = <0>;
305 compatible = "arm,cortex-a72";
307 enable-method = "psci";
308 next-level-cache = <&cluster1_l2>;
309 numa-node-id = <0>;
314 compatible = "arm,cortex-a72";
316 enable-method = "psci";
317 next-level-cache = <&cluster1_l2>;
318 numa-node-id = <0>;
323 compatible = "arm,cortex-a72";
325 enable-method = "psci";
326 next-level-cache = <&cluster1_l2>;
327 numa-node-id = <0>;
332 compatible = "arm,cortex-a72";
334 enable-method = "psci";
335 next-level-cache = <&cluster1_l2>;
336 numa-node-id = <0>;
341 compatible = "arm,cortex-a72";
343 enable-method = "psci";
344 next-level-cache = <&cluster2_l2>;
345 numa-node-id = <0>;
350 compatible = "arm,cortex-a72";
352 enable-method = "psci";
353 next-level-cache = <&cluster2_l2>;
354 numa-node-id = <0>;
359 compatible = "arm,cortex-a72";
361 enable-method = "psci";
362 next-level-cache = <&cluster2_l2>;
363 numa-node-id = <0>;
368 compatible = "arm,cortex-a72";
370 enable-method = "psci";
371 next-level-cache = <&cluster2_l2>;
372 numa-node-id = <0>;
377 compatible = "arm,cortex-a72";
379 enable-method = "psci";
380 next-level-cache = <&cluster3_l2>;
381 numa-node-id = <0>;
386 compatible = "arm,cortex-a72";
388 enable-method = "psci";
389 next-level-cache = <&cluster3_l2>;
390 numa-node-id = <0>;
395 compatible = "arm,cortex-a72";
397 enable-method = "psci";
398 next-level-cache = <&cluster3_l2>;
399 numa-node-id = <0>;
404 compatible = "arm,cortex-a72";
406 enable-method = "psci";
407 next-level-cache = <&cluster3_l2>;
408 numa-node-id = <0>;
413 compatible = "arm,cortex-a72";
415 enable-method = "psci";
416 next-level-cache = <&cluster4_l2>;
417 numa-node-id = <1>;
422 compatible = "arm,cortex-a72";
424 enable-method = "psci";
425 next-level-cache = <&cluster4_l2>;
426 numa-node-id = <1>;
431 compatible = "arm,cortex-a72";
433 enable-method = "psci";
434 next-level-cache = <&cluster4_l2>;
435 numa-node-id = <1>;
440 compatible = "arm,cortex-a72";
442 enable-method = "psci";
443 next-level-cache = <&cluster4_l2>;
444 numa-node-id = <1>;
449 compatible = "arm,cortex-a72";
451 enable-method = "psci";
452 next-level-cache = <&cluster5_l2>;
453 numa-node-id = <1>;
458 compatible = "arm,cortex-a72";
460 enable-method = "psci";
461 next-level-cache = <&cluster5_l2>;
462 numa-node-id = <1>;
467 compatible = "arm,cortex-a72";
469 enable-method = "psci";
470 next-level-cache = <&cluster5_l2>;
471 numa-node-id = <1>;
476 compatible = "arm,cortex-a72";
478 enable-method = "psci";
479 next-level-cache = <&cluster5_l2>;
480 numa-node-id = <1>;
485 compatible = "arm,cortex-a72";
487 enable-method = "psci";
488 next-level-cache = <&cluster6_l2>;
489 numa-node-id = <1>;
494 compatible = "arm,cortex-a72";
496 enable-method = "psci";
497 next-level-cache = <&cluster6_l2>;
498 numa-node-id = <1>;
503 compatible = "arm,cortex-a72";
505 enable-method = "psci";
506 next-level-cache = <&cluster6_l2>;
507 numa-node-id = <1>;
512 compatible = "arm,cortex-a72";
514 enable-method = "psci";
515 next-level-cache = <&cluster6_l2>;
516 numa-node-id = <1>;
521 compatible = "arm,cortex-a72";
523 enable-method = "psci";
524 next-level-cache = <&cluster7_l2>;
525 numa-node-id = <1>;
530 compatible = "arm,cortex-a72";
532 enable-method = "psci";
533 next-level-cache = <&cluster7_l2>;
534 numa-node-id = <1>;
539 compatible = "arm,cortex-a72";
541 enable-method = "psci";
542 next-level-cache = <&cluster7_l2>;
543 numa-node-id = <1>;
548 compatible = "arm,cortex-a72";
550 enable-method = "psci";
551 next-level-cache = <&cluster7_l2>;
552 numa-node-id = <1>;
557 compatible = "arm,cortex-a72";
559 enable-method = "psci";
560 next-level-cache = <&cluster8_l2>;
561 numa-node-id = <2>;
566 compatible = "arm,cortex-a72";
568 enable-method = "psci";
569 next-level-cache = <&cluster8_l2>;
570 numa-node-id = <2>;
575 compatible = "arm,cortex-a72";
577 enable-method = "psci";
578 next-level-cache = <&cluster8_l2>;
579 numa-node-id = <2>;
584 compatible = "arm,cortex-a72";
586 enable-method = "psci";
587 next-level-cache = <&cluster8_l2>;
588 numa-node-id = <2>;
593 compatible = "arm,cortex-a72";
595 enable-method = "psci";
596 next-level-cache = <&cluster9_l2>;
597 numa-node-id = <2>;
602 compatible = "arm,cortex-a72";
604 enable-method = "psci";
605 next-level-cache = <&cluster9_l2>;
606 numa-node-id = <2>;
611 compatible = "arm,cortex-a72";
613 enable-method = "psci";
614 next-level-cache = <&cluster9_l2>;
615 numa-node-id = <2>;
620 compatible = "arm,cortex-a72";
622 enable-method = "psci";
623 next-level-cache = <&cluster9_l2>;
624 numa-node-id = <2>;
629 compatible = "arm,cortex-a72";
631 enable-method = "psci";
632 next-level-cache = <&cluster10_l2>;
633 numa-node-id = <2>;
638 compatible = "arm,cortex-a72";
640 enable-method = "psci";
641 next-level-cache = <&cluster10_l2>;
642 numa-node-id = <2>;
647 compatible = "arm,cortex-a72";
649 enable-method = "psci";
650 next-level-cache = <&cluster10_l2>;
651 numa-node-id = <2>;
656 compatible = "arm,cortex-a72";
658 enable-method = "psci";
659 next-level-cache = <&cluster10_l2>;
660 numa-node-id = <2>;
665 compatible = "arm,cortex-a72";
667 enable-method = "psci";
668 next-level-cache = <&cluster11_l2>;
669 numa-node-id = <2>;
674 compatible = "arm,cortex-a72";
676 enable-method = "psci";
677 next-level-cache = <&cluster11_l2>;
678 numa-node-id = <2>;
683 compatible = "arm,cortex-a72";
685 enable-method = "psci";
686 next-level-cache = <&cluster11_l2>;
687 numa-node-id = <2>;
692 compatible = "arm,cortex-a72";
694 enable-method = "psci";
695 next-level-cache = <&cluster11_l2>;
696 numa-node-id = <2>;
701 compatible = "arm,cortex-a72";
703 enable-method = "psci";
704 next-level-cache = <&cluster12_l2>;
705 numa-node-id = <3>;
710 compatible = "arm,cortex-a72";
712 enable-method = "psci";
713 next-level-cache = <&cluster12_l2>;
714 numa-node-id = <3>;
719 compatible = "arm,cortex-a72";
721 enable-method = "psci";
722 next-level-cache = <&cluster12_l2>;
723 numa-node-id = <3>;
728 compatible = "arm,cortex-a72";
730 enable-method = "psci";
731 next-level-cache = <&cluster12_l2>;
732 numa-node-id = <3>;
737 compatible = "arm,cortex-a72";
739 enable-method = "psci";
740 next-level-cache = <&cluster13_l2>;
741 numa-node-id = <3>;
746 compatible = "arm,cortex-a72";
748 enable-method = "psci";
749 next-level-cache = <&cluster13_l2>;
750 numa-node-id = <3>;
755 compatible = "arm,cortex-a72";
757 enable-method = "psci";
758 next-level-cache = <&cluster13_l2>;
759 numa-node-id = <3>;
764 compatible = "arm,cortex-a72";
766 enable-method = "psci";
767 next-level-cache = <&cluster13_l2>;
768 numa-node-id = <3>;
773 compatible = "arm,cortex-a72";
775 enable-method = "psci";
776 next-level-cache = <&cluster14_l2>;
777 numa-node-id = <3>;
782 compatible = "arm,cortex-a72";
784 enable-method = "psci";
785 next-level-cache = <&cluster14_l2>;
786 numa-node-id = <3>;
791 compatible = "arm,cortex-a72";
793 enable-method = "psci";
794 next-level-cache = <&cluster14_l2>;
795 numa-node-id = <3>;
800 compatible = "arm,cortex-a72";
802 enable-method = "psci";
803 next-level-cache = <&cluster14_l2>;
804 numa-node-id = <3>;
809 compatible = "arm,cortex-a72";
811 enable-method = "psci";
812 next-level-cache = <&cluster15_l2>;
813 numa-node-id = <3>;
818 compatible = "arm,cortex-a72";
820 enable-method = "psci";
821 next-level-cache = <&cluster15_l2>;
822 numa-node-id = <3>;
827 compatible = "arm,cortex-a72";
829 enable-method = "psci";
830 next-level-cache = <&cluster15_l2>;
831 numa-node-id = <3>;
836 compatible = "arm,cortex-a72";
838 enable-method = "psci";
839 next-level-cache = <&cluster15_l2>;
840 numa-node-id = <3>;
843 cluster0_l2: l2-cache0 {
845 cache-level = <2>;
846 cache-unified;
849 cluster1_l2: l2-cache1 {
851 cache-level = <2>;
852 cache-unified;
855 cluster2_l2: l2-cache2 {
857 cache-level = <2>;
858 cache-unified;
861 cluster3_l2: l2-cache3 {
863 cache-level = <2>;
864 cache-unified;
867 cluster4_l2: l2-cache4 {
869 cache-level = <2>;
870 cache-unified;
873 cluster5_l2: l2-cache5 {
875 cache-level = <2>;
876 cache-unified;
879 cluster6_l2: l2-cache6 {
881 cache-level = <2>;
882 cache-unified;
885 cluster7_l2: l2-cache7 {
887 cache-level = <2>;
888 cache-unified;
891 cluster8_l2: l2-cache8 {
893 cache-level = <2>;
894 cache-unified;
897 cluster9_l2: l2-cache9 {
899 cache-level = <2>;
900 cache-unified;
903 cluster10_l2: l2-cache10 {
905 cache-level = <2>;
906 cache-unified;
909 cluster11_l2: l2-cache11 {
911 cache-level = <2>;
912 cache-unified;
915 cluster12_l2: l2-cache12 {
917 cache-level = <2>;
918 cache-unified;
921 cluster13_l2: l2-cache13 {
923 cache-level = <2>;
924 cache-unified;
927 cluster14_l2: l2-cache14 {
929 cache-level = <2>;
930 cache-unified;
933 cluster15_l2: l2-cache15 {
935 cache-level = <2>;
936 cache-unified;
940 gic: interrupt-controller@4d000000 {
941 compatible = "arm,gic-v3";
942 #interrupt-cells = <3>;
943 #address-cells = <2>;
944 #size-cells = <2>;
946 interrupt-controller;
947 #redistributor-regions = <4>;
948 redistributor-stride = <0x0 0x40000>;
959 p0_its_peri_a: msi-controller@4c000000 {
960 compatible = "arm,gic-v3-its";
961 msi-controller;
962 #msi-cells = <1>;
966 p0_its_peri_b: msi-controller@6c000000 {
967 compatible = "arm,gic-v3-its";
968 msi-controller;
969 #msi-cells = <1>;
973 p0_its_dsa_a: msi-controller@c6000000 {
974 compatible = "arm,gic-v3-its";
975 msi-controller;
976 #msi-cells = <1>;
980 p0_its_dsa_b: msi-controller@8c6000000 {
981 compatible = "arm,gic-v3-its";
982 msi-controller;
983 #msi-cells = <1>;
987 p1_its_peri_a: msi-controller@4004c000000 {
988 compatible = "arm,gic-v3-its";
989 msi-controller;
990 #msi-cells = <1>;
994 p1_its_peri_b: msi-controller@4006c000000 {
995 compatible = "arm,gic-v3-its";
996 msi-controller;
997 #msi-cells = <1>;
1001 p1_its_dsa_a: msi-controller@400c6000000 {
1002 compatible = "arm,gic-v3-its";
1003 msi-controller;
1004 #msi-cells = <1>;
1008 p1_its_dsa_b: msi-controller@408c6000000 {
1009 compatible = "arm,gic-v3-its";
1010 msi-controller;
1011 #msi-cells = <1>;
1016 eth0: ethernet-0 {
1017 compatible = "hisilicon,hns-nic-v2";
1018 ae-handle = <&dsaf0>;
1019 port-idx-in-ae = <4>;
1020 local-mac-address = [00 00 00 00 00 00];
1022 dma-coherent;
1025 eth1: ethernet-1 {
1026 compatible = "hisilicon,hns-nic-v2";
1027 ae-handle = <&dsaf0>;
1028 port-idx-in-ae = <5>;
1029 local-mac-address = [00 00 00 00 00 00];
1031 dma-coherent;
1034 eth2: ethernet-2 {
1035 compatible = "hisilicon,hns-nic-v2";
1036 ae-handle = <&dsaf0>;
1037 port-idx-in-ae = <0>;
1038 local-mac-address = [00 00 00 00 00 00];
1040 dma-coherent;
1043 eth3: ethernet-3 {
1044 compatible = "hisilicon,hns-nic-v2";
1045 ae-handle = <&dsaf0>;
1046 port-idx-in-ae = <1>;
1047 local-mac-address = [00 00 00 00 00 00];
1049 dma-coherent;
1053 compatible = "arm,armv8-timer";
1061 compatible = "arm,cortex-a72-pmu";
1065 p0_mbigen_peri_b: interrupt-controller@60080000 {
1066 compatible = "hisilicon,mbigen-v2";
1070 msi-parent = <&p0_its_peri_b 0x120c7>;
1071 interrupt-controller;
1072 #interrupt-cells = <2>;
1073 num-pins = <1>;
1077 p0_mbigen_pcie_a: interrupt-controller@a0080000 {
1078 compatible = "hisilicon,mbigen-v2";
1082 msi-parent = <&p0_its_dsa_a 0x40087>;
1083 interrupt-controller;
1084 #interrupt-cells = <2>;
1085 num-pins = <10>;
1089 msi-parent = <&p0_its_dsa_a 0x40000>;
1090 interrupt-controller;
1091 #interrupt-cells = <2>;
1092 num-pins = <128>;
1096 msi-parent = <&p0_its_dsa_a 0x40040>;
1097 interrupt-controller;
1098 #interrupt-cells = <2>;
1099 num-pins = <128>;
1103 msi-parent = <&p0_its_dsa_a 0x40b0c>;
1104 interrupt-controller;
1105 #interrupt-cells = <2>;
1106 num-pins = <3>;
1110 msi-parent = <&p0_its_dsa_a 0x40080>;
1111 interrupt-controller;
1112 #interrupt-cells = <2>;
1113 num-pins = <2>;
1116 p0_mbigen_alg_a:interrupt-controller@d0080000 {
1117 compatible = "hisilicon,mbigen-v2";
1121 msi-parent = <&p0_its_dsa_a 0x40400>;
1122 interrupt-controller;
1123 #interrupt-cells = <2>;
1124 num-pins = <33>;
1127 msi-parent = <&p0_its_dsa_a 0x40b1b>;
1128 interrupt-controller;
1129 #interrupt-cells = <2>;
1130 num-pins = <3>;
1133 p0_mbigen_alg_b:interrupt-controller@8,d0080000 {
1134 compatible = "hisilicon,mbigen-v2";
1138 msi-parent = <&p0_its_dsa_b 0x42400>;
1139 interrupt-controller;
1140 #interrupt-cells = <2>;
1141 num-pins = <33>;
1144 msi-parent = <&p0_its_dsa_b 0x42b1b>;
1145 interrupt-controller;
1146 #interrupt-cells = <2>;
1147 num-pins = <3>;
1150 p1_mbigen_alg_a:interrupt-controller@400,d0080000 {
1151 compatible = "hisilicon,mbigen-v2";
1155 msi-parent = <&p1_its_dsa_a 0x44400>;
1156 interrupt-controller;
1157 #interrupt-cells = <2>;
1158 num-pins = <33>;
1161 msi-parent = <&p1_its_dsa_a 0x44b1b>;
1162 interrupt-controller;
1163 #interrupt-cells = <2>;
1164 num-pins = <3>;
1167 p1_mbigen_alg_b:interrupt-controller@408,d0080000 {
1168 compatible = "hisilicon,mbigen-v2";
1172 msi-parent = <&p1_its_dsa_b 0x46400>;
1173 interrupt-controller;
1174 #interrupt-cells = <2>;
1175 num-pins = <33>;
1178 msi-parent = <&p1_its_dsa_b 0x46b1b>;
1179 interrupt-controller;
1180 #interrupt-cells = <2>;
1181 num-pins = <3>;
1184 p0_mbigen_dsa_a: interrupt-controller@c0080000 {
1185 compatible = "hisilicon,mbigen-v2";
1189 msi-parent = <&p0_its_dsa_a 0x40800>;
1190 interrupt-controller;
1191 #interrupt-cells = <2>;
1192 num-pins = <409>;
1195 mbigen_dsa_roce: intc-roce {
1196 msi-parent = <&p0_its_dsa_a 0x40B1E>;
1197 interrupt-controller;
1198 #interrupt-cells = <2>;
1199 num-pins = <34>;
1202 mbigen_sas0: intc-sas0 {
1203 msi-parent = <&p0_its_dsa_a 0x40900>;
1204 interrupt-controller;
1205 #interrupt-cells = <2>;
1206 num-pins = <128>;
1210 msi-parent = <&p0_its_dsa_a 0x40b20>;
1211 interrupt-controller;
1212 #interrupt-cells = <2>;
1213 num-pins = <3>;
1224 * have a SMMU translation for MSI. In order to workaround this,
1227 * systems. Hence please make sure that the smmu pcie node on
1229 * when iommu-map entry is used along with the PCIe node.
1230 * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html
1233 compatible = "arm,smmu-v3";
1235 #iommu-cells = <1>;
1236 dma-coherent;
1237 hisilicon,broken-prefetch-cmd;
1241 compatible = "arm,smmu-v3";
1243 interrupt-parent = <&p0_mbigen_smmu_alg_a>;
1247 interrupt-names = "eventq", "gerror", "priq";
1248 #iommu-cells = <1>;
1249 dma-coherent;
1250 hisilicon,broken-prefetch-cmd;
1253 compatible = "arm,smmu-v3";
1255 interrupt-parent = <&p0_mbigen_smmu_alg_b>;
1259 interrupt-names = "eventq", "gerror", "priq";
1260 #iommu-cells = <1>;
1261 dma-coherent;
1262 hisilicon,broken-prefetch-cmd;
1265 compatible = "arm,smmu-v3";
1267 interrupt-parent = <&p1_mbigen_smmu_alg_a>;
1271 interrupt-names = "eventq", "gerror", "priq";
1272 #iommu-cells = <1>;
1273 dma-coherent;
1274 hisilicon,broken-prefetch-cmd;
1277 compatible = "arm,smmu-v3";
1279 interrupt-parent = <&p1_mbigen_smmu_alg_b>;
1283 interrupt-names = "eventq", "gerror", "priq";
1284 #iommu-cells = <1>;
1285 dma-coherent;
1286 hisilicon,broken-prefetch-cmd;
1290 compatible = "simple-bus";
1291 #address-cells = <2>;
1292 #size-cells = <2>;
1296 compatible = "hisilicon,hip07-lpc";
1297 #size-cells = <1>;
1298 #address-cells = <2>;
1302 compatible = "ipmi-bt";
1310 compatible = "arm,sbsa-uart";
1312 interrupt-parent = <&mbigen_uart>;
1314 current-speed = <115200>;
1315 reg-io-width = <4>;
1320 compatible = "generic-ohci";
1322 interrupt-parent = <&mbigen_usb>;
1324 dma-coherent;
1329 compatible = "generic-ehci";
1331 interrupt-parent = <&mbigen_usb>;
1333 dma-coherent;
1338 compatible = "hisilicon,peri-subctrl","syscon";
1343 compatible = "hisilicon,dsa-subctrl", "syscon";
1350 reg-io-width = <2>;
1354 compatible = "hisilicon,pcie-sas-subctrl", "syscon";
1364 compatible = "hisilicon,hns-mdio";
1366 subctrl-vbase = <&peri_c_subctrl 0x338 0xa38
1368 #address-cells = <1>;
1369 #size-cells = <0>;
1371 phy0: ethernet-phy@0 {
1372 compatible = "ethernet-phy-ieee802.3-c22";
1376 phy1: ethernet-phy@1 {
1377 compatible = "ethernet-phy-ieee802.3-c22";
1383 #address-cells = <1>;
1384 #size-cells = <0>;
1385 compatible = "hisilicon,hns-dsaf-v2";
1386 mode = "6port-16rss";
1389 reg-names = "ppe-base", "dsaf-base";
1390 interrupt-parent = <&mbigen_dsaf0>;
1391 subctrl-syscon = <&dsa_subctrl>;
1392 reset-field-offset = <0>;
1477 desc-num = <0x400>;
1478 buf-size = <0x1000>;
1479 dma-coherent;
1483 serdes-syscon = <&serdes_ctrl>;
1484 cpld-syscon = <&dsa_cpld 0x0>;
1485 port-rst-offset = <0>;
1486 port-mode-offset = <0>;
1487 mc-mac-mask = [ff f0 00 00 00 00];
1488 media-type = "fiber";
1493 serdes-syscon = <&serdes_ctrl>;
1494 cpld-syscon = <&dsa_cpld 0x4>;
1495 port-rst-offset = <1>;
1496 port-mode-offset = <1>;
1497 mc-mac-mask = [ff f0 00 00 00 00];
1498 media-type = "fiber";
1503 phy-handle = <&phy0>;
1504 serdes-syscon = <&serdes_ctrl>;
1505 port-rst-offset = <4>;
1506 port-mode-offset = <2>;
1507 mc-mac-mask = [ff f0 00 00 00 00];
1508 media-type = "copper";
1513 phy-handle = <&phy1>;
1514 serdes-syscon = <&serdes_ctrl>;
1515 port-rst-offset = <5>;
1516 port-mode-offset = <3>;
1517 mc-mac-mask = [ff f0 00 00 00 00];
1518 media-type = "copper";
1523 compatible = "hisilicon,hns-roce-v1";
1525 dma-coherent;
1526 eth-handle = <ð2 ð3 0 0 ð0 ð1>;
1527 dsaf-handle = <&dsaf0>;
1528 node-guid = [00 9A CD 00 00 01 02 03];
1529 #address-cells = <2>;
1530 #size-cells = <2>;
1531 interrupt-parent = <&mbigen_dsa_roce>;
1567 interrupt-names = "hns-roce-comp-0",
1568 "hns-roce-comp-1",
1569 "hns-roce-comp-2",
1570 "hns-roce-comp-3",
1571 "hns-roce-comp-4",
1572 "hns-roce-comp-5",
1573 "hns-roce-comp-6",
1574 "hns-roce-comp-7",
1575 "hns-roce-comp-8",
1576 "hns-roce-comp-9",
1577 "hns-roce-comp-10",
1578 "hns-roce-comp-11",
1579 "hns-roce-comp-12",
1580 "hns-roce-comp-13",
1581 "hns-roce-comp-14",
1582 "hns-roce-comp-15",
1583 "hns-roce-comp-16",
1584 "hns-roce-comp-17",
1585 "hns-roce-comp-18",
1586 "hns-roce-comp-19",
1587 "hns-roce-comp-20",
1588 "hns-roce-comp-21",
1589 "hns-roce-comp-22",
1590 "hns-roce-comp-23",
1591 "hns-roce-comp-24",
1592 "hns-roce-comp-25",
1593 "hns-roce-comp-26",
1594 "hns-roce-comp-27",
1595 "hns-roce-comp-28",
1596 "hns-roce-comp-29",
1597 "hns-roce-comp-30",
1598 "hns-roce-comp-31",
1599 "hns-roce-async",
1600 "hns-roce-common";
1604 compatible = "hisilicon,hip07-sas-v2";
1606 sas-addr = [50 01 88 20 16 00 00 00];
1607 hisilicon,sas-syscon = <&dsa_subctrl>;
1608 ctrl-reset-reg = <0xa60>;
1609 ctrl-reset-sts-reg = <0x5a30>;
1610 ctrl-clock-ena-reg = <0x338>;
1611 queue-count = <16>;
1612 phy-count = <8>;
1613 dma-coherent;
1614 interrupt-parent = <&mbigen_sas0>;
1645 compatible = "hisilicon,hip07-sas-v2";
1647 sas-addr = [50 01 88 20 16 00 00 00];
1648 hisilicon,sas-syscon = <&pcie_subctl>;
1649 hip06-sas-v2-quirk-amt;
1650 ctrl-reset-reg = <0xa18>;
1651 ctrl-reset-sts-reg = <0x5a0c>;
1652 ctrl-clock-ena-reg = <0x318>;
1653 queue-count = <16>;
1654 phy-count = <8>;
1655 dma-coherent;
1656 interrupt-parent = <&mbigen_sas1>;
1687 compatible = "hisilicon,hip07-sas-v2";
1689 sas-addr = [50 01 88 20 16 00 00 00];
1690 hisilicon,sas-syscon = <&pcie_subctl>;
1691 ctrl-reset-reg = <0xae0>;
1692 ctrl-reset-sts-reg = <0x5a70>;
1693 ctrl-clock-ena-reg = <0x3a8>;
1694 queue-count = <16>;
1695 phy-count = <9>;
1696 dma-coherent;
1697 interrupt-parent = <&mbigen_sas2>;
1728 compatible = "hisilicon,hip07-pcie-ecam";
1731 bus-range = <0xf8 0xff>;
1732 msi-map = <0xf800 &p0_its_dsa_a 0xf800 0x800>;
1733 msi-map-mask = <0xffff>;
1734 #address-cells = <3>;
1735 #size-cells = <2>;
1737 dma-coherent;
1740 #interrupt-cells = <1>;
1741 interrupt-map-mask = <0xf800 0 0 7>;
1742 interrupt-map = <0x0 0 0 1 &mbigen_pcie2_a 671 4
1749 compatible = "hisilicon,hip07-sec";
1768 interrupt-parent = <&p0_mbigen_sec_a>;
1770 dma-coherent;
1790 compatible = "hisilicon,hip07-sec";
1809 interrupt-parent = <&p0_mbigen_sec_b>;
1811 dma-coherent;
1831 compatible = "hisilicon,hip07-sec";
1850 interrupt-parent = <&p1_mbigen_sec_a>;
1852 dma-coherent;
1872 compatible = "hisilicon,hip07-sec";
1891 interrupt-parent = <&p1_mbigen_sec_b>;
1893 dma-coherent;