Lines Matching +full:smmu +full:- +full:v3
1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
86 compatible = "arm,cortex-a57";
88 enable-method = "psci";
89 next-level-cache = <&cluster0_l2>;
94 compatible = "arm,cortex-a57";
96 enable-method = "psci";
97 next-level-cache = <&cluster0_l2>;
102 compatible = "arm,cortex-a57";
104 enable-method = "psci";
105 next-level-cache = <&cluster0_l2>;
110 compatible = "arm,cortex-a57";
112 enable-method = "psci";
113 next-level-cache = <&cluster0_l2>;
118 compatible = "arm,cortex-a57";
120 enable-method = "psci";
121 next-level-cache = <&cluster1_l2>;
126 compatible = "arm,cortex-a57";
128 enable-method = "psci";
129 next-level-cache = <&cluster1_l2>;
134 compatible = "arm,cortex-a57";
136 enable-method = "psci";
137 next-level-cache = <&cluster1_l2>;
142 compatible = "arm,cortex-a57";
144 enable-method = "psci";
145 next-level-cache = <&cluster1_l2>;
150 compatible = "arm,cortex-a57";
152 enable-method = "psci";
153 next-level-cache = <&cluster2_l2>;
158 compatible = "arm,cortex-a57";
160 enable-method = "psci";
161 next-level-cache = <&cluster2_l2>;
166 compatible = "arm,cortex-a57";
168 enable-method = "psci";
169 next-level-cache = <&cluster2_l2>;
174 compatible = "arm,cortex-a57";
176 enable-method = "psci";
177 next-level-cache = <&cluster2_l2>;
182 compatible = "arm,cortex-a57";
184 enable-method = "psci";
185 next-level-cache = <&cluster3_l2>;
190 compatible = "arm,cortex-a57";
192 enable-method = "psci";
193 next-level-cache = <&cluster3_l2>;
198 compatible = "arm,cortex-a57";
200 enable-method = "psci";
201 next-level-cache = <&cluster3_l2>;
206 compatible = "arm,cortex-a57";
208 enable-method = "psci";
209 next-level-cache = <&cluster3_l2>;
212 cluster0_l2: l2-cache0 {
214 cache-level = <2>;
215 cache-unified;
218 cluster1_l2: l2-cache1 {
220 cache-level = <2>;
221 cache-unified;
224 cluster2_l2: l2-cache2 {
226 cache-level = <2>;
227 cache-unified;
230 cluster3_l2: l2-cache3 {
232 cache-level = <2>;
233 cache-unified;
237 gic: interrupt-controller@4d000000 {
238 compatible = "arm,gic-v3";
239 #interrupt-cells = <3>;
240 #address-cells = <2>;
241 #size-cells = <2>;
243 interrupt-controller;
244 #redistributor-regions = <1>;
245 redistributor-stride = <0x0 0x30000>;
253 its_dsa: msi-controller@c6000000 {
254 compatible = "arm,gic-v3-its";
255 msi-controller;
256 #msi-cells = <1>;
261 eth2: ethernet-0 {
262 compatible = "hisilicon,hns-nic-v2";
263 ae-handle = <&dsaf0>;
264 port-idx-in-ae = <0>;
265 local-mac-address = [00 00 00 00 00 00];
267 dma-coherent;
270 eth3: ethernet-1 {
271 compatible = "hisilicon,hns-nic-v2";
272 ae-handle = <&dsaf0>;
273 port-idx-in-ae = <1>;
274 local-mac-address = [00 00 00 00 00 00];
276 dma-coherent;
279 eth0: ethernet-4 {
280 compatible = "hisilicon,hns-nic-v2";
281 ae-handle = <&dsaf0>;
282 port-idx-in-ae = <4>;
283 local-mac-address = [00 00 00 00 00 00];
285 dma-coherent;
288 eth1: ethernet-5 {
289 compatible = "hisilicon,hns-nic-v2";
290 ae-handle = <&dsaf0>;
291 port-idx-in-ae = <5>;
292 local-mac-address = [00 00 00 00 00 00];
294 dma-coherent;
298 compatible = "fixed-clock";
299 clock-frequency = <50000000>;
300 #clock-cells = <0>;
304 compatible = "arm,armv8-timer";
312 compatible = "arm,cortex-a57-pmu";
317 compatible = "hisilicon,mbigen-v2";
321 msi-parent = <&its_dsa 0x40080>;
322 interrupt-controller;
323 #interrupt-cells = <2>;
324 num-pins = <2>;
328 msi-parent = <&its_dsa 0x40000>;
329 interrupt-controller;
330 #interrupt-cells = <2>;
331 num-pins = <128>;
335 msi-parent = <&its_dsa 0x40040>;
336 interrupt-controller;
337 #interrupt-cells = <2>;
338 num-pins = <128>;
342 msi-parent = <&its_dsa 0x40085>;
343 interrupt-controller;
344 #interrupt-cells = <2>;
345 num-pins = <10>;
350 compatible = "hisilicon,mbigen-v2";
354 msi-parent = <&its_dsa 0x40800>;
355 interrupt-controller;
356 #interrupt-cells = <2>;
357 num-pins = <409>;
360 mbigen_sas0: intc-sas0 {
361 msi-parent = <&its_dsa 0x40900>;
362 interrupt-controller;
363 #interrupt-cells = <2>;
364 num-pins = <128>;
375 * have a SMMU translation for MSI. In order to workaround this,
378 * systems. Hence please make sure that the smmu pcie node on
380 * when iommu-map entry is used along with the PCIe node.
381 * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html
384 compatible = "arm,smmu-v3";
386 #iommu-cells = <1>;
387 dma-coherent;
388 hisilicon,broken-prefetch-cmd;
393 compatible = "simple-bus";
394 #address-cells = <2>;
395 #size-cells = <2>;
399 compatible = "hisilicon,hip06-lpc";
400 #size-cells = <1>;
401 #address-cells = <2>;
405 compatible = "ipmi-bt";
413 clock-frequency = <1843200>;
420 compatible = "generic-ohci";
422 interrupt-parent = <&mbigen_usb>;
424 dma-coherent;
429 compatible = "generic-ehci";
431 interrupt-parent = <&mbigen_usb>;
433 dma-coherent;
438 compatible = "hisilicon,peri-subctrl","syscon";
443 compatible = "hisilicon,dsa-subctrl", "syscon";
448 compatible = "hisilicon,pcie-sas-subctrl", "syscon";
458 compatible = "hisilicon,hns-mdio";
460 subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 0x531c 0x5a1c>;
461 #address-cells = <1>;
462 #size-cells = <0>;
464 phy0: ethernet-phy@0 {
465 compatible = "ethernet-phy-ieee802.3-c22";
469 phy1: ethernet-phy@1 {
470 compatible = "ethernet-phy-ieee802.3-c22";
476 #address-cells = <1>;
477 #size-cells = <0>;
478 compatible = "hisilicon,hns-dsaf-v2";
479 mode = "6port-16rss";
482 reg-names = "ppe-base", "dsaf-base";
483 interrupt-parent = <&mbigen_dsaf0>;
484 subctrl-syscon = <&dsa_subctrl>;
485 reset-field-offset = <0>;
570 desc-num = <0x400>;
571 buf-size = <0x1000>;
572 dma-coherent;
576 serdes-syscon = <&serdes_ctrl>;
577 port-rst-offset = <0>;
578 port-mode-offset = <0>;
579 media-type = "fiber";
584 serdes-syscon = <&serdes_ctrl>;
585 port-rst-offset = <1>;
586 port-mode-offset = <1>;
587 media-type = "fiber";
592 phy-handle = <&phy0>;
593 serdes-syscon = <&serdes_ctrl>;
594 port-rst-offset = <4>;
595 port-mode-offset = <2>;
596 media-type = "copper";
601 phy-handle = <&phy1>;
602 serdes-syscon = <&serdes_ctrl>;
603 port-rst-offset = <5>;
604 port-mode-offset = <3>;
605 media-type = "copper";
610 compatible = "hisilicon,hip06-sas-v2";
612 sas-addr = [50 01 88 20 16 00 00 00];
613 hisilicon,sas-syscon = <&dsa_subctrl>;
614 ctrl-reset-reg = <0xa60>;
615 ctrl-reset-sts-reg = <0x5a30>;
616 ctrl-clock-ena-reg = <0x338>;
618 queue-count = <16>;
619 phy-count = <8>;
620 dma-coherent;
621 interrupt-parent = <&mbigen_sas0>;
652 compatible = "hisilicon,hip06-sas-v2";
654 sas-addr = [50 01 88 20 16 00 00 00];
655 hisilicon,sas-syscon = <&pcie_subctl>;
656 hip06-sas-v2-quirk-amt;
657 ctrl-reset-reg = <0xa18>;
658 ctrl-reset-sts-reg = <0x5a0c>;
659 ctrl-clock-ena-reg = <0x318>;
661 queue-count = <16>;
662 phy-count = <8>;
663 dma-coherent;
664 interrupt-parent = <&mbigen_sas1>;
695 compatible = "hisilicon,hip06-sas-v2";
697 sas-addr = [50 01 88 20 16 00 00 00];
698 hisilicon,sas-syscon = <&pcie_subctl>;
699 ctrl-reset-reg = <0xae0>;
700 ctrl-reset-sts-reg = <0x5a70>;
701 ctrl-clock-ena-reg = <0x3a8>;
703 queue-count = <16>;
704 phy-count = <9>;
705 dma-coherent;
706 interrupt-parent = <&mbigen_sas2>;
737 compatible = "hisilicon,hip06-pcie-ecam";
740 bus-range = <0 31>;
741 msi-map = <0x0000 &its_dsa 0x0000 0x2000>;
742 msi-map-mask = <0xffff>;
743 #address-cells = <3>;
744 #size-cells = <2>;
746 dma-coherent;
749 #interrupt-cells = <1>;
750 interrupt-map-mask = <0xf800 0 0 7>;
751 interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4