Lines Matching +full:0 +full:xa01b0000
23 #size-cells = <0>;
87 reg = <0x10000>;
95 reg = <0x10001>;
103 reg = <0x10002>;
111 reg = <0x10003>;
119 reg = <0x10100>;
127 reg = <0x10101>;
135 reg = <0x10102>;
143 reg = <0x10103>;
151 reg = <0x10200>;
159 reg = <0x10201>;
167 reg = <0x10202>;
175 reg = <0x10203>;
183 reg = <0x10300>;
191 reg = <0x10301>;
199 reg = <0x10302>;
207 reg = <0x10303>;
245 redistributor-stride = <0x0 0x30000>;
246 reg = <0x0 0x4d000000 0 0x10000>, /* GICD */
247 <0x0 0x4d100000 0 0x300000>, /* GICR */
248 <0x0 0xfe000000 0 0x10000>, /* GICC */
249 <0x0 0xfe010000 0 0x10000>, /* GICH */
250 <0x0 0xfe020000 0 0x10000>; /* GICV */
257 reg = <0x0 0xc6000000 0x0 0x40000>;
261 eth2: ethernet-0 {
264 port-idx-in-ae = <0>;
300 #clock-cells = <0>;
318 reg = <0x0 0xa0080000 0x0 0x10000>;
321 msi-parent = <&its_dsa 0x40080>;
328 msi-parent = <&its_dsa 0x40000>;
335 msi-parent = <&its_dsa 0x40040>;
342 msi-parent = <&its_dsa 0x40085>;
351 reg = <0x0 0xc0080000 0x0 0x10000>;
354 msi-parent = <&its_dsa 0x40800>;
361 msi-parent = <&its_dsa 0x40900>;
385 reg = <0x0 0xa0040000 0x0 0x20000>;
402 reg = <0x0 0xa01b0000 0x0 0x1000>;
407 reg = <0x01 0xe4 0x04>;
414 reg = <0x01 0x2f8 0x08>;
421 reg = <0x0 0xa7030000 0x0 0x10000>;
430 reg = <0x0 0xa7020000 0x0 0x10000>;
439 reg = <0 0x60000000 0x0 0x10000>;
444 reg = <0x0 0xc0000000 0x0 0x10000>;
449 reg = <0x0 0xa0000000 0x0 0x10000>;
454 reg = <0 0xc2200000 0x0 0x80000>;
459 reg = <0x0 0x603c0000 0x0 0x1000>;
460 subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 0x531c 0x5a1c>;
462 #size-cells = <0>;
464 phy0: ethernet-phy@0 {
466 reg = <0>;
477 #size-cells = <0>;
480 reg = <0x0 0xc5000000 0x0 0x890000>,
481 <0x0 0xc7000000 0x0 0x600000>;
485 reset-field-offset = <0>;
570 desc-num = <0x400>;
571 buf-size = <0x1000>;
574 port@0 {
575 reg = <0>;
577 port-rst-offset = <0>;
578 port-mode-offset = <0>;
611 reg = <0 0xc3000000 0 0x10000>;
614 ctrl-reset-reg = <0xa60>;
615 ctrl-reset-sts-reg = <0x5a30>;
616 ctrl-clock-ena-reg = <0x338>;
617 clocks = <&refclk 0>;
653 reg = <0 0xa2000000 0 0x10000>;
657 ctrl-reset-reg = <0xa18>;
658 ctrl-reset-sts-reg = <0x5a0c>;
659 ctrl-clock-ena-reg = <0x318>;
660 clocks = <&refclk 0>;
696 reg = <0 0xa3000000 0 0x10000>;
699 ctrl-reset-reg = <0xae0>;
700 ctrl-reset-sts-reg = <0x5a70>;
701 ctrl-clock-ena-reg = <0x3a8>;
702 clocks = <&refclk 0>;
738 reg = <0 0xb0000000 0 0x2000000>,
739 <0 0xa0090000 0 0x10000>;
740 bus-range = <0 31>;
741 msi-map = <0x0000 &its_dsa 0x0000 0x2000>;
742 msi-map-mask = <0xffff>;
747 ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0 0x5ff0000>,
748 <0x01000000 0 0 0 0xb7ff0000 0 0x10000>;
750 interrupt-map-mask = <0xf800 0 0 7>;
751 interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4
752 0x0 0 0 2 &mbigen_pcie0 650 4
753 0x0 0 0 3 &mbigen_pcie0 650 4
754 0x0 0 0 4 &mbigen_pcie0 650 4>;