Lines Matching +full:ns +full:- +full:thermal
1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/hisi,hi6220-resets.h>
10 #include <dt-bindings/clock/hi6220-clock.h>
11 #include <dt-bindings/pinctrl/hisi.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 compatible = "arm,psci-0.2";
26 #address-cells = <2>;
27 #size-cells = <0>;
29 cpu-map {
60 idle-states {
61 entry-method = "psci";
63 CPU_SLEEP: cpu-sleep {
64 compatible = "arm,idle-state";
65 local-timer-stop;
66 arm,psci-suspend-param = <0x0010000>;
67 entry-latency-us = <700>;
68 exit-latency-us = <250>;
69 min-residency-us = <1000>;
72 CLUSTER_SLEEP: cluster-sleep {
73 compatible = "arm,idle-state";
74 local-timer-stop;
75 arm,psci-suspend-param = <0x1010000>;
76 entry-latency-us = <1000>;
77 exit-latency-us = <700>;
78 min-residency-us = <2700>;
79 wakeup-latency-us = <1500>;
84 compatible = "arm,cortex-a53";
87 enable-method = "psci";
88 next-level-cache = <&CLUSTER0_L2>;
90 operating-points-v2 = <&cpu_opp_table>;
91 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
92 #cooling-cells = <2>; /* min followed by max */
93 dynamic-power-coefficient = <311>;
97 compatible = "arm,cortex-a53";
100 enable-method = "psci";
101 next-level-cache = <&CLUSTER0_L2>;
103 operating-points-v2 = <&cpu_opp_table>;
104 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
105 #cooling-cells = <2>; /* min followed by max */
106 dynamic-power-coefficient = <311>;
110 compatible = "arm,cortex-a53";
113 enable-method = "psci";
114 next-level-cache = <&CLUSTER0_L2>;
116 operating-points-v2 = <&cpu_opp_table>;
117 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
118 #cooling-cells = <2>; /* min followed by max */
119 dynamic-power-coefficient = <311>;
123 compatible = "arm,cortex-a53";
126 enable-method = "psci";
127 next-level-cache = <&CLUSTER0_L2>;
129 operating-points-v2 = <&cpu_opp_table>;
130 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
131 #cooling-cells = <2>; /* min followed by max */
132 dynamic-power-coefficient = <311>;
136 compatible = "arm,cortex-a53";
139 enable-method = "psci";
140 next-level-cache = <&CLUSTER1_L2>;
142 operating-points-v2 = <&cpu_opp_table>;
143 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
144 #cooling-cells = <2>; /* min followed by max */
145 dynamic-power-coefficient = <311>;
149 compatible = "arm,cortex-a53";
152 enable-method = "psci";
153 next-level-cache = <&CLUSTER1_L2>;
155 operating-points-v2 = <&cpu_opp_table>;
156 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
157 #cooling-cells = <2>; /* min followed by max */
158 dynamic-power-coefficient = <311>;
162 compatible = "arm,cortex-a53";
165 enable-method = "psci";
166 next-level-cache = <&CLUSTER1_L2>;
168 operating-points-v2 = <&cpu_opp_table>;
169 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
170 #cooling-cells = <2>; /* min followed by max */
171 dynamic-power-coefficient = <311>;
175 compatible = "arm,cortex-a53";
178 enable-method = "psci";
179 next-level-cache = <&CLUSTER1_L2>;
181 operating-points-v2 = <&cpu_opp_table>;
182 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
183 #cooling-cells = <2>; /* min followed by max */
184 dynamic-power-coefficient = <311>;
187 CLUSTER0_L2: l2-cache0 {
189 cache-level = <2>;
190 cache-unified;
193 CLUSTER1_L2: l2-cache1 {
195 cache-level = <2>;
196 cache-unified;
200 cpu_opp_table: opp-table-0 {
201 compatible = "operating-points-v2";
202 opp-shared;
205 opp-hz = /bits/ 64 <208000000>;
206 opp-microvolt = <1040000>;
207 clock-latency-ns = <500000>;
210 opp-hz = /bits/ 64 <432000000>;
211 opp-microvolt = <1040000>;
212 clock-latency-ns = <500000>;
215 opp-hz = /bits/ 64 <729000000>;
216 opp-microvolt = <1090000>;
217 clock-latency-ns = <500000>;
220 opp-hz = /bits/ 64 <960000000>;
221 opp-microvolt = <1180000>;
222 clock-latency-ns = <500000>;
225 opp-hz = /bits/ 64 <1200000000>;
226 opp-microvolt = <1330000>;
227 clock-latency-ns = <500000>;
231 gic: interrupt-controller@f6801000 {
232 compatible = "arm,gic-400";
237 #address-cells = <0>;
238 #interrupt-cells = <3>;
239 interrupt-controller;
244 compatible = "arm,armv8-timer";
245 interrupt-parent = <&gic>;
253 compatible = "simple-bus";
254 #address-cells = <2>;
255 #size-cells = <2>;
259 compatible = "hisilicon,hi6220-sramctrl", "syscon";
264 compatible = "hisilicon,hi6220-aoctrl", "syscon";
266 #clock-cells = <1>;
267 #reset-cells = <1>;
271 compatible = "hisilicon,hi6220-sysctrl", "syscon";
273 #clock-cells = <1>;
274 #reset-cells = <1>;
278 compatible = "hisilicon,hi6220-mediactrl", "syscon";
280 #clock-cells = <1>;
281 #reset-cells = <1>;
285 compatible = "hisilicon,hi6220-pmctrl", "syscon";
287 #clock-cells = <1>;
291 compatible = "hisilicon,hi6220-acpu-sctrl", "syscon";
293 #clock-cells = <1>;
302 compatible = "hisilicon,hi6220-stub-clk";
303 hisilicon,hi6220-clk-sram = <&sram>;
304 #clock-cells = <1>;
305 mbox-names = "mbox-tx";
315 clock-names = "uartclk", "apb_pclk";
324 clock-names = "uartclk", "apb_pclk";
325 pinctrl-names = "default";
326 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>;
328 dma-names = "rx", "tx";
338 clock-names = "uartclk", "apb_pclk";
339 pinctrl-names = "default";
340 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
350 clock-names = "uartclk", "apb_pclk";
351 pinctrl-names = "default";
352 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
362 clock-names = "uartclk", "apb_pclk";
363 pinctrl-names = "default";
364 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
369 compatible = "hisilicon,k3-dma-1.0";
371 #dma-cells = <1>;
372 dma-channels = <15>;
373 dma-requests = <32>;
376 dma-no-cci;
377 dma-type = "hi6220_dma";
389 clock-names = "timer1", "timer2", "apb_pclk";
397 clock-names = "apb_pclk";
405 clock-names = "apb_pclk";
409 compatible = "pinctrl-single";
411 #address-cells = <1>;
412 #size-cells = <0>;
413 #pinctrl-cells = <1>;
414 #gpio-range-cells = <3>;
415 pinctrl-single,register-width = <32>;
416 pinctrl-single,function-mask = <7>;
417 pinctrl-single,gpio-range = <
442 range: gpio-range {
443 #pinctrl-single,gpio-range-cells = <3>;
448 compatible = "pinconf-single";
450 #address-cells = <1>;
451 #size-cells = <0>;
452 #pinctrl-cells = <1>;
453 pinctrl-single,register-width = <32>;
457 compatible = "pinconf-single";
459 #address-cells = <1>;
460 #size-cells = <0>;
461 #pinctrl-cells = <1>;
462 pinctrl-single,register-width = <32>;
469 gpio-controller;
470 #gpio-cells = <2>;
471 interrupt-controller;
472 #interrupt-cells = <2>;
474 clock-names = "apb_pclk";
481 gpio-controller;
482 #gpio-cells = <2>;
483 interrupt-controller;
484 #interrupt-cells = <2>;
486 clock-names = "apb_pclk";
493 gpio-controller;
494 #gpio-cells = <2>;
495 interrupt-controller;
496 #interrupt-cells = <2>;
498 clock-names = "apb_pclk";
505 gpio-controller;
506 #gpio-cells = <2>;
507 gpio-ranges = <&pmx0 0 80 8>;
508 interrupt-controller;
509 #interrupt-cells = <2>;
511 clock-names = "apb_pclk";
518 gpio-controller;
519 #gpio-cells = <2>;
520 gpio-ranges = <&pmx0 0 88 8>;
521 interrupt-controller;
522 #interrupt-cells = <2>;
524 clock-names = "apb_pclk";
531 gpio-controller;
532 #gpio-cells = <2>;
533 gpio-ranges = <&pmx0 0 96 8>;
534 interrupt-controller;
535 #interrupt-cells = <2>;
537 clock-names = "apb_pclk";
544 gpio-controller;
545 #gpio-cells = <2>;
546 gpio-ranges = <&pmx0 0 104 8>;
547 interrupt-controller;
548 #interrupt-cells = <2>;
550 clock-names = "apb_pclk";
557 gpio-controller;
558 #gpio-cells = <2>;
559 gpio-ranges = <&pmx0 0 112 8>;
560 interrupt-controller;
561 #interrupt-cells = <2>;
563 clock-names = "apb_pclk";
570 gpio-controller;
571 #gpio-cells = <2>;
572 gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>;
573 interrupt-controller;
574 #interrupt-cells = <2>;
576 clock-names = "apb_pclk";
583 gpio-controller;
584 #gpio-cells = <2>;
585 gpio-ranges = <&pmx0 0 8 8>;
586 interrupt-controller;
587 #interrupt-cells = <2>;
589 clock-names = "apb_pclk";
596 gpio-controller;
597 #gpio-cells = <2>;
598 gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>;
599 interrupt-controller;
600 #interrupt-cells = <2>;
602 clock-names = "apb_pclk";
609 gpio-controller;
610 #gpio-cells = <2>;
611 gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>;
612 interrupt-controller;
613 #interrupt-cells = <2>;
615 clock-names = "apb_pclk";
622 gpio-controller;
623 #gpio-cells = <2>;
624 gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>;
625 interrupt-controller;
626 #interrupt-cells = <2>;
628 clock-names = "apb_pclk";
635 gpio-controller;
636 #gpio-cells = <2>;
637 gpio-ranges = <&pmx0 0 48 8>;
638 interrupt-controller;
639 #interrupt-cells = <2>;
641 clock-names = "apb_pclk";
648 gpio-controller;
649 #gpio-cells = <2>;
650 gpio-ranges = <&pmx0 0 56 8>;
651 interrupt-controller;
652 #interrupt-cells = <2>;
654 clock-names = "apb_pclk";
661 gpio-controller;
662 #gpio-cells = <2>;
663 gpio-ranges = <
668 interrupt-controller;
669 #interrupt-cells = <2>;
671 clock-names = "apb_pclk";
678 gpio-controller;
679 #gpio-cells = <2>;
680 gpio-ranges = <&pmx0 0 127 8>;
681 interrupt-controller;
682 #interrupt-cells = <2>;
684 clock-names = "apb_pclk";
691 gpio-controller;
692 #gpio-cells = <2>;
693 gpio-ranges = <&pmx0 0 135 8>;
694 interrupt-controller;
695 #interrupt-cells = <2>;
697 clock-names = "apb_pclk";
704 gpio-controller;
705 #gpio-cells = <2>;
706 gpio-ranges = <&pmx0 0 143 8>;
707 interrupt-controller;
708 #interrupt-cells = <2>;
710 clock-names = "apb_pclk";
717 gpio-controller;
718 #gpio-cells = <2>;
719 gpio-ranges = <&pmx0 0 151 8>;
720 interrupt-controller;
721 #interrupt-cells = <2>;
723 clock-names = "apb_pclk";
731 clock-names = "sspclk", "apb_pclk";
732 pinctrl-names = "default";
733 pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>;
734 num-cs = <1>;
735 cs-gpios = <&gpio6 2 0>;
740 compatible = "snps,designware-i2c";
744 i2c-sda-hold-time-ns = <300>;
745 pinctrl-names = "default";
746 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
751 compatible = "snps,designware-i2c";
755 i2c-sda-hold-time-ns = <300>;
756 pinctrl-names = "default";
757 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
762 compatible = "snps,designware-i2c";
766 i2c-sda-hold-time-ns = <300>;
767 pinctrl-names = "default";
768 pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
773 compatible = "hisilicon,hi6220-usb-phy";
774 #phy-cells = <0>;
775 phy-supply = <®_5v_hub>;
776 hisilicon,peripheral-syscon = <&sys_ctrl>;
780 compatible = "hisilicon,hi6220-usb";
783 phy-names = "usb2-phy";
785 clock-names = "otg";
787 g-rx-fifo-size = <512>;
788 g-np-tx-fifo-size = <128>;
789 g-tx-fifo-size = <128 128 128 128 128 128 128 128
795 compatible = "hisilicon,hi6220-mbox";
799 #mbox-cells = <3>;
803 compatible = "hisilicon,hi6220-dw-mshc";
807 clock-names = "ciu", "biu";
809 reset-names = "reset";
810 pinctrl-names = "default";
811 pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func
816 compatible = "hisilicon,hi6220-dw-mshc";
817 hisilicon,peripheral-syscon = <&ao_ctrl>;
820 #address-cells = <0x1>;
821 #size-cells = <0x0>;
823 clock-names = "ciu", "biu";
825 reset-names = "reset";
826 pinctrl-names = "default", "idle";
827 pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
828 pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
832 compatible = "hisilicon,hi6220-dw-mshc";
836 clock-names = "ciu", "biu";
838 reset-names = "reset";
839 pinctrl-names = "default", "idle";
840 pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>;
841 pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;
850 clock-names = "wdog_clk", "apb_pclk";
858 clock-names = "thermal_clk";
859 #thermal-sensor-cells = <1>;
863 compatible = "hisilicon,hi6210-i2s";
865 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */
868 clock-names = "dacodec", "i2s-base";
870 dma-names = "rx", "tx";
871 hisilicon,sysctrl-syscon = <&sys_ctrl>;
872 #sound-dai-cells = <1>;
875 thermal-zones {
877 cls0: cls0-thermal {
878 polling-delay = <1000>;
879 polling-delay-passive = <100>;
880 sustainable-power = <3326>;
883 thermal-sensors = <&tsensor 2>;
886 threshold: trip-point0 {
892 target: trip-point1 {
899 cooling-maps {
902 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
916 compatible = "hisilicon,hi6220-ade";
918 reg-names = "ade_base";
919 hisilicon,noc-syscon = <&medianoc_ade>;
927 clock-names = "clk_ade_core",
931 assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
933 assigned-clock-rates = <360000000>, <288000000>;
934 dma-coherent;
939 remote-endpoint = <&dsi_in>;
945 compatible = "hisilicon,hi6220-dsi";
948 clock-names = "pclk";
952 #address-cells = <1>;
953 #size-cells = <0>;
959 remote-endpoint = <&ade_out>;
966 compatible = "arm,coresight-cpu-debug","arm,primecell";
969 clock-names = "apb_pclk";
974 compatible = "arm,coresight-cpu-debug","arm,primecell";
977 clock-names = "apb_pclk";
982 compatible = "arm,coresight-cpu-debug","arm,primecell";
985 clock-names = "apb_pclk";
990 compatible = "arm,coresight-cpu-debug","arm,primecell";
993 clock-names = "apb_pclk";
998 compatible = "arm,coresight-cpu-debug","arm,primecell";
1001 clock-names = "apb_pclk";
1006 compatible = "arm,coresight-cpu-debug","arm,primecell";
1009 clock-names = "apb_pclk";
1014 compatible = "arm,coresight-cpu-debug","arm,primecell";
1017 clock-names = "apb_pclk";
1022 compatible = "arm,coresight-cpu-debug","arm,primecell";
1025 clock-names = "apb_pclk";
1030 compatible = "hisilicon,hi6220-mali", "arm,mali-450";
1032 interrupt-parent = <&gic>;
1045 interrupt-names = "gp",
1058 clock-names = "bus", "core";
1059 assigned-clocks = <&media_ctrl HI6220_G3D_CLK>,
1061 assigned-clock-rates = <500000000>, <144000000>;
1062 reset-names = "ao_g3d", "media_g3d";
1068 #include "hi6220-coresight.dtsi"