Lines Matching +full:ns +full:- +full:thermal
1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/hi3660-clock.h>
10 #include <dt-bindings/thermal/thermal.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <2>;
25 #size-cells = <0>;
27 cpu-map {
59 compatible = "arm,cortex-a53";
62 enable-method = "psci";
63 next-level-cache = <&A53_L2>;
64 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
65 capacity-dmips-mhz = <592>;
67 operating-points-v2 = <&cluster0_opp>;
68 #cooling-cells = <2>;
69 dynamic-power-coefficient = <110>;
73 compatible = "arm,cortex-a53";
76 enable-method = "psci";
77 next-level-cache = <&A53_L2>;
78 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
79 capacity-dmips-mhz = <592>;
81 operating-points-v2 = <&cluster0_opp>;
82 #cooling-cells = <2>;
86 compatible = "arm,cortex-a53";
89 enable-method = "psci";
90 next-level-cache = <&A53_L2>;
91 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
92 capacity-dmips-mhz = <592>;
94 operating-points-v2 = <&cluster0_opp>;
95 #cooling-cells = <2>;
99 compatible = "arm,cortex-a53";
102 enable-method = "psci";
103 next-level-cache = <&A53_L2>;
104 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
105 capacity-dmips-mhz = <592>;
107 operating-points-v2 = <&cluster0_opp>;
108 #cooling-cells = <2>;
112 compatible = "arm,cortex-a73";
115 enable-method = "psci";
116 next-level-cache = <&A73_L2>;
117 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
118 capacity-dmips-mhz = <1024>;
120 operating-points-v2 = <&cluster1_opp>;
121 #cooling-cells = <2>;
122 dynamic-power-coefficient = <550>;
126 compatible = "arm,cortex-a73";
129 enable-method = "psci";
130 next-level-cache = <&A73_L2>;
131 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
132 capacity-dmips-mhz = <1024>;
134 operating-points-v2 = <&cluster1_opp>;
135 #cooling-cells = <2>;
139 compatible = "arm,cortex-a73";
142 enable-method = "psci";
143 next-level-cache = <&A73_L2>;
144 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
145 capacity-dmips-mhz = <1024>;
147 operating-points-v2 = <&cluster1_opp>;
148 #cooling-cells = <2>;
152 compatible = "arm,cortex-a73";
155 enable-method = "psci";
156 next-level-cache = <&A73_L2>;
157 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
158 capacity-dmips-mhz = <1024>;
160 operating-points-v2 = <&cluster1_opp>;
161 #cooling-cells = <2>;
164 idle-states {
165 entry-method = "psci";
167 CPU_SLEEP_0: cpu-sleep-0 {
168 compatible = "arm,idle-state";
169 local-timer-stop;
170 arm,psci-suspend-param = <0x0010000>;
171 entry-latency-us = <400>;
172 exit-latency-us = <650>;
173 min-residency-us = <1500>;
175 CLUSTER_SLEEP_0: cluster-sleep-0 {
176 compatible = "arm,idle-state";
177 local-timer-stop;
178 arm,psci-suspend-param = <0x1010000>;
179 entry-latency-us = <500>;
180 exit-latency-us = <1600>;
181 min-residency-us = <3500>;
185 CPU_SLEEP_1: cpu-sleep-1 {
186 compatible = "arm,idle-state";
187 local-timer-stop;
188 arm,psci-suspend-param = <0x0010000>;
189 entry-latency-us = <400>;
190 exit-latency-us = <550>;
191 min-residency-us = <1500>;
194 CLUSTER_SLEEP_1: cluster-sleep-1 {
195 compatible = "arm,idle-state";
196 local-timer-stop;
197 arm,psci-suspend-param = <0x1010000>;
198 entry-latency-us = <800>;
199 exit-latency-us = <2900>;
200 min-residency-us = <3500>;
204 A53_L2: l2-cache0 {
206 cache-level = <2>;
207 cache-unified;
210 A73_L2: l2-cache1 {
212 cache-level = <2>;
213 cache-unified;
217 cluster0_opp: opp-table-0 {
218 compatible = "operating-points-v2";
219 opp-shared;
222 opp-hz = /bits/ 64 <533000000>;
223 opp-microvolt = <700000>;
224 clock-latency-ns = <300000>;
228 opp-hz = /bits/ 64 <999000000>;
229 opp-microvolt = <800000>;
230 clock-latency-ns = <300000>;
234 opp-hz = /bits/ 64 <1402000000>;
235 opp-microvolt = <900000>;
236 clock-latency-ns = <300000>;
240 opp-hz = /bits/ 64 <1709000000>;
241 opp-microvolt = <1000000>;
242 clock-latency-ns = <300000>;
246 opp-hz = /bits/ 64 <1844000000>;
247 opp-microvolt = <1100000>;
248 clock-latency-ns = <300000>;
252 cluster1_opp: opp-table-1 {
253 compatible = "operating-points-v2";
254 opp-shared;
257 opp-hz = /bits/ 64 <903000000>;
258 opp-microvolt = <700000>;
259 clock-latency-ns = <300000>;
263 opp-hz = /bits/ 64 <1421000000>;
264 opp-microvolt = <800000>;
265 clock-latency-ns = <300000>;
269 opp-hz = /bits/ 64 <1805000000>;
270 opp-microvolt = <900000>;
271 clock-latency-ns = <300000>;
275 opp-hz = /bits/ 64 <2112000000>;
276 opp-microvolt = <1000000>;
277 clock-latency-ns = <300000>;
281 opp-hz = /bits/ 64 <2362000000>;
282 opp-microvolt = <1100000>;
283 clock-latency-ns = <300000>;
287 gic: interrupt-controller@e82b0000 {
288 compatible = "arm,gic-400";
293 #address-cells = <0>;
294 #interrupt-cells = <3>;
295 interrupt-controller;
300 a53-pmu {
301 compatible = "arm,cortex-a53-pmu";
306 interrupt-affinity = <&cpu0>,
312 a73-pmu {
313 compatible = "arm,cortex-a73-pmu";
318 interrupt-affinity = <&cpu4>,
325 compatible = "arm,armv8-timer";
326 interrupt-parent = <&gic>;
338 compatible = "simple-bus";
339 #address-cells = <2>;
340 #size-cells = <2>;
344 compatible = "hisilicon,hi3660-crgctrl", "syscon";
346 #clock-cells = <1>;
350 compatible = "hisilicon,hi3660-reset";
351 #reset-cells = <2>;
352 hisi,rst-syscon = <&crg_ctrl>;
357 compatible = "hisilicon,hi3660-pctrl", "syscon";
359 #clock-cells = <1>;
363 compatible = "hisilicon,hi3660-pmuctrl", "syscon";
365 #clock-cells = <1>;
369 compatible = "hisilicon,hi3660-sctrl", "syscon";
371 #clock-cells = <1>;
375 compatible = "hisilicon,hi3660-iomcu", "syscon";
377 #clock-cells = <1>;
382 compatible = "hisilicon,hi3660-reset";
383 hisi,rst-syscon = <&iomcu>;
384 #reset-cells = <2>;
388 compatible = "hisilicon,hi3660-mbox";
392 #mbox-cells = <3>;
396 compatible = "hisilicon,hi3660-stub-clk";
398 #clock-cells = <1>;
410 clock-names = "timer1", "timer2", "apb_pclk";
414 compatible = "snps,designware-i2c";
417 #address-cells = <1>;
418 #size-cells = <0>;
419 clock-frequency = <400000>;
422 pinctrl-names = "default";
423 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
428 compatible = "snps,designware-i2c";
431 #address-cells = <1>;
432 #size-cells = <0>;
433 clock-frequency = <400000>;
436 pinctrl-names = "default";
437 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
442 compatible = "snps,designware-i2c";
445 #address-cells = <1>;
446 #size-cells = <0>;
447 clock-frequency = <400000>;
450 pinctrl-names = "default";
451 pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
456 compatible = "snps,designware-i2c";
459 #address-cells = <1>;
460 #size-cells = <0>;
461 clock-frequency = <400000>;
464 pinctrl-names = "default";
465 pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>;
475 clock-names = "uartclk", "apb_pclk";
476 pinctrl-names = "default";
477 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
485 dma-names = "rx", "tx";
489 clock-names = "uartclk", "apb_pclk";
490 pinctrl-names = "default";
491 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
499 dma-names = "rx", "tx";
503 clock-names = "uartclk", "apb_pclk";
504 pinctrl-names = "default";
505 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
515 clock-names = "uartclk", "apb_pclk";
516 pinctrl-names = "default";
517 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
525 dma-names = "rx", "tx";
529 clock-names = "uartclk", "apb_pclk";
530 pinctrl-names = "default";
531 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
539 dma-names = "rx", "tx";
543 clock-names = "uartclk", "apb_pclk";
544 pinctrl-names = "default";
545 pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>;
555 clock-names = "uartclk", "apb_pclk";
556 pinctrl-names = "default";
557 pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
562 compatible = "hisilicon,k3-dma-1.0";
564 #dma-cells = <1>;
565 dma-channels = <16>;
566 dma-requests = <32>;
567 dma-channel-mask = <0xfffe>;
570 dma-no-cci;
571 dma-type = "hi3660_dma";
574 asp_dmac: dma-controller@e804b000 {
575 compatible = "hisilicon,hisi-pcm-asp-dma-1.0";
577 #dma-cells = <1>;
578 dma-channels = <16>;
579 dma-requests = <32>;
581 interrupt-names = "asp_dma_irq";
589 clock-names = "apb_pclk";
596 gpio-controller;
597 #gpio-cells = <2>;
598 gpio-ranges = <&pmx0 1 0 7>;
599 interrupt-controller;
600 #interrupt-cells = <2>;
602 clock-names = "apb_pclk";
609 gpio-controller;
610 #gpio-cells = <2>;
611 gpio-ranges = <&pmx0 1 7 7>;
612 interrupt-controller;
613 #interrupt-cells = <2>;
615 clock-names = "apb_pclk";
622 gpio-controller;
623 #gpio-cells = <2>;
624 gpio-ranges = <&pmx0 0 14 8>;
625 interrupt-controller;
626 #interrupt-cells = <2>;
628 clock-names = "apb_pclk";
635 gpio-controller;
636 #gpio-cells = <2>;
637 gpio-ranges = <&pmx0 0 22 8>;
638 interrupt-controller;
639 #interrupt-cells = <2>;
641 clock-names = "apb_pclk";
648 gpio-controller;
649 #gpio-cells = <2>;
650 gpio-ranges = <&pmx0 0 30 8>;
651 interrupt-controller;
652 #interrupt-cells = <2>;
654 clock-names = "apb_pclk";
661 gpio-controller;
662 #gpio-cells = <2>;
663 gpio-ranges = <&pmx0 0 38 8>;
664 interrupt-controller;
665 #interrupt-cells = <2>;
667 clock-names = "apb_pclk";
674 gpio-controller;
675 #gpio-cells = <2>;
676 gpio-ranges = <&pmx0 0 46 8>;
677 interrupt-controller;
678 #interrupt-cells = <2>;
680 clock-names = "apb_pclk";
687 gpio-controller;
688 #gpio-cells = <2>;
689 gpio-ranges = <&pmx0 0 54 8>;
690 interrupt-controller;
691 #interrupt-cells = <2>;
693 clock-names = "apb_pclk";
700 gpio-controller;
701 #gpio-cells = <2>;
702 gpio-ranges = <&pmx0 0 62 8>;
703 interrupt-controller;
704 #interrupt-cells = <2>;
706 clock-names = "apb_pclk";
713 gpio-controller;
714 #gpio-cells = <2>;
715 gpio-ranges = <&pmx0 0 70 8>;
716 interrupt-controller;
717 #interrupt-cells = <2>;
719 clock-names = "apb_pclk";
726 gpio-controller;
727 #gpio-cells = <2>;
728 gpio-ranges = <&pmx0 0 78 8>;
729 interrupt-controller;
730 #interrupt-cells = <2>;
732 clock-names = "apb_pclk";
739 gpio-controller;
740 #gpio-cells = <2>;
741 gpio-ranges = <&pmx0 0 86 8>;
742 interrupt-controller;
743 #interrupt-cells = <2>;
745 clock-names = "apb_pclk";
752 gpio-controller;
753 #gpio-cells = <2>;
754 gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
755 interrupt-controller;
756 #interrupt-cells = <2>;
758 clock-names = "apb_pclk";
765 gpio-controller;
766 #gpio-cells = <2>;
767 gpio-ranges = <&pmx0 0 102 8>;
768 interrupt-controller;
769 #interrupt-cells = <2>;
771 clock-names = "apb_pclk";
778 gpio-controller;
779 #gpio-cells = <2>;
780 gpio-ranges = <&pmx0 0 110 8>;
781 interrupt-controller;
782 #interrupt-cells = <2>;
784 clock-names = "apb_pclk";
791 gpio-controller;
792 #gpio-cells = <2>;
793 gpio-ranges = <&pmx0 0 118 6>;
794 interrupt-controller;
795 #interrupt-cells = <2>;
797 clock-names = "apb_pclk";
804 gpio-controller;
805 #gpio-cells = <2>;
806 interrupt-controller;
807 #interrupt-cells = <2>;
809 clock-names = "apb_pclk";
816 gpio-controller;
817 #gpio-cells = <2>;
818 interrupt-controller;
819 #interrupt-cells = <2>;
821 clock-names = "apb_pclk";
828 gpio-controller;
829 #gpio-cells = <2>;
830 gpio-ranges = <&pmx2 0 0 8>;
831 interrupt-controller;
832 #interrupt-cells = <2>;
834 clock-names = "apb_pclk";
841 gpio-controller;
842 #gpio-cells = <2>;
843 gpio-ranges = <&pmx2 0 8 4>;
844 interrupt-controller;
845 #interrupt-cells = <2>;
847 clock-names = "apb_pclk";
854 gpio-controller;
855 #gpio-cells = <2>;
856 gpio-ranges = <&pmx1 0 0 6>;
857 interrupt-controller;
858 #interrupt-cells = <2>;
860 clock-names = "apb_pclk";
867 gpio-controller;
868 #gpio-cells = <2>;
869 interrupt-controller;
870 #interrupt-cells = <2>;
871 gpio-ranges = <&pmx3 0 0 6>;
873 clock-names = "apb_pclk";
880 gpio-controller;
881 #gpio-cells = <2>;
883 gpio-ranges = <&pmx4 2 0 6>;
884 interrupt-controller;
885 #interrupt-cells = <2>;
887 clock-names = "apb_pclk";
894 gpio-controller;
895 #gpio-cells = <2>;
897 gpio-ranges = <&pmx4 0 6 7>;
898 interrupt-controller;
899 #interrupt-cells = <2>;
901 clock-names = "apb_pclk";
908 gpio-controller;
909 #gpio-cells = <2>;
911 gpio-ranges = <&pmx4 0 13 8>;
912 interrupt-controller;
913 #interrupt-cells = <2>;
915 clock-names = "apb_pclk";
922 gpio-controller;
923 #gpio-cells = <2>;
925 gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>;
926 interrupt-controller;
927 #interrupt-cells = <2>;
929 clock-names = "apb_pclk";
936 gpio-controller;
937 #gpio-cells = <2>;
939 gpio-ranges = <&pmx4 0 28 8>;
940 interrupt-controller;
941 #interrupt-cells = <2>;
943 clock-names = "apb_pclk";
950 gpio-controller;
951 #gpio-cells = <2>;
953 gpio-ranges = <&pmx4 0 36 6>;
954 interrupt-controller;
955 #interrupt-cells = <2>;
957 clock-names = "apb_pclk";
964 gpio-controller;
965 #gpio-cells = <2>;
966 interrupt-controller;
967 #interrupt-cells = <2>;
969 clock-names = "apb_pclk";
975 #address-cells = <1>;
976 #size-cells = <0>;
979 clock-names = "sspclk", "apb_pclk";
980 pinctrl-names = "default";
981 pinctrl-0 = <&spi2_pmx_func &spi2_cfg_func>;
982 num-cs = <1>;
983 cs-gpios = <&gpio27 2 0>;
990 #address-cells = <1>;
991 #size-cells = <0>;
994 clock-names = "sspclk", "apb_pclk";
995 pinctrl-names = "default";
996 pinctrl-0 = <&spi3_pmx_func &spi3_cfg_func>;
997 num-cs = <1>;
998 cs-gpios = <&gpio18 5 0>;
1003 compatible = "hisilicon,kirin960-pcie";
1008 reg-names = "dbi", "apb", "phy", "config";
1009 bus-range = <0x0 0xff>;
1010 #address-cells = <3>;
1011 #size-cells = <2>;
1016 num-lanes = <1>;
1017 #interrupt-cells = <1>;
1019 interrupt-names = "msi";
1020 interrupt-map-mask = <0xf800 0 0 7>;
1021 interrupt-map = <0x0 0 0 1
1034 clock-names = "pcie_phy_ref", "pcie_aux",
1037 reset-gpios = <&gpio11 1 0 >;
1042 compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1";
1047 interrupt-parent = <&gic>;
1051 clock-names = "ref_clk", "phy_clk";
1052 freq-table-hz = <0 0>,
1056 reset-names = "rst";
1061 compatible = "hisilicon,hi3660-dw-mshc";
1063 #address-cells = <1>;
1064 #size-cells = <0>;
1068 clock-names = "ciu", "biu";
1069 clock-frequency = <3200000>;
1071 reset-names = "reset";
1072 hisilicon,peripheral-syscon = <&sctrl>;
1073 card-detect-delay = <200>;
1079 compatible = "hisilicon,hi3660-dw-mshc";
1081 #address-cells = <0x1>;
1082 #size-cells = <0x0>;
1086 clock-names = "ciu", "biu";
1088 reset-names = "reset";
1089 card-detect-delay = <200>;
1099 clock-names = "wdog_clk", "apb_pclk";
1108 clock-names = "wdog_clk", "apb_pclk";
1112 compatible = "hisilicon,hi3660-tsensor";
1115 #thermal-sensor-cells = <1>;
1118 thermal-zones {
1120 cls0: cls0-thermal {
1121 polling-delay = <1000>;
1122 polling-delay-passive = <100>;
1123 sustainable-power = <4500>;
1126 thermal-sensors = <&tsensor 1>;
1129 threshold: trip-point0 {
1135 target: trip-point1 {
1142 cooling-maps {
1146 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1154 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1164 compatible = "hisilicon,hi3660-usb3-otg-bc", "syscon", "simple-mfd";
1167 usb_phy: usb-phy {
1168 compatible = "hisilicon,hi3660-usb-phy";
1169 #phy-cells = <0>;
1170 hisilicon,pericrg-syscon = <&crg_ctrl>;
1171 hisilicon,pctrl-syscon = <&pctrl>;
1172 hisilicon,eye-diagram-param = <0x22466e4>;
1182 clock-names = "ref", "bus_early";
1184 assigned-clocks = <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>;
1185 assigned-clock-rates = <229000000>;
1194 phy-names = "usb3-phy";
1199 #include "hi3660-coresight.dtsi"