Lines Matching +full:scmi +full:- +full:smc

1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright 2021-2024 NXP
7 * Andra-Teodora Ilie <andra.ilie@nxp.com>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <0x02>;
16 #size-cells = <0x02>;
19 #address-cells = <1>;
20 #size-cells = <0>;
22 cpu-map {
62 compatible = "arm,cortex-a53";
64 enable-method = "psci";
70 compatible = "arm,cortex-a53";
72 enable-method = "psci";
78 compatible = "arm,cortex-a53";
80 enable-method = "psci";
86 compatible = "arm,cortex-a53";
88 enable-method = "psci";
94 compatible = "arm,cortex-a53";
96 enable-method = "psci";
102 compatible = "arm,cortex-a53";
104 enable-method = "psci";
110 compatible = "arm,cortex-a53";
112 enable-method = "psci";
118 compatible = "arm,cortex-a53";
120 enable-method = "psci";
126 scmi: scmi { label
127 compatible = "arm,scmi-smc";
129 arm,smc-id = <0xc20000fe>;
130 #address-cells = <1>;
131 #size-cells = <0>;
135 #clock-cells = <1>;
140 #clock-cells = <1>;
145 compatible = "arm,psci-1.0";
146 method = "smc";
152 compatible = "arm,cortex-a53-pmu";
156 reserved-memory {
157 #address-cells = <2>;
158 #size-cells = <2>;
162 compatible = "arm,scmi-shmem";
164 no-map;
169 compatible = "simple-bus";
170 #address-cells = <1>;
171 #size-cells = <1>;
175 compatible = "nxp,s32g3-rtc",
176 "nxp,s32g2-rtc";
180 clock-names = "ipg", "source0";
184 compatible = "nxp,s32g2-siul2-pinctrl";
185 /* MSCR0-MSCR101 registers on siul2_0 */
187 /* MSCR112-MSCR122 registers on siul2_1 */
189 /* MSCR144-MSCR190 registers on siul2_1 */
191 /* IMCR0-IMCR83 registers on siul2_0 */
193 /* IMCR119-IMCR397 registers on siul2_1 */
195 /* IMCR430-IMCR495 registers on siul2_1 */
198 jtag_pins: jtag-pins {
199 jtag-grp0 {
201 input-enable;
202 bias-pull-up;
203 slew-rate = <166>;
206 jtag-grp1 {
208 slew-rate = <166>;
211 jtag-grp2 {
213 input-enable;
214 bias-pull-down;
215 slew-rate = <166>;
218 jtag-grp3 {
224 jtag-grp4 {
226 input-enable;
227 bias-pull-up;
228 slew-rate = <166>;
232 pinctrl_usdhc0: usdhc0grp-pins {
233 usdhc0-grp0 {
236 output-enable;
237 bias-pull-down;
238 slew-rate = <150>;
241 usdhc0-grp1 {
251 output-enable;
252 input-enable;
253 bias-pull-up;
254 slew-rate = <150>;
257 usdhc0-grp2 {
259 output-enable;
260 slew-rate = <150>;
263 usdhc0-grp3 {
265 input-enable;
266 slew-rate = <150>;
269 usdhc0-grp4 {
283 pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins {
284 usdhc0-100mhz-grp0 {
287 output-enable;
288 bias-pull-down;
289 slew-rate = <150>;
292 usdhc0-100mhz-grp1 {
302 output-enable;
303 input-enable;
304 bias-pull-up;
305 slew-rate = <150>;
308 usdhc0-100mhz-grp2 {
310 output-enable;
311 slew-rate = <150>;
314 usdhc0-100mhz-grp3 {
316 input-enable;
317 slew-rate = <150>;
320 usdhc0-100mhz-grp4 {
334 pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins {
335 usdhc0-200mhz-grp0 {
338 output-enable;
339 bias-pull-down;
340 slew-rate = <208>;
343 usdhc0-200mhz-grp1 {
353 output-enable;
354 input-enable;
355 bias-pull-up;
356 slew-rate = <208>;
359 usdhc0-200mhz-grp2 {
361 output-enable;
362 slew-rate = <208>;
365 usdhc0-200mhz-grp3 {
367 input-enable;
368 slew-rate = <208>;
371 usdhc0-200mhz-grp4 {
386 edma0: dma-controller@40144000 {
387 compatible = "nxp,s32g3-edma", "nxp,s32g2-edma";
391 #dma-cells = <2>;
392 dma-channels = <32>;
396 interrupt-names = "tx-0-15",
397 "tx-16-31",
400 clock-names = "dmamux0", "dmamux1";
404 compatible = "nxp,s32g3-flexcan",
405 "nxp,s32g2-flexcan";
411 interrupt-names = "mb-0", "state", "berr", "mb-1";
413 clock-names = "ipg", "per";
418 compatible = "nxp,s32g3-flexcan",
419 "nxp,s32g2-flexcan";
425 interrupt-names = "mb-0", "state", "berr", "mb-1";
427 clock-names = "ipg", "per";
432 compatible = "nxp,s32g3-linflexuart",
433 "fsl,s32v234-linflexuart";
440 compatible = "nxp,s32g3-linflexuart",
441 "fsl,s32v234-linflexuart";
448 #index-cells = <1>;
449 compatible = "nxp,s32g3-usbmisc";
454 compatible = "nxp,s32g3-usb", "nxp,s32g2-usb";
456 interrupt-parent = <&gic>;
461 ahb-burst-config = <0x3>;
462 tx-burst-size-dword = <0x10>;
463 rx-burst-size-dword = <0x10>;
466 maximum-speed = "high-speed";
471 compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
475 clock-names = "dspi";
476 spi-num-chipselects = <8>;
477 bus-num = <0>;
479 dma-names = "tx", "rx";
484 compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
488 clock-names = "dspi";
489 spi-num-chipselects = <5>;
490 bus-num = <1>;
492 dma-names = "tx", "rx";
497 compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
501 clock-names = "dspi";
502 spi-num-chipselects = <5>;
503 bus-num = <2>;
505 dma-names = "tx", "rx";
510 compatible = "nxp,s32g3-i2c",
511 "nxp,s32g2-i2c";
513 #address-cells = <1>;
514 #size-cells = <0>;
517 clock-names = "ipg";
522 compatible = "nxp,s32g3-i2c",
523 "nxp,s32g2-i2c";
525 #address-cells = <1>;
526 #size-cells = <0>;
529 clock-names = "ipg";
534 compatible = "nxp,s32g3-i2c",
535 "nxp,s32g2-i2c";
537 #address-cells = <1>;
538 #size-cells = <0>;
541 clock-names = "ipg";
545 edma1: dma-controller@40244000 {
546 compatible = "nxp,s32g3-edma", "nxp,s32g2-edma";
550 #dma-cells = <2>;
551 dma-channels = <32>;
555 interrupt-names = "tx-0-15",
556 "tx-16-31",
559 clock-names = "dmamux0", "dmamux1";
563 compatible = "nxp,s32g3-flexcan",
564 "nxp,s32g2-flexcan";
570 interrupt-names = "mb-0", "state", "berr", "mb-1";
572 clock-names = "ipg", "per";
577 compatible = "nxp,s32g3-flexcan",
578 "nxp,s32g2-flexcan";
584 interrupt-names = "mb-0", "state", "berr", "mb-1";
586 clock-names = "ipg", "per";
591 compatible = "nxp,s32g3-linflexuart",
592 "fsl,s32v234-linflexuart";
599 compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
603 clock-names = "dspi";
604 spi-num-chipselects = <5>;
605 bus-num = <3>;
607 dma-names = "tx", "rx";
612 compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
616 clock-names = "dspi";
617 spi-num-chipselects = <5>;
618 bus-num = <4>;
620 dma-names = "tx", "rx";
625 compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
629 clock-names = "dspi";
630 spi-num-chipselects = <5>;
631 bus-num = <5>;
633 dma-names = "tx", "rx";
638 compatible = "nxp,s32g3-i2c",
639 "nxp,s32g2-i2c";
641 #address-cells = <1>;
642 #size-cells = <0>;
645 clock-names = "ipg";
650 compatible = "nxp,s32g3-i2c",
651 "nxp,s32g2-i2c";
653 #address-cells = <1>;
654 #size-cells = <0>;
657 clock-names = "ipg";
662 compatible = "nxp,s32g3-usdhc",
663 "nxp,s32g2-usdhc";
669 clock-names = "ipg", "ahb", "per";
673 gic: interrupt-controller@50800000 {
674 compatible = "arm,gic-v3";
675 #interrupt-cells = <3>;
676 interrupt-controller;
687 compatible = "arm,armv8-timer";
688 interrupt-parent = <&gic>;
689 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* sec-phys */
692 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, /* hyp-phys */
693 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; /* hyp-virt */
694 arm,no-tick-in-suspend;