Lines Matching +full:grp0 +full:- +full:pinmux
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright 2021-2024 NXP
7 * Andra-Teodora Ilie <andra.ilie@nxp.com>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <0x02>;
16 #size-cells = <0x02>;
19 #address-cells = <1>;
20 #size-cells = <0>;
22 cpu-map {
62 compatible = "arm,cortex-a53";
64 enable-method = "psci";
70 compatible = "arm,cortex-a53";
72 enable-method = "psci";
78 compatible = "arm,cortex-a53";
80 enable-method = "psci";
86 compatible = "arm,cortex-a53";
88 enable-method = "psci";
94 compatible = "arm,cortex-a53";
96 enable-method = "psci";
102 compatible = "arm,cortex-a53";
104 enable-method = "psci";
110 compatible = "arm,cortex-a53";
112 enable-method = "psci";
118 compatible = "arm,cortex-a53";
120 enable-method = "psci";
127 compatible = "arm,scmi-smc";
129 arm,smc-id = <0xc20000fe>;
130 #address-cells = <1>;
131 #size-cells = <0>;
135 #clock-cells = <1>;
140 #clock-cells = <1>;
145 compatible = "arm,psci-1.0";
152 compatible = "arm,cortex-a53-pmu";
156 reserved-memory {
157 #address-cells = <2>;
158 #size-cells = <2>;
162 compatible = "arm,scmi-shmem";
164 no-map;
169 compatible = "simple-bus";
170 #address-cells = <1>;
171 #size-cells = <1>;
175 compatible = "nxp,s32g2-siul2-pinctrl";
176 /* MSCR0-MSCR101 registers on siul2_0 */
178 /* MSCR112-MSCR122 registers on siul2_1 */
180 /* MSCR144-MSCR190 registers on siul2_1 */
182 /* IMCR0-IMCR83 registers on siul2_0 */
184 /* IMCR119-IMCR397 registers on siul2_1 */
186 /* IMCR430-IMCR495 registers on siul2_1 */
189 jtag_pins: jtag-pins {
190 jtag-grp0 {
191 pinmux = <0x0>;
192 input-enable;
193 bias-pull-up;
194 slew-rate = <166>;
197 jtag-grp1 {
198 pinmux = <0x11>;
199 slew-rate = <166>;
202 jtag-grp2 {
203 pinmux = <0x40>;
204 input-enable;
205 bias-pull-down;
206 slew-rate = <166>;
209 jtag-grp3 {
210 pinmux = <0x23c0>,
215 jtag-grp4 {
216 pinmux = <0x51>;
217 input-enable;
218 bias-pull-up;
219 slew-rate = <166>;
223 pinctrl_usdhc0: usdhc0grp-pins {
224 usdhc0-grp0 {
225 pinmux = <0x2e1>,
227 output-enable;
228 bias-pull-down;
229 slew-rate = <150>;
232 usdhc0-grp1 {
233 pinmux = <0x2f1>,
242 output-enable;
243 input-enable;
244 bias-pull-up;
245 slew-rate = <150>;
248 usdhc0-grp2 {
249 pinmux = <0x391>;
250 output-enable;
251 slew-rate = <150>;
254 usdhc0-grp3 {
255 pinmux = <0x3a0>;
256 input-enable;
257 slew-rate = <150>;
260 usdhc0-grp4 {
261 pinmux = <0x2032>,
274 pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins {
275 usdhc0-100mhz-grp0 {
276 pinmux = <0x2e1>,
278 output-enable;
279 bias-pull-down;
280 slew-rate = <150>;
283 usdhc0-100mhz-grp1 {
284 pinmux = <0x2f1>,
293 output-enable;
294 input-enable;
295 bias-pull-up;
296 slew-rate = <150>;
299 usdhc0-100mhz-grp2 {
300 pinmux = <0x391>;
301 output-enable;
302 slew-rate = <150>;
305 usdhc0-100mhz-grp3 {
306 pinmux = <0x3a0>;
307 input-enable;
308 slew-rate = <150>;
311 usdhc0-100mhz-grp4 {
312 pinmux = <0x2032>,
325 pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins {
326 usdhc0-200mhz-grp0 {
327 pinmux = <0x2e1>,
329 output-enable;
330 bias-pull-down;
331 slew-rate = <208>;
334 usdhc0-200mhz-grp1 {
335 pinmux = <0x2f1>,
344 output-enable;
345 input-enable;
346 bias-pull-up;
347 slew-rate = <208>;
350 usdhc0-200mhz-grp2 {
351 pinmux = <0x391>;
352 output-enable;
353 slew-rate = <208>;
356 usdhc0-200mhz-grp3 {
357 pinmux = <0x3a0>;
358 input-enable;
359 slew-rate = <208>;
362 usdhc0-200mhz-grp4 {
363 pinmux = <0x2032>,
377 edma0: dma-controller@40144000 {
378 compatible = "nxp,s32g3-edma", "nxp,s32g2-edma";
382 #dma-cells = <2>;
383 dma-channels = <32>;
387 interrupt-names = "tx-0-15",
388 "tx-16-31",
391 clock-names = "dmamux0", "dmamux1";
395 compatible = "nxp,s32g3-flexcan",
396 "nxp,s32g2-flexcan";
402 interrupt-names = "mb-0", "state", "berr", "mb-1";
404 clock-names = "ipg", "per";
409 compatible = "nxp,s32g3-flexcan",
410 "nxp,s32g2-flexcan";
416 interrupt-names = "mb-0", "state", "berr", "mb-1";
418 clock-names = "ipg", "per";
423 compatible = "nxp,s32g3-linflexuart",
424 "fsl,s32v234-linflexuart";
431 compatible = "nxp,s32g3-linflexuart",
432 "fsl,s32v234-linflexuart";
439 compatible = "nxp,s32g3-i2c",
440 "nxp,s32g2-i2c";
442 #address-cells = <1>;
443 #size-cells = <0>;
446 clock-names = "ipg";
451 compatible = "nxp,s32g3-i2c",
452 "nxp,s32g2-i2c";
454 #address-cells = <1>;
455 #size-cells = <0>;
458 clock-names = "ipg";
463 compatible = "nxp,s32g3-i2c",
464 "nxp,s32g2-i2c";
466 #address-cells = <1>;
467 #size-cells = <0>;
470 clock-names = "ipg";
474 edma1: dma-controller@40244000 {
475 compatible = "nxp,s32g3-edma", "nxp,s32g2-edma";
479 #dma-cells = <2>;
480 dma-channels = <32>;
484 interrupt-names = "tx-0-15",
485 "tx-16-31",
488 clock-names = "dmamux0", "dmamux1";
492 compatible = "nxp,s32g3-flexcan",
493 "nxp,s32g2-flexcan";
499 interrupt-names = "mb-0", "state", "berr", "mb-1";
501 clock-names = "ipg", "per";
506 compatible = "nxp,s32g3-flexcan",
507 "nxp,s32g2-flexcan";
513 interrupt-names = "mb-0", "state", "berr", "mb-1";
515 clock-names = "ipg", "per";
520 compatible = "nxp,s32g3-linflexuart",
521 "fsl,s32v234-linflexuart";
528 compatible = "nxp,s32g3-i2c",
529 "nxp,s32g2-i2c";
531 #address-cells = <1>;
532 #size-cells = <0>;
535 clock-names = "ipg";
540 compatible = "nxp,s32g3-i2c",
541 "nxp,s32g2-i2c";
543 #address-cells = <1>;
544 #size-cells = <0>;
547 clock-names = "ipg";
552 compatible = "nxp,s32g3-usdhc",
553 "nxp,s32g2-usdhc";
559 clock-names = "ipg", "ahb", "per";
563 gic: interrupt-controller@50800000 {
564 compatible = "arm,gic-v3";
565 #interrupt-cells = <3>;
566 interrupt-controller;
577 compatible = "arm,armv8-timer";
578 interrupt-parent = <&gic>;
579 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* sec-phys */
582 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, /* hyp-phys */
583 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; /* hyp-virt */
584 arm,no-tick-in-suspend;