Lines Matching +full:num +full:- +full:tx +full:- +full:queues
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 * Copyright 2017-2021, 2024-2025 NXP
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
18 #address-cells = <2>;
19 #size-cells = <2>;
23 compatible = "arm,scmi-shmem";
25 no-map;
30 #address-cells = <1>;
31 #size-cells = <0>;
35 compatible = "arm,cortex-a53";
37 enable-method = "psci";
38 next-level-cache = <&cluster0_l2>;
43 compatible = "arm,cortex-a53";
45 enable-method = "psci";
46 next-level-cache = <&cluster0_l2>;
51 compatible = "arm,cortex-a53";
53 enable-method = "psci";
54 next-level-cache = <&cluster1_l2>;
59 compatible = "arm,cortex-a53";
61 enable-method = "psci";
62 next-level-cache = <&cluster1_l2>;
65 cluster0_l2: l2-cache0 {
67 cache-level = <2>;
68 cache-unified;
71 cluster1_l2: l2-cache1 {
73 cache-level = <2>;
74 cache-unified;
79 compatible = "arm,cortex-a53-pmu";
84 compatible = "arm,armv8-timer";
93 compatible = "arm,scmi-smc";
94 arm,smc-id = <0xc20000fe>;
95 #address-cells = <1>;
96 #size-cells = <0>;
101 #clock-cells = <1>;
106 compatible = "arm,psci-1.0";
112 compatible = "simple-bus";
113 #address-cells = <1>;
114 #size-cells = <1>;
118 compatible = "nxp,s32g2-rtc";
122 clock-names = "ipg", "source0";
126 compatible = "nxp,s32g2-siul2-pinctrl";
127 /* MSCR0-MSCR101 registers on siul2_0 */
129 /* MSCR112-MSCR122 registers on siul2_1 */
131 /* MSCR144-MSCR190 registers on siul2_1 */
133 /* IMCR0-IMCR83 registers on siul2_0 */
135 /* IMCR119-IMCR397 registers on siul2_1 */
137 /* IMCR430-IMCR495 registers on siul2_1 */
140 jtag_pins: jtag-pins {
141 jtag-grp0 {
143 input-enable;
144 bias-pull-up;
145 slew-rate = <166>;
148 jtag-grp1 {
150 slew-rate = <166>;
153 jtag-grp2 {
155 input-enable;
156 bias-pull-down;
157 slew-rate = <166>;
160 jtag-grp3 {
166 jtag-grp4 {
168 input-enable;
169 bias-pull-up;
170 slew-rate = <166>;
174 pinctrl_usdhc0: usdhc0grp-pins {
175 usdhc0-grp0 {
178 output-enable;
179 bias-pull-down;
180 slew-rate = <150>;
183 usdhc0-grp1 {
193 output-enable;
194 input-enable;
195 bias-pull-up;
196 slew-rate = <150>;
199 usdhc0-grp2 {
201 output-enable;
202 slew-rate = <150>;
205 usdhc0-grp3 {
207 input-enable;
208 slew-rate = <150>;
211 usdhc0-grp4 {
225 pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins {
226 usdhc0-100mhz-grp0 {
229 output-enable;
230 bias-pull-down;
231 slew-rate = <150>;
234 usdhc0-100mhz-grp1 {
244 output-enable;
245 input-enable;
246 bias-pull-up;
247 slew-rate = <150>;
250 usdhc0-100mhz-grp2 {
252 output-enable;
253 slew-rate = <150>;
256 usdhc0-100mhz-grp3 {
258 input-enable;
259 slew-rate = <150>;
262 usdhc0-100mhz-grp4 {
276 pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins {
277 usdhc0-200mhz-grp0 {
280 output-enable;
281 bias-pull-down;
282 slew-rate = <208>;
285 usdhc0-200mhz-grp1 {
295 output-enable;
296 input-enable;
297 bias-pull-up;
298 slew-rate = <208>;
301 usdhc0-200mhz-grp2 {
303 output-enable;
304 slew-rate = <208>;
307 usdhc0-200mhz-grp3 {
309 input-enable;
310 slew-rate = <208>;
313 usdhc0-200mhz-grp4 {
329 compatible = "nxp,s32g2-ocotp";
331 #address-cells = <1>;
332 #size-cells = <1>;
336 compatible = "nxp,s32g2-swt";
339 clock-names = "counter", "module", "register";
344 compatible = "nxp,s32g2-swt";
347 clock-names = "counter", "module", "register";
352 compatible = "nxp,s32g2-swt";
355 clock-names = "counter", "module", "register";
360 compatible = "nxp,s32g2-swt";
363 clock-names = "counter", "module", "register";
368 compatible = "nxp,s32g2-stm";
372 clock-names = "counter", "module", "register";
377 compatible = "nxp,s32g2-stm";
381 clock-names = "counter", "module", "register";
386 compatible = "nxp,s32g2-stm";
390 clock-names = "counter", "module", "register";
395 compatible = "nxp,s32g2-stm";
399 clock-names = "counter", "module", "register";
403 edma0: dma-controller@40144000 {
404 compatible = "nxp,s32g2-edma";
408 #dma-cells = <2>;
409 dma-channels = <32>;
413 interrupt-names = "tx-0-15",
414 "tx-16-31",
417 clock-names = "dmamux0", "dmamux1";
421 compatible = "nxp,s32g2-flexcan";
427 interrupt-names = "mb-0", "state", "berr", "mb-1";
429 clock-names = "ipg", "per";
434 compatible = "nxp,s32g2-flexcan";
440 interrupt-names = "mb-0", "state", "berr", "mb-1";
442 clock-names = "ipg", "per";
447 compatible = "nxp,s32g2-linflexuart",
448 "fsl,s32v234-linflexuart";
455 compatible = "nxp,s32g2-linflexuart",
456 "fsl,s32v234-linflexuart";
463 #index-cells = <1>;
464 compatible = "nxp,s32g2-usbmisc";
469 compatible = "nxp,s32g2-usb";
471 interrupt-parent = <&gic>;
476 ahb-burst-config = <0x3>;
477 tx-burst-size-dword = <0x10>;
478 rx-burst-size-dword = <0x10>;
481 maximum-speed = "high-speed";
486 compatible = "nxp,s32g2-dspi";
490 clock-names = "dspi";
491 spi-num-chipselects = <8>;
492 bus-num = <0>;
494 dma-names = "tx", "rx";
499 compatible = "nxp,s32g2-dspi";
503 clock-names = "dspi";
504 spi-num-chipselects = <5>;
505 bus-num = <1>;
507 dma-names = "tx", "rx";
512 compatible = "nxp,s32g2-dspi";
516 clock-names = "dspi";
517 spi-num-chipselects = <5>;
518 bus-num = <2>;
520 dma-names = "tx", "rx";
525 compatible = "nxp,s32g2-i2c";
527 #address-cells = <1>;
528 #size-cells = <0>;
531 clock-names = "ipg";
536 compatible = "nxp,s32g2-i2c";
538 #address-cells = <1>;
539 #size-cells = <0>;
542 clock-names = "ipg";
547 compatible = "nxp,s32g2-i2c";
549 #address-cells = <1>;
550 #size-cells = <0>;
553 clock-names = "ipg";
558 compatible = "nxp,s32g2-swt";
561 clock-names = "counter", "module", "register";
566 compatible = "nxp,s32g2-swt";
569 clock-names = "counter", "module", "register";
574 compatible = "nxp,s32g2-swt";
577 clock-names = "counter", "module", "register";
582 compatible = "nxp,s32g2-stm";
585 clock-names = "counter", "module", "register";
591 compatible = "nxp,s32g2-stm";
594 clock-names = "counter", "module", "register";
600 compatible = "nxp,s32g2-stm";
603 clock-names = "counter", "module", "register";
608 edma1: dma-controller@40244000 {
609 compatible = "nxp,s32g2-edma";
613 #dma-cells = <2>;
614 dma-channels = <32>;
618 interrupt-names = "tx-0-15",
619 "tx-16-31",
622 clock-names = "dmamux0", "dmamux1";
626 compatible = "nxp,s32g2-flexcan";
632 interrupt-names = "mb-0", "state", "berr", "mb-1";
634 clock-names = "ipg", "per";
639 compatible = "nxp,s32g2-flexcan";
645 interrupt-names = "mb-0", "state", "berr", "mb-1";
647 clock-names = "ipg", "per";
652 compatible = "nxp,s32g2-linflexuart",
653 "fsl,s32v234-linflexuart";
660 compatible = "nxp,s32g2-dspi";
664 clock-names = "dspi";
665 spi-num-chipselects = <5>;
666 bus-num = <3>;
668 dma-names = "tx", "rx";
673 compatible = "nxp,s32g2-dspi";
677 clock-names = "dspi";
678 spi-num-chipselects = <5>;
679 bus-num = <4>;
681 dma-names = "tx", "rx";
686 compatible = "nxp,s32g2-dspi";
690 clock-names = "dspi";
691 spi-num-chipselects = <5>;
692 bus-num = <5>;
694 dma-names = "tx", "rx";
699 compatible = "nxp,s32g2-i2c";
701 #address-cells = <1>;
702 #size-cells = <0>;
705 clock-names = "ipg";
710 compatible = "nxp,s32g2-i2c";
712 #address-cells = <1>;
713 #size-cells = <0>;
716 clock-names = "ipg";
721 compatible = "nxp,s32g2-usdhc";
725 clock-names = "ipg", "ahb", "per";
726 bus-width = <8>;
731 compatible = "nxp,s32g2-dwmac";
734 interrupt-parent = <&gic>;
736 interrupt-names = "macirq";
737 snps,mtl-rx-config = <&mtl_rx_setup>;
738 snps,mtl-tx-config = <&mtl_tx_setup>;
741 mtl_rx_setup: rx-queues-config {
742 snps,rx-queues-to-use = <5>;
760 mtl_tx_setup: tx-queues-config {
761 snps,tx-queues-to-use = <5>;
780 compatible = "snps,dwmac-mdio";
781 #address-cells = <1>;
782 #size-cells = <0>;
786 gic: interrupt-controller@50800000 {
787 compatible = "arm,gic-v3";
794 interrupt-controller;
795 #interrupt-cells = <3>;