Lines Matching +full:imx7ulp +full:- +full:lpi2c
1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
6 #include <dt-bindings/dma/fsl-edma.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx95-clock.h"
13 #include "imx95-pinfunc.h"
14 #include "imx95-power.h"
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-a55";
29 enable-method = "psci";
30 #cooling-cells = <2>;
31 power-domains = <&scmi_perf IMX95_PERF_A55>;
32 power-domain-names = "perf";
33 i-cache-size = <32768>;
34 i-cache-line-size = <64>;
35 i-cache-sets = <128>;
36 d-cache-size = <32768>;
37 d-cache-line-size = <64>;
38 d-cache-sets = <128>;
39 next-level-cache = <&l2_cache_l0>;
44 compatible = "arm,cortex-a55";
46 enable-method = "psci";
47 #cooling-cells = <2>;
48 power-domains = <&scmi_perf IMX95_PERF_A55>;
49 power-domain-names = "perf";
50 i-cache-size = <32768>;
51 i-cache-line-size = <64>;
52 i-cache-sets = <128>;
53 d-cache-size = <32768>;
54 d-cache-line-size = <64>;
55 d-cache-sets = <128>;
56 next-level-cache = <&l2_cache_l1>;
61 compatible = "arm,cortex-a55";
63 enable-method = "psci";
64 #cooling-cells = <2>;
65 power-domains = <&scmi_perf IMX95_PERF_A55>;
66 power-domain-names = "perf";
67 i-cache-size = <32768>;
68 i-cache-line-size = <64>;
69 i-cache-sets = <128>;
70 d-cache-size = <32768>;
71 d-cache-line-size = <64>;
72 d-cache-sets = <128>;
73 next-level-cache = <&l2_cache_l2>;
78 compatible = "arm,cortex-a55";
80 enable-method = "psci";
81 #cooling-cells = <2>;
82 power-domains = <&scmi_perf IMX95_PERF_A55>;
83 power-domain-names = "perf";
84 i-cache-size = <32768>;
85 i-cache-line-size = <64>;
86 i-cache-sets = <128>;
87 d-cache-size = <32768>;
88 d-cache-line-size = <64>;
89 d-cache-sets = <128>;
90 next-level-cache = <&l2_cache_l3>;
95 compatible = "arm,cortex-a55";
97 power-domains = <&scmi_perf IMX95_PERF_A55>;
98 power-domain-names = "perf";
99 enable-method = "psci";
100 #cooling-cells = <2>;
101 i-cache-size = <32768>;
102 i-cache-line-size = <64>;
103 i-cache-sets = <128>;
104 d-cache-size = <32768>;
105 d-cache-line-size = <64>;
106 d-cache-sets = <128>;
107 next-level-cache = <&l2_cache_l4>;
112 compatible = "arm,cortex-a55";
114 power-domains = <&scmi_perf IMX95_PERF_A55>;
115 power-domain-names = "perf";
116 enable-method = "psci";
117 #cooling-cells = <2>;
118 i-cache-size = <32768>;
119 i-cache-line-size = <64>;
120 i-cache-sets = <128>;
121 d-cache-size = <32768>;
122 d-cache-line-size = <64>;
123 d-cache-sets = <128>;
124 next-level-cache = <&l2_cache_l5>;
127 l2_cache_l0: l2-cache-l0 {
129 cache-size = <65536>;
130 cache-line-size = <64>;
131 cache-sets = <256>;
132 cache-level = <2>;
133 cache-unified;
134 next-level-cache = <&l3_cache>;
137 l2_cache_l1: l2-cache-l1 {
139 cache-size = <65536>;
140 cache-line-size = <64>;
141 cache-sets = <256>;
142 cache-level = <2>;
143 cache-unified;
144 next-level-cache = <&l3_cache>;
147 l2_cache_l2: l2-cache-l2 {
149 cache-size = <65536>;
150 cache-line-size = <64>;
151 cache-sets = <256>;
152 cache-level = <2>;
153 cache-unified;
154 next-level-cache = <&l3_cache>;
157 l2_cache_l3: l2-cache-l3 {
159 cache-size = <65536>;
160 cache-line-size = <64>;
161 cache-sets = <256>;
162 cache-level = <2>;
163 cache-unified;
164 next-level-cache = <&l3_cache>;
167 l2_cache_l4: l2-cache-l4 {
169 cache-size = <65536>;
170 cache-line-size = <64>;
171 cache-sets = <256>;
172 cache-level = <2>;
173 cache-unified;
174 next-level-cache = <&l3_cache>;
177 l2_cache_l5: l2-cache-l5 {
179 cache-size = <65536>;
180 cache-line-size = <64>;
181 cache-sets = <256>;
182 cache-level = <2>;
183 cache-unified;
184 next-level-cache = <&l3_cache>;
187 l3_cache: l3-cache {
189 cache-size = <524288>;
190 cache-line-size = <64>;
191 cache-sets = <512>;
192 cache-level = <3>;
193 cache-unified;
196 cpu-map {
225 dummy: clock-dummy {
226 compatible = "fixed-clock";
227 #clock-cells = <0>;
228 clock-frequency = <0>;
229 clock-output-names = "dummy";
232 clk_ext1: clock-ext1 {
233 compatible = "fixed-clock";
234 #clock-cells = <0>;
235 clock-frequency = <133000000>;
236 clock-output-names = "clk_ext1";
239 sai1_mclk: clock-sai-mclk1 {
240 compatible = "fixed-clock";
241 #clock-cells = <0>;
242 clock-frequency= <0>;
243 clock-output-names = "sai1_mclk";
246 sai2_mclk: clock-sai-mclk2 {
247 compatible = "fixed-clock";
248 #clock-cells = <0>;
249 clock-frequency= <0>;
250 clock-output-names = "sai2_mclk";
253 sai3_mclk: clock-sai-mclk3 {
254 compatible = "fixed-clock";
255 #clock-cells = <0>;
256 clock-frequency= <0>;
257 clock-output-names = "sai3_mclk";
260 sai4_mclk: clock-sai-mclk4 {
261 compatible = "fixed-clock";
262 #clock-cells = <0>;
263 clock-frequency= <0>;
264 clock-output-names = "sai4_mclk";
267 sai5_mclk: clock-sai-mclk5 {
268 compatible = "fixed-clock";
269 #clock-cells = <0>;
270 clock-frequency= <0>;
271 clock-output-names = "sai5_mclk";
274 osc_24m: clock-24m {
275 compatible = "fixed-clock";
276 #clock-cells = <0>;
277 clock-frequency = <24000000>;
278 clock-output-names = "osc_24m";
282 compatible = "mmio-sram";
285 #address-cells = <1>;
286 #size-cells = <1>;
294 #address-cells = <1>;
295 #size-cells = <0>;
299 #power-domain-cells = <1>;
304 #power-domain-cells = <1>;
309 #clock-cells = <1>;
314 #thermal-sensor-cells = <1>;
325 compatible = "arm,cortex-a55-pmu";
329 thermal_zones: thermal-zones {
330 a55-thermal {
331 polling-delay-passive = <250>;
332 polling-delay = <2000>;
333 thermal-sensors = <&scmi_sensor 1>;
349 cooling-maps {
352 cooling-device =
365 compatible = "arm,psci-1.0";
370 compatible = "arm,armv8-timer";
375 clock-frequency = <24000000>;
376 arm,no-tick-in-suspend;
377 interrupt-parent = <&gic>;
380 gic: interrupt-controller@48000000 {
381 compatible = "arm,gic-v3";
384 #address-cells = <2>;
385 #size-cells = <2>;
386 #interrupt-cells = <3>;
387 interrupt-controller;
389 interrupt-parent = <&gic>;
390 dma-noncoherent;
393 its: msi-controller@48040000 {
394 compatible = "arm,gic-v3-its";
396 msi-controller;
397 #msi-cells = <1>;
398 dma-noncoherent;
403 compatible = "simple-bus";
404 #address-cells = <2>;
405 #size-cells = <2>;
409 compatible = "fsl,aips-bus", "simple-bus";
413 #address-cells = <1>;
414 #size-cells = <1>;
416 edma2: dma-controller@42000000 {
417 compatible = "fsl,imx95-edma5";
419 #dma-cells = <3>;
420 dma-channels = <64>;
486 clock-names = "dma";
489 edma3: dma-controller@42210000 {
490 compatible = "fsl,imx95-edma5";
492 #dma-cells = <3>;
493 dma-channels = <64>;
559 clock-names = "dma";
563 compatible = "fsl,imx95-mu";
567 #mbox-cells = <2>;
572 compatible = "fsl,imx93-wdt";
576 timeout-sec = <40>;
581 compatible = "fsl,imx7ulp-pwm";
584 #pwm-cells = <3>;
589 compatible = "fsl,imx7ulp-pwm";
592 #pwm-cells = <3>;
597 compatible = "fsl,imx7ulp-pwm";
600 #pwm-cells = <3>;
605 compatible = "fsl,imx7ulp-pwm";
608 #pwm-cells = <3>;
613 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
618 clock-names = "per", "ipg";
619 #address-cells = <1>;
620 #size-cells = <0>;
622 dma-names = "tx", "rx";
627 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
632 clock-names = "per", "ipg";
633 #address-cells = <1>;
634 #size-cells = <0>;
636 dma-names = "tx", "rx";
641 #address-cells = <1>;
642 #size-cells = <0>;
643 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
648 clock-names = "per", "ipg";
650 dma-names = "tx", "rx";
655 #address-cells = <1>;
656 #size-cells = <0>;
657 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
662 clock-names = "per", "ipg";
664 dma-names = "tx", "rx";
669 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
670 "fsl,imx7ulp-lpuart";
674 clock-names = "ipg";
676 dma-names = "rx", "tx";
681 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
682 "fsl,imx7ulp-lpuart";
686 clock-names = "ipg";
688 dma-names = "rx", "tx";
693 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
694 "fsl,imx7ulp-lpuart";
698 clock-names = "ipg";
700 dma-names = "rx", "tx";
705 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
706 "fsl,imx7ulp-lpuart";
710 clock-names = "ipg";
712 dma-names = "rx", "tx";
717 compatible = "fsl,imx95-flexcan";
722 clock-names = "ipg", "per";
723 assigned-clocks = <&scmi_clk IMX95_CLK_CAN2>;
724 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
725 assigned-clock-rates = <40000000>;
726 fsl,clk-source = /bits/ 8 <0>;
731 compatible = "fsl,imx95-flexcan";
736 clock-names = "ipg", "per";
737 assigned-clocks = <&scmi_clk IMX95_CLK_CAN3>;
738 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
739 assigned-clock-rates = <40000000>;
740 fsl,clk-source = /bits/ 8 <0>;
745 compatible = "nxp,imx8mm-fspi";
747 reg-names = "fspi_base", "fspi_mmap";
748 #address-cells = <1>;
749 #size-cells = <0>;
753 clock-names = "fspi_en", "fspi";
754 assigned-clocks = <&scmi_clk IMX95_CLK_FLEXSPI1>;
755 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>;
756 assigned-clock-rates = <200000000>;
761 compatible = "fsl,imx95-sai";
767 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
769 dma-names = "rx", "tx";
774 compatible = "fsl,imx95-sai";
780 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
782 dma-names = "rx", "tx";
787 compatible = "fsl,imx95-sai";
793 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
795 dma-names = "rx", "tx";
800 compatible = "fsl,imx95-xcvr";
803 reg-names = "ram", "regs", "rxfifo", "txfifo";
812 clock-names = "ipg", "phy", "spba", "pll_ipg";
814 dma-names = "rx", "tx";
819 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
820 "fsl,imx7ulp-lpuart";
824 clock-names = "ipg";
826 dma-names = "rx", "tx";
831 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
832 "fsl,imx7ulp-lpuart";
836 clock-names = "ipg";
838 dma-names = "rx", "tx";
843 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
848 clock-names = "per", "ipg";
849 #address-cells = <1>;
850 #size-cells = <0>;
852 dma-names = "tx", "rx";
857 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
862 clock-names = "per", "ipg";
863 #address-cells = <1>;
864 #size-cells = <0>;
866 dma-names = "tx", "rx";
871 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
876 clock-names = "per", "ipg";
877 #address-cells = <1>;
878 #size-cells = <0>;
880 dma-names = "tx", "rx";
885 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
890 clock-names = "per", "ipg";
891 #address-cells = <1>;
892 #size-cells = <0>;
894 dma-names = "tx", "rx";
899 #address-cells = <1>;
900 #size-cells = <0>;
901 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
906 clock-names = "per", "ipg";
908 dma-names = "tx", "rx";
913 #address-cells = <1>;
914 #size-cells = <0>;
915 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
920 clock-names = "per", "ipg";
922 dma-names = "tx", "rx";
927 #address-cells = <1>;
928 #size-cells = <0>;
929 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
934 clock-names = "per", "ipg";
936 dma-names = "tx", "rx";
941 #address-cells = <1>;
942 #size-cells = <0>;
943 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
948 clock-names = "per", "ipg";
950 dma-names = "tx", "rx";
955 compatible = "fsl,imx95-mu";
959 #mbox-cells = <2>;
964 compatible = "fsl,imx95-flexcan";
969 clock-names = "ipg", "per";
970 assigned-clocks = <&scmi_clk IMX95_CLK_CAN4>;
971 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
972 assigned-clock-rates = <40000000>;
973 fsl,clk-source = /bits/ 8 <0>;
978 compatible = "fsl,imx95-flexcan";
983 clock-names = "ipg", "per";
984 assigned-clocks = <&scmi_clk IMX95_CLK_CAN5>;
985 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
986 assigned-clock-rates = <40000000>;
987 fsl,clk-source = /bits/ 8 <0>;
993 compatible = "fsl,aips-bus", "simple-bus";
995 #address-cells = <1>;
996 #size-cells = <1>;
1000 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc";
1006 clock-names = "ipg", "ahb", "per";
1007 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC1>;
1008 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>;
1009 assigned-clock-rates = <400000000>;
1010 bus-width = <8>;
1011 fsl,tuning-start-tap = <1>;
1012 fsl,tuning-step= <2>;
1017 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc";
1023 clock-names = "ipg", "ahb", "per";
1024 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC2>;
1025 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>;
1026 assigned-clock-rates = <400000000>;
1027 bus-width = <4>;
1028 fsl,tuning-start-tap = <1>;
1029 fsl,tuning-step= <2>;
1034 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc";
1040 clock-names = "ipg", "ahb", "per";
1041 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC3>;
1042 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>;
1043 assigned-clock-rates = <400000000>;
1044 bus-width = <4>;
1045 fsl,tuning-start-tap = <1>;
1046 fsl,tuning-step= <2>;
1052 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
1054 gpio-controller;
1055 #gpio-cells = <2>;
1058 interrupt-controller;
1059 #interrupt-cells = <2>;
1062 clock-names = "gpio", "port";
1063 gpio-ranges = <&scmi_iomuxc 0 4 32>;
1067 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
1069 gpio-controller;
1070 #gpio-cells = <2>;
1073 interrupt-controller;
1074 #interrupt-cells = <2>;
1077 clock-names = "gpio", "port";
1078 gpio-ranges = <&scmi_iomuxc 0 104 8>, <&scmi_iomuxc 8 74 18>,
1083 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
1085 gpio-controller;
1086 #gpio-cells = <2>;
1089 interrupt-controller;
1090 #interrupt-cells = <2>;
1093 clock-names = "gpio", "port";
1094 gpio-ranges = <&scmi_iomuxc 0 46 28>, <&scmi_iomuxc 28 44 2>;
1098 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
1100 gpio-controller;
1101 #gpio-cells = <2>;
1104 interrupt-controller;
1105 #interrupt-cells = <2>;
1108 clock-names = "gpio", "port";
1109 gpio-ranges = <&scmi_iomuxc 0 92 12>, <&scmi_iomuxc 12 36 6>;
1113 compatible = "fsl,aips-bus", "simple-bus";
1116 #address-cells = <1>;
1117 #size-cells = <1>;
1119 edma1: dma-controller@44000000 {
1120 compatible = "fsl,imx93-edma3";
1122 #dma-cells = <3>;
1123 dma-channels = <31>;
1156 clock-names = "dma";
1160 compatible = "fsl,imx95-mu";
1164 #mbox-cells = <2>;
1169 compatible = "fsl,imx7ulp-pwm";
1172 #pwm-cells = <3>;
1177 compatible = "fsl,imx7ulp-pwm";
1180 #pwm-cells = <3>;
1185 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
1190 clock-names = "per", "ipg";
1191 #address-cells = <1>;
1192 #size-cells = <0>;
1194 dma-names = "tx", "rx";
1199 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
1204 clock-names = "per", "ipg";
1205 #address-cells = <1>;
1206 #size-cells = <0>;
1208 dma-names = "tx", "rx";
1213 #address-cells = <1>;
1214 #size-cells = <0>;
1215 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
1220 clock-names = "per", "ipg";
1222 dma-names = "tx", "rx";
1227 #address-cells = <1>;
1228 #size-cells = <0>;
1229 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
1234 clock-names = "per", "ipg";
1236 dma-names = "tx", "rx";
1241 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
1242 "fsl,imx7ulp-lpuart";
1246 clock-names = "ipg";
1248 dma-names = "rx", "tx";
1253 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
1254 "fsl,imx7ulp-lpuart";
1258 clock-names = "ipg";
1260 dma-names = "rx", "tx";
1265 compatible = "fsl,imx95-flexcan";
1270 clock-names = "ipg", "per";
1271 assigned-clocks = <&scmi_clk IMX95_CLK_CAN1>;
1272 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
1273 assigned-clock-rates = <40000000>;
1274 fsl,clk-source = /bits/ 8 <0>;
1279 compatible = "fsl,imx95-sai";
1285 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1287 dma-names = "rx", "tx";
1292 compatible = "fsl,imx95-micfil", "fsl,imx93-micfil";
1303 clock-names = "ipg_clk", "ipg_clk_app",
1306 dma-names = "rx";
1311 compatible = "nxp,imx93-adc";
1317 clock-names = "ipg";
1322 compatible = "fsl,imx95-mu";
1326 #address-cells = <1>;
1327 #size-cells = <1>;
1328 #mbox-cells = <2>;
1331 compatible = "mmio-sram";
1334 #address-cells = <1>;
1335 #size-cells = <1>;
1337 scmi_buf0: scmi-sram-section@0 {
1338 compatible = "arm,scmi-shmem";
1342 scmi_buf1: scmi-sram-section@80 {
1343 compatible = "arm,scmi-shmem";
1351 compatible = "fsl,imx95-mu";
1355 #mbox-cells = <2>;
1360 compatible = "fsl,imx95-mu";
1364 #mbox-cells = <2>;
1369 compatible = "fsl,imx95-mu";
1373 #mbox-cells = <2>;
1379 compatible = "fsl,imx95-mu-v2x";
1382 #mbox-cells = <2>;
1386 compatible = "fsl,imx95-mu-v2x";
1389 #mbox-cells = <2>;
1394 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
1396 gpio-controller;
1397 #gpio-cells = <2>;
1400 interrupt-controller;
1401 #interrupt-cells = <2>;
1404 clock-names = "gpio", "port";
1405 gpio-ranges = <&scmi_iomuxc 0 112 16>;
1410 compatible = "fsl,imx95-mu-ele";
1413 #mbox-cells = <2>;
1418 compatible = "fsl,imx95-mu-ele";
1421 #mbox-cells = <2>;
1426 compatible = "fsl,imx95-mu-ele";
1429 #mbox-cells = <2>;
1434 compatible = "fsl,imx95-mu-ele";
1437 #mbox-cells = <2>;
1441 compatible = "fsl,imx95-mu-ele";
1444 #mbox-cells = <2>;
1449 compatible = "fsl,imx95-mu-ele";
1452 #mbox-cells = <2>;
1457 compatible = "fsl,aips-bus", "simple-bus";
1460 #address-cells = <1>;
1461 #size-cells = <1>;
1464 compatible = "arm,smmu-v3";
1470 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
1471 #iommu-cells = <1>;
1477 compatible = "fsl,imx95-pcie";
1482 reg-names = "dbi", "config", "atu", "app";
1485 #address-cells = <3>;
1486 #size-cells = <2>;
1488 linux,pci-domain = <0>;
1489 bus-range = <0x00 0xff>;
1490 num-lanes = <1>;
1491 num-viewport = <8>;
1493 interrupt-names = "msi";
1494 #interrupt-cells = <1>;
1495 interrupt-map-mask = <0 0 0 0x7>;
1496 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
1504 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
1505 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
1508 assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
1509 assigned-clock-parents = <0>, <0>,
1511 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
1512 fsl,max-link-speed = <3>;
1516 pcie0_ep: pcie-ep@4c300000 {
1517 compatible = "fsl,imx95-pcie-ep";
1524 reg-names = "dbi","atu", "dbi2", "app", "dma", "addr_space";
1525 num-lanes = <1>;
1527 interrupt-names = "dma";
1532 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
1533 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
1536 assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
1537 assigned-clock-parents = <0>, <0>,
1539 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
1544 compatible = "fsl,imx95-pcie";
1549 reg-names = "dbi", "config", "atu", "app";
1552 #address-cells = <3>;
1553 #size-cells = <2>;
1555 linux,pci-domain = <1>;
1556 bus-range = <0x00 0xff>;
1557 num-lanes = <1>;
1558 num-viewport = <8>;
1560 interrupt-names = "msi";
1561 #interrupt-cells = <1>;
1562 interrupt-map-mask = <0 0 0 0x7>;
1563 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1571 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
1572 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
1575 assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
1576 assigned-clock-parents = <0>, <0>,
1578 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
1579 fsl,max-link-speed = <3>;
1583 pcie1_ep: pcie-ep@4c380000 {
1584 compatible = "fsl,imx95-pcie-ep";
1591 reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space";
1592 num-lanes = <1>;
1594 interrupt-names = "dma";
1599 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
1600 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
1603 assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
1604 assigned-clock-parents = <0>, <0>,
1606 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
1611 compatible = "nxp,imx95-netcmix-blk-ctrl", "syscon";
1613 #clock-cells = <1>;
1615 assigned-clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>;
1616 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
1617 assigned-clock-rates = <133333333>;
1618 power-domains = <&scmi_devpd IMX95_PD_NETC>;
1623 compatible = "fsl,imx95-sai";
1629 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1630 power-domains = <&scmi_devpd IMX95_PD_NETC>;
1632 dma-names = "rx", "tx";
1636 ddr-pmu@4e090dc0 {
1637 compatible = "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu";