Lines Matching +full:imx7d +full:- +full:pcie +full:- +full:phy
1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
6 #include <dt-bindings/clock/nxp,imx95-clock.h>
7 #include <dt-bindings/dma/fsl-edma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
13 #include "imx95-clock.h"
14 #include "imx95-pinfunc.h"
15 #include "imx95-power.h"
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
23 #address-cells = <1>;
24 #size-cells = <0>;
26 idle-states {
27 entry-method = "psci";
29 cpu_pd_wait: cpu-pd-wait {
30 compatible = "arm,idle-state";
31 arm,psci-suspend-param = <0x0010033>;
32 local-timer-stop;
33 entry-latency-us = <10000>;
34 exit-latency-us = <7000>;
35 min-residency-us = <27000>;
36 wakeup-latency-us = <15000>;
42 compatible = "arm,cortex-a55";
44 enable-method = "psci";
45 #cooling-cells = <2>;
46 cpu-idle-states = <&cpu_pd_wait>;
47 power-domains = <&scmi_perf IMX95_PERF_A55>;
48 power-domain-names = "perf";
49 i-cache-size = <32768>;
50 i-cache-line-size = <64>;
51 i-cache-sets = <128>;
52 d-cache-size = <32768>;
53 d-cache-line-size = <64>;
54 d-cache-sets = <128>;
55 next-level-cache = <&l2_cache_l0>;
60 compatible = "arm,cortex-a55";
62 enable-method = "psci";
63 #cooling-cells = <2>;
64 cpu-idle-states = <&cpu_pd_wait>;
65 power-domains = <&scmi_perf IMX95_PERF_A55>;
66 power-domain-names = "perf";
67 i-cache-size = <32768>;
68 i-cache-line-size = <64>;
69 i-cache-sets = <128>;
70 d-cache-size = <32768>;
71 d-cache-line-size = <64>;
72 d-cache-sets = <128>;
73 next-level-cache = <&l2_cache_l1>;
78 compatible = "arm,cortex-a55";
80 enable-method = "psci";
81 #cooling-cells = <2>;
82 cpu-idle-states = <&cpu_pd_wait>;
83 power-domains = <&scmi_perf IMX95_PERF_A55>;
84 power-domain-names = "perf";
85 i-cache-size = <32768>;
86 i-cache-line-size = <64>;
87 i-cache-sets = <128>;
88 d-cache-size = <32768>;
89 d-cache-line-size = <64>;
90 d-cache-sets = <128>;
91 next-level-cache = <&l2_cache_l2>;
96 compatible = "arm,cortex-a55";
98 enable-method = "psci";
99 #cooling-cells = <2>;
100 cpu-idle-states = <&cpu_pd_wait>;
101 power-domains = <&scmi_perf IMX95_PERF_A55>;
102 power-domain-names = "perf";
103 i-cache-size = <32768>;
104 i-cache-line-size = <64>;
105 i-cache-sets = <128>;
106 d-cache-size = <32768>;
107 d-cache-line-size = <64>;
108 d-cache-sets = <128>;
109 next-level-cache = <&l2_cache_l3>;
114 compatible = "arm,cortex-a55";
116 power-domains = <&scmi_perf IMX95_PERF_A55>;
117 power-domain-names = "perf";
118 enable-method = "psci";
119 #cooling-cells = <2>;
120 cpu-idle-states = <&cpu_pd_wait>;
121 i-cache-size = <32768>;
122 i-cache-line-size = <64>;
123 i-cache-sets = <128>;
124 d-cache-size = <32768>;
125 d-cache-line-size = <64>;
126 d-cache-sets = <128>;
127 next-level-cache = <&l2_cache_l4>;
132 compatible = "arm,cortex-a55";
134 power-domains = <&scmi_perf IMX95_PERF_A55>;
135 power-domain-names = "perf";
136 enable-method = "psci";
137 #cooling-cells = <2>;
138 cpu-idle-states = <&cpu_pd_wait>;
139 i-cache-size = <32768>;
140 i-cache-line-size = <64>;
141 i-cache-sets = <128>;
142 d-cache-size = <32768>;
143 d-cache-line-size = <64>;
144 d-cache-sets = <128>;
145 next-level-cache = <&l2_cache_l5>;
148 l2_cache_l0: l2-cache-l0 {
150 cache-size = <65536>;
151 cache-line-size = <64>;
152 cache-sets = <256>;
153 cache-level = <2>;
154 cache-unified;
155 next-level-cache = <&l3_cache>;
158 l2_cache_l1: l2-cache-l1 {
160 cache-size = <65536>;
161 cache-line-size = <64>;
162 cache-sets = <256>;
163 cache-level = <2>;
164 cache-unified;
165 next-level-cache = <&l3_cache>;
168 l2_cache_l2: l2-cache-l2 {
170 cache-size = <65536>;
171 cache-line-size = <64>;
172 cache-sets = <256>;
173 cache-level = <2>;
174 cache-unified;
175 next-level-cache = <&l3_cache>;
178 l2_cache_l3: l2-cache-l3 {
180 cache-size = <65536>;
181 cache-line-size = <64>;
182 cache-sets = <256>;
183 cache-level = <2>;
184 cache-unified;
185 next-level-cache = <&l3_cache>;
188 l2_cache_l4: l2-cache-l4 {
190 cache-size = <65536>;
191 cache-line-size = <64>;
192 cache-sets = <256>;
193 cache-level = <2>;
194 cache-unified;
195 next-level-cache = <&l3_cache>;
198 l2_cache_l5: l2-cache-l5 {
200 cache-size = <65536>;
201 cache-line-size = <64>;
202 cache-sets = <256>;
203 cache-level = <2>;
204 cache-unified;
205 next-level-cache = <&l3_cache>;
208 l3_cache: l3-cache {
210 cache-size = <524288>;
211 cache-line-size = <64>;
212 cache-sets = <512>;
213 cache-level = <3>;
214 cache-unified;
217 cpu-map {
246 dummy: clock-dummy {
247 compatible = "fixed-clock";
248 #clock-cells = <0>;
249 clock-frequency = <0>;
250 clock-output-names = "dummy";
253 clk_ext1: clock-ext1 {
254 compatible = "fixed-clock";
255 #clock-cells = <0>;
256 clock-frequency = <133000000>;
257 clock-output-names = "clk_ext1";
260 sai1_mclk: clock-sai-mclk1 {
261 compatible = "fixed-clock";
262 #clock-cells = <0>;
263 clock-frequency= <0>;
264 clock-output-names = "sai1_mclk";
267 sai2_mclk: clock-sai-mclk2 {
268 compatible = "fixed-clock";
269 #clock-cells = <0>;
270 clock-frequency= <0>;
271 clock-output-names = "sai2_mclk";
274 sai3_mclk: clock-sai-mclk3 {
275 compatible = "fixed-clock";
276 #clock-cells = <0>;
277 clock-frequency= <0>;
278 clock-output-names = "sai3_mclk";
281 sai4_mclk: clock-sai-mclk4 {
282 compatible = "fixed-clock";
283 #clock-cells = <0>;
284 clock-frequency= <0>;
285 clock-output-names = "sai4_mclk";
288 sai5_mclk: clock-sai-mclk5 {
289 compatible = "fixed-clock";
290 #clock-cells = <0>;
291 clock-frequency= <0>;
292 clock-output-names = "sai5_mclk";
295 clk_sys100m: clock-sys100m {
296 compatible = "fixed-clock";
297 #clock-cells = <0>;
298 clock-frequency = <100000000>;
299 clock-output-names = "clk_sys100m";
302 osc_24m: clock-24m {
303 compatible = "fixed-clock";
304 #clock-cells = <0>;
305 clock-frequency = <24000000>;
306 clock-output-names = "osc_24m";
310 compatible = "mmio-sram";
313 #address-cells = <1>;
314 #size-cells = <1>;
322 #address-cells = <1>;
323 #size-cells = <0>;
324 arm,max-rx-timeout-ms = <5000>;
328 #power-domain-cells = <1>;
337 #power-domain-cells = <1>;
342 #clock-cells = <1>;
347 #thermal-sensor-cells = <1>;
365 compatible = "arm,cortex-a55-pmu";
369 thermal_zones: thermal-zones {
370 a55-thermal {
371 polling-delay-passive = <250>;
372 polling-delay = <2000>;
373 thermal-sensors = <&scmi_sensor 1>;
389 cooling-maps {
392 cooling-device =
403 ana-thermal {
404 polling-delay-passive = <250>;
405 polling-delay = <2000>;
406 thermal-sensors = <&scmi_sensor 0>;
421 cooling-maps {
424 cooling-device =
437 compatible = "arm,psci-1.0";
442 compatible = "arm,armv8-timer";
447 clock-frequency = <24000000>;
448 arm,no-tick-in-suspend;
449 interrupt-parent = <&gic>;
452 gic: interrupt-controller@48000000 {
453 compatible = "arm,gic-v3";
456 #address-cells = <2>;
457 #size-cells = <2>;
458 #interrupt-cells = <3>;
459 interrupt-controller;
461 interrupt-parent = <&gic>;
462 dma-noncoherent;
465 its: msi-controller@48040000 {
466 compatible = "arm,gic-v3-its";
468 msi-controller;
469 #msi-cells = <1>;
470 dma-noncoherent;
475 compatible = "usb-nop-xceiv";
477 clock-names = "main_clk";
478 #phy-cells = <0>;
482 compatible = "simple-bus";
483 #address-cells = <2>;
484 #size-cells = <2>;
488 compatible = "fsl,aips-bus", "simple-bus";
492 #address-cells = <1>;
493 #size-cells = <1>;
495 edma2: dma-controller@42000000 {
496 compatible = "fsl,imx95-edma5";
498 #dma-cells = <3>;
499 dma-channels = <64>;
565 clock-names = "dma";
568 edma3: dma-controller@42210000 {
569 compatible = "fsl,imx95-edma5";
571 #dma-cells = <3>;
572 dma-channels = <64>;
638 clock-names = "dma";
642 compatible = "fsl,imx95-mu";
646 #mbox-cells = <2>;
651 compatible = "fsl,imx93-wdt";
655 timeout-sec = <40>;
660 compatible = "fsl,imx7ulp-pwm";
663 #pwm-cells = <3>;
668 compatible = "fsl,imx7ulp-pwm";
671 #pwm-cells = <3>;
676 compatible = "fsl,imx7ulp-pwm";
679 #pwm-cells = <3>;
684 compatible = "fsl,imx7ulp-pwm";
687 #pwm-cells = <3>;
692 compatible = "nxp,imx95-i3c", "silvaco,i3c-master-v1";
695 #address-cells = <3>;
696 #size-cells = <0>;
699 clock-names = "pclk", "fast_clk";
704 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
709 clock-names = "per", "ipg";
710 #address-cells = <1>;
711 #size-cells = <0>;
713 dma-names = "tx", "rx";
718 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
723 clock-names = "per", "ipg";
724 #address-cells = <1>;
725 #size-cells = <0>;
727 dma-names = "tx", "rx";
732 #address-cells = <1>;
733 #size-cells = <0>;
734 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
739 clock-names = "per", "ipg";
741 dma-names = "tx", "rx";
746 #address-cells = <1>;
747 #size-cells = <0>;
748 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
753 clock-names = "per", "ipg";
755 dma-names = "tx", "rx";
760 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
761 "fsl,imx7ulp-lpuart";
765 clock-names = "ipg";
767 dma-names = "rx", "tx";
772 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
773 "fsl,imx7ulp-lpuart";
777 clock-names = "ipg";
779 dma-names = "rx", "tx";
784 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
785 "fsl,imx7ulp-lpuart";
789 clock-names = "ipg";
791 dma-names = "rx", "tx";
796 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
797 "fsl,imx7ulp-lpuart";
801 clock-names = "ipg";
803 dma-names = "rx", "tx";
808 compatible = "fsl,imx95-flexcan";
813 clock-names = "ipg", "per";
814 assigned-clocks = <&scmi_clk IMX95_CLK_CAN2>;
815 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
816 assigned-clock-rates = <40000000>;
817 fsl,clk-source = /bits/ 8 <0>;
822 compatible = "fsl,imx95-flexcan";
827 clock-names = "ipg", "per";
828 assigned-clocks = <&scmi_clk IMX95_CLK_CAN3>;
829 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
830 assigned-clock-rates = <40000000>;
831 fsl,clk-source = /bits/ 8 <0>;
836 compatible = "nxp,imx8mm-fspi";
838 reg-names = "fspi_base", "fspi_mmap";
839 #address-cells = <1>;
840 #size-cells = <0>;
844 clock-names = "fspi_en", "fspi";
845 assigned-clocks = <&scmi_clk IMX95_CLK_FLEXSPI1>;
846 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>;
847 assigned-clock-rates = <200000000>;
852 compatible = "fsl,imx95-sai";
858 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
860 dma-names = "rx", "tx";
865 compatible = "fsl,imx95-sai";
871 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
873 dma-names = "rx", "tx";
878 compatible = "fsl,imx95-sai";
884 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
886 dma-names = "rx", "tx";
891 compatible = "fsl,imx95-xcvr";
894 reg-names = "ram", "regs", "rxfifo", "txfifo";
903 clock-names = "ipg", "phy", "spba", "pll_ipg";
905 dma-names = "rx", "tx";
910 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
911 "fsl,imx7ulp-lpuart";
915 clock-names = "ipg";
917 dma-names = "rx", "tx";
922 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
923 "fsl,imx7ulp-lpuart";
927 clock-names = "ipg";
929 dma-names = "rx", "tx";
934 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
939 clock-names = "per", "ipg";
940 #address-cells = <1>;
941 #size-cells = <0>;
943 dma-names = "tx", "rx";
948 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
953 clock-names = "per", "ipg";
954 #address-cells = <1>;
955 #size-cells = <0>;
957 dma-names = "tx", "rx";
962 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
967 clock-names = "per", "ipg";
968 #address-cells = <1>;
969 #size-cells = <0>;
971 dma-names = "tx", "rx";
976 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
981 clock-names = "per", "ipg";
982 #address-cells = <1>;
983 #size-cells = <0>;
985 dma-names = "tx", "rx";
990 #address-cells = <1>;
991 #size-cells = <0>;
992 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
997 clock-names = "per", "ipg";
999 dma-names = "tx", "rx";
1004 #address-cells = <1>;
1005 #size-cells = <0>;
1006 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
1011 clock-names = "per", "ipg";
1013 dma-names = "tx", "rx";
1018 #address-cells = <1>;
1019 #size-cells = <0>;
1020 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
1025 clock-names = "per", "ipg";
1027 dma-names = "tx", "rx";
1032 #address-cells = <1>;
1033 #size-cells = <0>;
1034 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
1039 clock-names = "per", "ipg";
1041 dma-names = "tx", "rx";
1046 compatible = "fsl,imx95-mu";
1050 #mbox-cells = <2>;
1055 compatible = "fsl,imx95-flexcan";
1060 clock-names = "ipg", "per";
1061 assigned-clocks = <&scmi_clk IMX95_CLK_CAN4>;
1062 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
1063 assigned-clock-rates = <40000000>;
1064 fsl,clk-source = /bits/ 8 <0>;
1069 compatible = "fsl,imx95-flexcan";
1074 clock-names = "ipg", "per";
1075 assigned-clocks = <&scmi_clk IMX95_CLK_CAN5>;
1076 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
1077 assigned-clock-rates = <40000000>;
1078 fsl,clk-source = /bits/ 8 <0>;
1084 compatible = "fsl,aips-bus", "simple-bus";
1086 #address-cells = <1>;
1087 #size-cells = <1>;
1091 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc";
1097 clock-names = "ipg", "ahb", "per";
1098 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC1>;
1099 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>;
1100 assigned-clock-rates = <400000000>;
1101 bus-width = <8>;
1102 fsl,tuning-start-tap = <1>;
1103 fsl,tuning-step= <2>;
1108 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc";
1114 clock-names = "ipg", "ahb", "per";
1115 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC2>;
1116 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>;
1117 assigned-clock-rates = <400000000>;
1118 bus-width = <4>;
1119 fsl,tuning-start-tap = <1>;
1120 fsl,tuning-step= <2>;
1125 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc";
1131 clock-names = "ipg", "ahb", "per";
1132 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC3>;
1133 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>;
1134 assigned-clock-rates = <400000000>;
1135 bus-width = <4>;
1136 fsl,tuning-start-tap = <1>;
1137 fsl,tuning-step= <2>;
1143 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
1145 gpio-controller;
1146 #gpio-cells = <2>;
1149 interrupt-controller;
1150 #interrupt-cells = <2>;
1153 clock-names = "gpio", "port";
1154 gpio-ranges = <&scmi_iomuxc 0 4 32>;
1159 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
1161 gpio-controller;
1162 #gpio-cells = <2>;
1165 interrupt-controller;
1166 #interrupt-cells = <2>;
1169 clock-names = "gpio", "port";
1170 gpio-ranges = <&scmi_iomuxc 0 104 8>, <&scmi_iomuxc 8 74 18>,
1176 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
1178 gpio-controller;
1179 #gpio-cells = <2>;
1182 interrupt-controller;
1183 #interrupt-cells = <2>;
1186 clock-names = "gpio", "port";
1187 gpio-ranges = <&scmi_iomuxc 0 46 28>, <&scmi_iomuxc 28 44 2>;
1192 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
1194 gpio-controller;
1195 #gpio-cells = <2>;
1198 interrupt-controller;
1199 #interrupt-cells = <2>;
1202 clock-names = "gpio", "port";
1203 gpio-ranges = <&scmi_iomuxc 0 92 12>, <&scmi_iomuxc 12 36 6>;
1208 compatible = "fsl,aips-bus", "simple-bus";
1211 #address-cells = <1>;
1212 #size-cells = <1>;
1214 edma1: dma-controller@44000000 {
1215 compatible = "fsl,imx93-edma3";
1217 #dma-cells = <3>;
1218 dma-channels = <31>;
1251 clock-names = "dma";
1255 compatible = "fsl,imx95-mu";
1259 #mbox-cells = <2>;
1264 compatible = "fsl,imx7ulp-pwm";
1267 #pwm-cells = <3>;
1272 compatible = "fsl,imx7ulp-pwm";
1275 #pwm-cells = <3>;
1280 compatible = "nxp,imx95-i3c", "silvaco,i3c-master-v1";
1283 #address-cells = <3>;
1284 #size-cells = <0>;
1287 clock-names = "pclk", "fast_clk";
1292 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
1297 clock-names = "per", "ipg";
1298 #address-cells = <1>;
1299 #size-cells = <0>;
1301 dma-names = "tx", "rx";
1306 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
1311 clock-names = "per", "ipg";
1312 #address-cells = <1>;
1313 #size-cells = <0>;
1315 dma-names = "tx", "rx";
1320 #address-cells = <1>;
1321 #size-cells = <0>;
1322 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
1327 clock-names = "per", "ipg";
1329 dma-names = "tx", "rx";
1334 #address-cells = <1>;
1335 #size-cells = <0>;
1336 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
1341 clock-names = "per", "ipg";
1343 dma-names = "tx", "rx";
1348 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
1349 "fsl,imx7ulp-lpuart";
1353 clock-names = "ipg";
1355 dma-names = "rx", "tx";
1360 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
1361 "fsl,imx7ulp-lpuart";
1365 clock-names = "ipg";
1367 dma-names = "rx", "tx";
1372 compatible = "fsl,imx95-flexcan";
1377 clock-names = "ipg", "per";
1378 assigned-clocks = <&scmi_clk IMX95_CLK_CAN1>;
1379 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
1380 assigned-clock-rates = <40000000>;
1381 fsl,clk-source = /bits/ 8 <0>;
1386 compatible = "fsl,imx95-sai";
1392 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1394 dma-names = "rx", "tx";
1399 compatible = "fsl,imx95-micfil", "fsl,imx93-micfil";
1410 clock-names = "ipg_clk", "ipg_clk_app",
1413 dma-names = "rx";
1418 compatible = "nxp,imx93-adc";
1424 clock-names = "ipg";
1425 #io-channel-cells = <1>;
1430 compatible = "fsl,imx95-mu";
1434 #address-cells = <1>;
1435 #size-cells = <1>;
1436 #mbox-cells = <2>;
1439 compatible = "mmio-sram";
1442 #address-cells = <1>;
1443 #size-cells = <1>;
1445 scmi_buf0: scmi-sram-section@0 {
1446 compatible = "arm,scmi-shmem";
1450 scmi_buf1: scmi-sram-section@80 {
1451 compatible = "arm,scmi-shmem";
1459 compatible = "fsl,imx95-mu";
1463 #mbox-cells = <2>;
1468 compatible = "fsl,imx95-mu";
1472 #mbox-cells = <2>;
1477 compatible = "fsl,imx95-mu";
1481 #mbox-cells = <2>;
1487 compatible = "fsl,imx95-mu-v2x";
1490 #mbox-cells = <2>;
1494 compatible = "fsl,imx95-mu-v2x";
1497 #mbox-cells = <2>;
1502 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
1504 gpio-controller;
1505 #gpio-cells = <2>;
1508 interrupt-controller;
1509 #interrupt-cells = <2>;
1512 clock-names = "gpio", "port";
1513 gpio-ranges = <&scmi_iomuxc 0 112 16>;
1519 compatible = "fsl,imx95-mu-ele";
1522 #mbox-cells = <2>;
1527 compatible = "fsl,imx95-mu-ele";
1530 #mbox-cells = <2>;
1535 compatible = "fsl,imx95-mu-ele";
1538 #mbox-cells = <2>;
1543 compatible = "fsl,imx95-mu-ele";
1546 #mbox-cells = <2>;
1550 compatible = "fsl,imx95-mu-ele";
1553 #mbox-cells = <2>;
1558 compatible = "fsl,imx95-mu-ele";
1561 #mbox-cells = <2>;
1566 compatible = "fsl,aips-bus", "simple-bus";
1569 #address-cells = <1>;
1570 #size-cells = <1>;
1573 compatible = "arm,smmu-v3";
1579 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
1580 #iommu-cells = <1>;
1586 compatible = "fsl,imx95-dwc3", "fsl,imx8mp-dwc3";
1591 clock-names = "hsio", "suspend";
1593 #address-cells = <2>;
1594 #size-cells = <2>;
1596 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
1597 dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
1606 clock-names = "bus_early", "ref", "suspend";
1609 phy-names = "usb2-phy", "usb3-phy";
1610 snps,gfladj-refclk-lpm-sel-quirk;
1611 snps,parkmode-disable-ss-quirk;
1617 compatible = "nxp,imx95-hsio-blk-ctl", "syscon";
1619 #clock-cells = <1>;
1621 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
1624 usb3_phy: phy@4c1f0040 {
1625 compatible = "fsl,imx95-usb-phy", "fsl,imx8mp-usb-phy";
1629 clock-names = "phy";
1630 #phy-cells = <0>;
1631 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
1636 compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
1642 clock-names = "usb_ctrl_root", "usb_wakeup";
1645 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
1651 compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc",
1652 "fsl,imx6q-usbmisc";
1655 #index-cells = <1>;
1658 pcie0: pcie@4c300000 {
1659 compatible = "fsl,imx95-pcie";
1664 reg-names = "dbi", "config", "atu", "app";
1667 #address-cells = <3>;
1668 #size-cells = <2>;
1670 linux,pci-domain = <0>;
1671 bus-range = <0x00 0xff>;
1672 num-lanes = <1>;
1673 num-viewport = <8>;
1675 interrupt-names = "msi";
1676 #interrupt-cells = <1>;
1677 interrupt-map-mask = <0 0 0 0x7>;
1678 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
1687 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
1688 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
1691 assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
1692 assigned-clock-parents = <0>, <0>,
1694 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
1696 msi-map = <0x0 &its 0x10 0x1>,
1698 iommu-map = <0x000 &smmu 0x10 0x1>,
1700 iommu-map-mask = <0x1ff>;
1701 fsl,max-link-speed = <3>;
1705 pcie0_ep: pcie-ep@4c300000 {
1706 compatible = "fsl,imx95-pcie-ep";
1713 reg-names = "dbi","atu", "dbi2", "app", "dma", "addr_space";
1714 num-lanes = <1>;
1716 interrupt-names = "dma";
1721 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
1722 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
1725 assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
1726 assigned-clock-parents = <0>, <0>,
1728 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
1732 pcie1: pcie@4c380000 {
1733 compatible = "fsl,imx95-pcie";
1738 reg-names = "dbi", "config", "atu", "app";
1741 #address-cells = <3>;
1742 #size-cells = <2>;
1744 linux,pci-domain = <1>;
1745 bus-range = <0x00 0xff>;
1746 num-lanes = <1>;
1747 num-viewport = <8>;
1749 interrupt-names = "msi";
1750 #interrupt-cells = <1>;
1751 interrupt-map-mask = <0 0 0 0x7>;
1752 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1761 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
1762 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
1765 assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
1766 assigned-clock-parents = <0>, <0>,
1768 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
1770 msi-map = <0x0 &its 0x98 0x1>,
1772 msi-map-mask = <0x1ff>;
1774 iommu-map = <0x000 &smmu 0x18 0x1>,
1776 iommu-map-mask = <0x1ff>;
1777 fsl,max-link-speed = <3>;
1781 pcie1_ep: pcie-ep@4c380000 {
1782 compatible = "fsl,imx95-pcie-ep";
1789 reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space";
1790 num-lanes = <1>;
1792 interrupt-names = "dma";
1797 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
1798 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
1801 assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
1802 assigned-clock-parents = <0>, <0>,
1804 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
1808 vpu_blk_ctrl: clock-controller@4c410000 {
1809 compatible = "nxp,imx95-vpu-csr", "syscon";
1811 #clock-cells = <1>;
1813 power-domains = <&scmi_devpd IMX95_PD_VPU>;
1814 assigned-clocks = <&scmi_clk IMX95_CLK_VPUAPB>,
1817 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>,
1820 assigned-clock-rates = <133333333>, <667000000>, <500000000>;
1824 compatible = "nxp,imx95-jpgdec", "nxp,imx8qxp-jpgdec";
1832 assigned-clocks = <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_DEC>;
1833 assigned-clock-parents = <&scmi_clk IMX95_CLK_VPUJPEG>;
1834 power-domains = <&scmi_devpd IMX95_PD_VPU>;
1838 compatible = "nxp,imx95-jpgenc", "nxp,imx8qxp-jpgenc";
1846 assigned-clocks = <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_DEC>;
1847 assigned-clock-parents = <&scmi_clk IMX95_CLK_VPUJPEG>;
1848 power-domains = <&scmi_devpd IMX95_PD_VPU>;
1852 compatible = "nxp,imx95-netcmix-blk-ctrl", "syscon";
1854 #clock-cells = <1>;
1856 assigned-clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>;
1857 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
1858 assigned-clock-rates = <133333333>;
1859 power-domains = <&scmi_devpd IMX95_PD_NETC>;
1864 compatible = "fsl,imx95-sai";
1870 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1871 power-domains = <&scmi_devpd IMX95_PD_NETC>;
1873 dma-names = "rx", "tx";
1877 netc_blk_ctrl: system-controller@4cde0000 {
1878 compatible = "nxp,imx95-netc-blk-ctrl";
1882 reg-names = "ierb", "prb", "netcmix";
1883 #address-cells = <2>;
1884 #size-cells = <2>;
1886 power-domains = <&scmi_devpd IMX95_PD_NETC>;
1887 assigned-clocks = <&scmi_clk IMX95_CLK_ENET>,
1889 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD2>,
1891 assigned-clock-rates = <666666666>, <250000000>;
1893 clock-names = "ipg";
1896 netc_bus0: pcie@4ca00000 {
1897 compatible = "pci-host-ecam-generic";
1899 #address-cells = <3>;
1900 #size-cells = <2>;
1902 bus-range = <0x0 0x0>;
1903 msi-map = <0x0 &its 0x60 0x1>, //ENETC0 PF
1911 iommu-map = <0x0 &smmu 0x20 0x1>,
1919 /* ENETC0~2 and Timer BAR0 - non-prefetchable memory */
1921 /* Timer BAR2 - prefetchable memory */
1923 /* ENETC0~2: VF0-1 BAR0 - non-prefetchable memory */
1925 /* ENETC0~2: VF0-1 BAR2 - prefetchable memory */
1932 clock-names = "ref";
1940 clock-names = "ref";
1956 netc_bus1: pcie@4cb00000 {
1957 compatible = "pci-host-ecam-generic";
1959 #address-cells = <3>;
1960 #size-cells = <2>;
1962 bus-range = <0x1 0x1>;
1963 /* EMDIO BAR0 - non-prefetchable memory */
1965 /* EMDIO BAR2 - prefetchable memory */
1971 #address-cells = <1>;
1972 #size-cells = <0>;
1978 ddr-pmu@4e090dc0 {
1979 compatible = "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu";