Lines Matching +full:aips +full:- +full:bus
1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
6 #include <dt-bindings/dma/fsl-edma.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx95-clock.h"
13 #include "imx95-pinfunc.h"
14 #include "imx95-power.h"
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
23 #size-cells = <0>;
25 idle-states {
26 entry-method = "psci";
28 cpu_pd_wait: cpu-pd-wait {
29 compatible = "arm,idle-state";
30 arm,psci-suspend-param = <0x0010033>;
31 local-timer-stop;
32 entry-latency-us = <10000>;
33 exit-latency-us = <7000>;
34 min-residency-us = <27000>;
35 wakeup-latency-us = <15000>;
41 compatible = "arm,cortex-a55";
43 enable-method = "psci";
44 #cooling-cells = <2>;
45 cpu-idle-states = <&cpu_pd_wait>;
46 power-domains = <&scmi_perf IMX95_PERF_A55>;
47 power-domain-names = "perf";
48 i-cache-size = <32768>;
49 i-cache-line-size = <64>;
50 i-cache-sets = <128>;
51 d-cache-size = <32768>;
52 d-cache-line-size = <64>;
53 d-cache-sets = <128>;
54 next-level-cache = <&l2_cache_l0>;
59 compatible = "arm,cortex-a55";
61 enable-method = "psci";
62 #cooling-cells = <2>;
63 cpu-idle-states = <&cpu_pd_wait>;
64 power-domains = <&scmi_perf IMX95_PERF_A55>;
65 power-domain-names = "perf";
66 i-cache-size = <32768>;
67 i-cache-line-size = <64>;
68 i-cache-sets = <128>;
69 d-cache-size = <32768>;
70 d-cache-line-size = <64>;
71 d-cache-sets = <128>;
72 next-level-cache = <&l2_cache_l1>;
77 compatible = "arm,cortex-a55";
79 enable-method = "psci";
80 #cooling-cells = <2>;
81 cpu-idle-states = <&cpu_pd_wait>;
82 power-domains = <&scmi_perf IMX95_PERF_A55>;
83 power-domain-names = "perf";
84 i-cache-size = <32768>;
85 i-cache-line-size = <64>;
86 i-cache-sets = <128>;
87 d-cache-size = <32768>;
88 d-cache-line-size = <64>;
89 d-cache-sets = <128>;
90 next-level-cache = <&l2_cache_l2>;
95 compatible = "arm,cortex-a55";
97 enable-method = "psci";
98 #cooling-cells = <2>;
99 cpu-idle-states = <&cpu_pd_wait>;
100 power-domains = <&scmi_perf IMX95_PERF_A55>;
101 power-domain-names = "perf";
102 i-cache-size = <32768>;
103 i-cache-line-size = <64>;
104 i-cache-sets = <128>;
105 d-cache-size = <32768>;
106 d-cache-line-size = <64>;
107 d-cache-sets = <128>;
108 next-level-cache = <&l2_cache_l3>;
113 compatible = "arm,cortex-a55";
115 power-domains = <&scmi_perf IMX95_PERF_A55>;
116 power-domain-names = "perf";
117 enable-method = "psci";
118 #cooling-cells = <2>;
119 cpu-idle-states = <&cpu_pd_wait>;
120 i-cache-size = <32768>;
121 i-cache-line-size = <64>;
122 i-cache-sets = <128>;
123 d-cache-size = <32768>;
124 d-cache-line-size = <64>;
125 d-cache-sets = <128>;
126 next-level-cache = <&l2_cache_l4>;
131 compatible = "arm,cortex-a55";
133 power-domains = <&scmi_perf IMX95_PERF_A55>;
134 power-domain-names = "perf";
135 enable-method = "psci";
136 #cooling-cells = <2>;
137 cpu-idle-states = <&cpu_pd_wait>;
138 i-cache-size = <32768>;
139 i-cache-line-size = <64>;
140 i-cache-sets = <128>;
141 d-cache-size = <32768>;
142 d-cache-line-size = <64>;
143 d-cache-sets = <128>;
144 next-level-cache = <&l2_cache_l5>;
147 l2_cache_l0: l2-cache-l0 {
149 cache-size = <65536>;
150 cache-line-size = <64>;
151 cache-sets = <256>;
152 cache-level = <2>;
153 cache-unified;
154 next-level-cache = <&l3_cache>;
157 l2_cache_l1: l2-cache-l1 {
159 cache-size = <65536>;
160 cache-line-size = <64>;
161 cache-sets = <256>;
162 cache-level = <2>;
163 cache-unified;
164 next-level-cache = <&l3_cache>;
167 l2_cache_l2: l2-cache-l2 {
169 cache-size = <65536>;
170 cache-line-size = <64>;
171 cache-sets = <256>;
172 cache-level = <2>;
173 cache-unified;
174 next-level-cache = <&l3_cache>;
177 l2_cache_l3: l2-cache-l3 {
179 cache-size = <65536>;
180 cache-line-size = <64>;
181 cache-sets = <256>;
182 cache-level = <2>;
183 cache-unified;
184 next-level-cache = <&l3_cache>;
187 l2_cache_l4: l2-cache-l4 {
189 cache-size = <65536>;
190 cache-line-size = <64>;
191 cache-sets = <256>;
192 cache-level = <2>;
193 cache-unified;
194 next-level-cache = <&l3_cache>;
197 l2_cache_l5: l2-cache-l5 {
199 cache-size = <65536>;
200 cache-line-size = <64>;
201 cache-sets = <256>;
202 cache-level = <2>;
203 cache-unified;
204 next-level-cache = <&l3_cache>;
207 l3_cache: l3-cache {
209 cache-size = <524288>;
210 cache-line-size = <64>;
211 cache-sets = <512>;
212 cache-level = <3>;
213 cache-unified;
216 cpu-map {
245 dummy: clock-dummy {
246 compatible = "fixed-clock";
247 #clock-cells = <0>;
248 clock-frequency = <0>;
249 clock-output-names = "dummy";
252 clk_ext1: clock-ext1 {
253 compatible = "fixed-clock";
254 #clock-cells = <0>;
255 clock-frequency = <133000000>;
256 clock-output-names = "clk_ext1";
259 sai1_mclk: clock-sai-mclk1 {
260 compatible = "fixed-clock";
261 #clock-cells = <0>;
262 clock-frequency= <0>;
263 clock-output-names = "sai1_mclk";
266 sai2_mclk: clock-sai-mclk2 {
267 compatible = "fixed-clock";
268 #clock-cells = <0>;
269 clock-frequency= <0>;
270 clock-output-names = "sai2_mclk";
273 sai3_mclk: clock-sai-mclk3 {
274 compatible = "fixed-clock";
275 #clock-cells = <0>;
276 clock-frequency= <0>;
277 clock-output-names = "sai3_mclk";
280 sai4_mclk: clock-sai-mclk4 {
281 compatible = "fixed-clock";
282 #clock-cells = <0>;
283 clock-frequency= <0>;
284 clock-output-names = "sai4_mclk";
287 sai5_mclk: clock-sai-mclk5 {
288 compatible = "fixed-clock";
289 #clock-cells = <0>;
290 clock-frequency= <0>;
291 clock-output-names = "sai5_mclk";
294 osc_24m: clock-24m {
295 compatible = "fixed-clock";
296 #clock-cells = <0>;
297 clock-frequency = <24000000>;
298 clock-output-names = "osc_24m";
302 compatible = "mmio-sram";
305 #address-cells = <1>;
306 #size-cells = <1>;
314 #address-cells = <1>;
315 #size-cells = <0>;
316 arm,max-rx-timeout-ms = <5000>;
320 #power-domain-cells = <1>;
329 #power-domain-cells = <1>;
334 #clock-cells = <1>;
339 #thermal-sensor-cells = <1>;
357 compatible = "arm,cortex-a55-pmu";
361 thermal_zones: thermal-zones {
362 a55-thermal {
363 polling-delay-passive = <250>;
364 polling-delay = <2000>;
365 thermal-sensors = <&scmi_sensor 1>;
381 cooling-maps {
384 cooling-device =
395 ana-thermal {
396 polling-delay-passive = <250>;
397 polling-delay = <2000>;
398 thermal-sensors = <&scmi_sensor 0>;
413 cooling-maps {
416 cooling-device =
429 compatible = "arm,psci-1.0";
434 compatible = "arm,armv8-timer";
439 clock-frequency = <24000000>;
440 arm,no-tick-in-suspend;
441 interrupt-parent = <&gic>;
444 gic: interrupt-controller@48000000 {
445 compatible = "arm,gic-v3";
448 #address-cells = <2>;
449 #size-cells = <2>;
450 #interrupt-cells = <3>;
451 interrupt-controller;
453 interrupt-parent = <&gic>;
454 dma-noncoherent;
457 its: msi-controller@48040000 {
458 compatible = "arm,gic-v3-its";
460 msi-controller;
461 #msi-cells = <1>;
462 dma-noncoherent;
467 compatible = "simple-bus";
468 #address-cells = <2>;
469 #size-cells = <2>;
472 aips2: bus@42000000 {
473 compatible = "fsl,aips-bus", "simple-bus";
477 #address-cells = <1>;
478 #size-cells = <1>;
480 edma2: dma-controller@42000000 {
481 compatible = "fsl,imx95-edma5";
483 #dma-cells = <3>;
484 dma-channels = <64>;
550 clock-names = "dma";
553 edma3: dma-controller@42210000 {
554 compatible = "fsl,imx95-edma5";
556 #dma-cells = <3>;
557 dma-channels = <64>;
623 clock-names = "dma";
627 compatible = "fsl,imx95-mu";
631 #mbox-cells = <2>;
636 compatible = "fsl,imx93-wdt";
640 timeout-sec = <40>;
645 compatible = "fsl,imx7ulp-pwm";
648 #pwm-cells = <3>;
653 compatible = "fsl,imx7ulp-pwm";
656 #pwm-cells = <3>;
661 compatible = "fsl,imx7ulp-pwm";
664 #pwm-cells = <3>;
669 compatible = "fsl,imx7ulp-pwm";
672 #pwm-cells = <3>;
677 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
682 clock-names = "per", "ipg";
683 #address-cells = <1>;
684 #size-cells = <0>;
686 dma-names = "tx", "rx";
691 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
696 clock-names = "per", "ipg";
697 #address-cells = <1>;
698 #size-cells = <0>;
700 dma-names = "tx", "rx";
705 #address-cells = <1>;
706 #size-cells = <0>;
707 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
712 clock-names = "per", "ipg";
714 dma-names = "tx", "rx";
719 #address-cells = <1>;
720 #size-cells = <0>;
721 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
726 clock-names = "per", "ipg";
728 dma-names = "tx", "rx";
733 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
734 "fsl,imx7ulp-lpuart";
738 clock-names = "ipg";
740 dma-names = "rx", "tx";
745 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
746 "fsl,imx7ulp-lpuart";
750 clock-names = "ipg";
752 dma-names = "rx", "tx";
757 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
758 "fsl,imx7ulp-lpuart";
762 clock-names = "ipg";
764 dma-names = "rx", "tx";
769 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
770 "fsl,imx7ulp-lpuart";
774 clock-names = "ipg";
776 dma-names = "rx", "tx";
781 compatible = "fsl,imx95-flexcan";
786 clock-names = "ipg", "per";
787 assigned-clocks = <&scmi_clk IMX95_CLK_CAN2>;
788 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
789 assigned-clock-rates = <40000000>;
790 fsl,clk-source = /bits/ 8 <0>;
795 compatible = "fsl,imx95-flexcan";
800 clock-names = "ipg", "per";
801 assigned-clocks = <&scmi_clk IMX95_CLK_CAN3>;
802 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
803 assigned-clock-rates = <40000000>;
804 fsl,clk-source = /bits/ 8 <0>;
809 compatible = "nxp,imx8mm-fspi";
811 reg-names = "fspi_base", "fspi_mmap";
812 #address-cells = <1>;
813 #size-cells = <0>;
817 clock-names = "fspi_en", "fspi";
818 assigned-clocks = <&scmi_clk IMX95_CLK_FLEXSPI1>;
819 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>;
820 assigned-clock-rates = <200000000>;
825 compatible = "fsl,imx95-sai";
831 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
833 dma-names = "rx", "tx";
838 compatible = "fsl,imx95-sai";
844 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
846 dma-names = "rx", "tx";
851 compatible = "fsl,imx95-sai";
857 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
859 dma-names = "rx", "tx";
864 compatible = "fsl,imx95-xcvr";
867 reg-names = "ram", "regs", "rxfifo", "txfifo";
876 clock-names = "ipg", "phy", "spba", "pll_ipg";
878 dma-names = "rx", "tx";
883 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
884 "fsl,imx7ulp-lpuart";
888 clock-names = "ipg";
890 dma-names = "rx", "tx";
895 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
896 "fsl,imx7ulp-lpuart";
900 clock-names = "ipg";
902 dma-names = "rx", "tx";
907 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
912 clock-names = "per", "ipg";
913 #address-cells = <1>;
914 #size-cells = <0>;
916 dma-names = "tx", "rx";
921 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
926 clock-names = "per", "ipg";
927 #address-cells = <1>;
928 #size-cells = <0>;
930 dma-names = "tx", "rx";
935 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
940 clock-names = "per", "ipg";
941 #address-cells = <1>;
942 #size-cells = <0>;
944 dma-names = "tx", "rx";
949 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
954 clock-names = "per", "ipg";
955 #address-cells = <1>;
956 #size-cells = <0>;
958 dma-names = "tx", "rx";
963 #address-cells = <1>;
964 #size-cells = <0>;
965 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
970 clock-names = "per", "ipg";
972 dma-names = "tx", "rx";
977 #address-cells = <1>;
978 #size-cells = <0>;
979 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
984 clock-names = "per", "ipg";
986 dma-names = "tx", "rx";
991 #address-cells = <1>;
992 #size-cells = <0>;
993 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
998 clock-names = "per", "ipg";
1000 dma-names = "tx", "rx";
1005 #address-cells = <1>;
1006 #size-cells = <0>;
1007 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
1012 clock-names = "per", "ipg";
1014 dma-names = "tx", "rx";
1019 compatible = "fsl,imx95-mu";
1023 #mbox-cells = <2>;
1028 compatible = "fsl,imx95-flexcan";
1033 clock-names = "ipg", "per";
1034 assigned-clocks = <&scmi_clk IMX95_CLK_CAN4>;
1035 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
1036 assigned-clock-rates = <40000000>;
1037 fsl,clk-source = /bits/ 8 <0>;
1042 compatible = "fsl,imx95-flexcan";
1047 clock-names = "ipg", "per";
1048 assigned-clocks = <&scmi_clk IMX95_CLK_CAN5>;
1049 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
1050 assigned-clock-rates = <40000000>;
1051 fsl,clk-source = /bits/ 8 <0>;
1056 aips3: bus@42800000 {
1057 compatible = "fsl,aips-bus", "simple-bus";
1059 #address-cells = <1>;
1060 #size-cells = <1>;
1064 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc";
1070 clock-names = "ipg", "ahb", "per";
1071 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC1>;
1072 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>;
1073 assigned-clock-rates = <400000000>;
1074 bus-width = <8>;
1075 fsl,tuning-start-tap = <1>;
1076 fsl,tuning-step= <2>;
1081 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc";
1087 clock-names = "ipg", "ahb", "per";
1088 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC2>;
1089 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>;
1090 assigned-clock-rates = <400000000>;
1091 bus-width = <4>;
1092 fsl,tuning-start-tap = <1>;
1093 fsl,tuning-step= <2>;
1098 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc";
1104 clock-names = "ipg", "ahb", "per";
1105 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC3>;
1106 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>;
1107 assigned-clock-rates = <400000000>;
1108 bus-width = <4>;
1109 fsl,tuning-start-tap = <1>;
1110 fsl,tuning-step= <2>;
1116 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
1118 gpio-controller;
1119 #gpio-cells = <2>;
1122 interrupt-controller;
1123 #interrupt-cells = <2>;
1126 clock-names = "gpio", "port";
1127 gpio-ranges = <&scmi_iomuxc 0 4 32>;
1131 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
1133 gpio-controller;
1134 #gpio-cells = <2>;
1137 interrupt-controller;
1138 #interrupt-cells = <2>;
1141 clock-names = "gpio", "port";
1142 gpio-ranges = <&scmi_iomuxc 0 104 8>, <&scmi_iomuxc 8 74 18>,
1147 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
1149 gpio-controller;
1150 #gpio-cells = <2>;
1153 interrupt-controller;
1154 #interrupt-cells = <2>;
1157 clock-names = "gpio", "port";
1158 gpio-ranges = <&scmi_iomuxc 0 46 28>, <&scmi_iomuxc 28 44 2>;
1162 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
1164 gpio-controller;
1165 #gpio-cells = <2>;
1168 interrupt-controller;
1169 #interrupt-cells = <2>;
1172 clock-names = "gpio", "port";
1173 gpio-ranges = <&scmi_iomuxc 0 92 12>, <&scmi_iomuxc 12 36 6>;
1176 aips1: bus@44000000 {
1177 compatible = "fsl,aips-bus", "simple-bus";
1180 #address-cells = <1>;
1181 #size-cells = <1>;
1183 edma1: dma-controller@44000000 {
1184 compatible = "fsl,imx93-edma3";
1186 #dma-cells = <3>;
1187 dma-channels = <31>;
1220 clock-names = "dma";
1224 compatible = "fsl,imx95-mu";
1228 #mbox-cells = <2>;
1233 compatible = "fsl,imx7ulp-pwm";
1236 #pwm-cells = <3>;
1241 compatible = "fsl,imx7ulp-pwm";
1244 #pwm-cells = <3>;
1249 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
1254 clock-names = "per", "ipg";
1255 #address-cells = <1>;
1256 #size-cells = <0>;
1258 dma-names = "tx", "rx";
1263 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
1268 clock-names = "per", "ipg";
1269 #address-cells = <1>;
1270 #size-cells = <0>;
1272 dma-names = "tx", "rx";
1277 #address-cells = <1>;
1278 #size-cells = <0>;
1279 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
1284 clock-names = "per", "ipg";
1286 dma-names = "tx", "rx";
1291 #address-cells = <1>;
1292 #size-cells = <0>;
1293 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
1298 clock-names = "per", "ipg";
1300 dma-names = "tx", "rx";
1305 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
1306 "fsl,imx7ulp-lpuart";
1310 clock-names = "ipg";
1312 dma-names = "rx", "tx";
1317 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
1318 "fsl,imx7ulp-lpuart";
1322 clock-names = "ipg";
1324 dma-names = "rx", "tx";
1329 compatible = "fsl,imx95-flexcan";
1334 clock-names = "ipg", "per";
1335 assigned-clocks = <&scmi_clk IMX95_CLK_CAN1>;
1336 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
1337 assigned-clock-rates = <40000000>;
1338 fsl,clk-source = /bits/ 8 <0>;
1343 compatible = "fsl,imx95-sai";
1349 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1351 dma-names = "rx", "tx";
1356 compatible = "fsl,imx95-micfil", "fsl,imx93-micfil";
1367 clock-names = "ipg_clk", "ipg_clk_app",
1370 dma-names = "rx";
1375 compatible = "nxp,imx93-adc";
1381 clock-names = "ipg";
1386 compatible = "fsl,imx95-mu";
1390 #address-cells = <1>;
1391 #size-cells = <1>;
1392 #mbox-cells = <2>;
1395 compatible = "mmio-sram";
1398 #address-cells = <1>;
1399 #size-cells = <1>;
1401 scmi_buf0: scmi-sram-section@0 {
1402 compatible = "arm,scmi-shmem";
1406 scmi_buf1: scmi-sram-section@80 {
1407 compatible = "arm,scmi-shmem";
1415 compatible = "fsl,imx95-mu";
1419 #mbox-cells = <2>;
1424 compatible = "fsl,imx95-mu";
1428 #mbox-cells = <2>;
1433 compatible = "fsl,imx95-mu";
1437 #mbox-cells = <2>;
1443 compatible = "fsl,imx95-mu-v2x";
1446 #mbox-cells = <2>;
1450 compatible = "fsl,imx95-mu-v2x";
1453 #mbox-cells = <2>;
1458 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
1460 gpio-controller;
1461 #gpio-cells = <2>;
1464 interrupt-controller;
1465 #interrupt-cells = <2>;
1468 clock-names = "gpio", "port";
1469 gpio-ranges = <&scmi_iomuxc 0 112 16>;
1474 compatible = "fsl,imx95-mu-ele";
1477 #mbox-cells = <2>;
1482 compatible = "fsl,imx95-mu-ele";
1485 #mbox-cells = <2>;
1490 compatible = "fsl,imx95-mu-ele";
1493 #mbox-cells = <2>;
1498 compatible = "fsl,imx95-mu-ele";
1501 #mbox-cells = <2>;
1505 compatible = "fsl,imx95-mu-ele";
1508 #mbox-cells = <2>;
1513 compatible = "fsl,imx95-mu-ele";
1516 #mbox-cells = <2>;
1520 aips4: bus@49000000 {
1521 compatible = "fsl,aips-bus", "simple-bus";
1524 #address-cells = <1>;
1525 #size-cells = <1>;
1528 compatible = "arm,smmu-v3";
1534 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
1535 #iommu-cells = <1>;
1541 compatible = "fsl,imx95-pcie";
1546 reg-names = "dbi", "config", "atu", "app";
1549 #address-cells = <3>;
1550 #size-cells = <2>;
1552 linux,pci-domain = <0>;
1553 bus-range = <0x00 0xff>;
1554 num-lanes = <1>;
1555 num-viewport = <8>;
1557 interrupt-names = "msi";
1558 #interrupt-cells = <1>;
1559 interrupt-map-mask = <0 0 0 0x7>;
1560 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
1568 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
1569 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
1572 assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
1573 assigned-clock-parents = <0>, <0>,
1575 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
1576 fsl,max-link-speed = <3>;
1580 pcie0_ep: pcie-ep@4c300000 {
1581 compatible = "fsl,imx95-pcie-ep";
1588 reg-names = "dbi","atu", "dbi2", "app", "dma", "addr_space";
1589 num-lanes = <1>;
1591 interrupt-names = "dma";
1596 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
1597 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
1600 assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
1601 assigned-clock-parents = <0>, <0>,
1603 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
1608 compatible = "fsl,imx95-pcie";
1613 reg-names = "dbi", "config", "atu", "app";
1616 #address-cells = <3>;
1617 #size-cells = <2>;
1619 linux,pci-domain = <1>;
1620 bus-range = <0x00 0xff>;
1621 num-lanes = <1>;
1622 num-viewport = <8>;
1624 interrupt-names = "msi";
1625 #interrupt-cells = <1>;
1626 interrupt-map-mask = <0 0 0 0x7>;
1627 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1635 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
1636 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
1639 assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
1640 assigned-clock-parents = <0>, <0>,
1642 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
1643 fsl,max-link-speed = <3>;
1647 pcie1_ep: pcie-ep@4c380000 {
1648 compatible = "fsl,imx95-pcie-ep";
1655 reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space";
1656 num-lanes = <1>;
1658 interrupt-names = "dma";
1663 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
1664 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
1667 assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
1668 assigned-clock-parents = <0>, <0>,
1670 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
1675 compatible = "nxp,imx95-netcmix-blk-ctrl", "syscon";
1677 #clock-cells = <1>;
1679 assigned-clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>;
1680 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
1681 assigned-clock-rates = <133333333>;
1682 power-domains = <&scmi_devpd IMX95_PD_NETC>;
1687 compatible = "fsl,imx95-sai";
1693 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1694 power-domains = <&scmi_devpd IMX95_PD_NETC>;
1696 dma-names = "rx", "tx";
1700 ddr-pmu@4e090dc0 {
1701 compatible = "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu";