Lines Matching +full:0 +full:x445b1000
24 #size-cells = <0>;
31 arm,psci-suspend-param = <0x0010033>;
40 A55_0: cpu@0 {
43 reg = <0x0>;
61 reg = <0x100>;
79 reg = <0x200>;
97 reg = <0x300>;
115 reg = <0x400>;
133 reg = <0x500>;
248 #clock-cells = <0>;
249 clock-frequency = <0>;
255 #clock-cells = <0>;
262 #clock-cells = <0>;
263 clock-frequency= <0>;
269 #clock-cells = <0>;
270 clock-frequency= <0>;
276 #clock-cells = <0>;
277 clock-frequency= <0>;
283 #clock-cells = <0>;
284 clock-frequency= <0>;
290 #clock-cells = <0>;
291 clock-frequency= <0>;
297 #clock-cells = <0>;
304 #clock-cells = <0>;
311 reg = <0x0 0x204c0000 0x0 0x18000>;
312 ranges = <0x0 0x0 0x204c0000 0x18000>;
320 mboxes = <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>, <&mu2 5 1>;
323 #size-cells = <0>;
327 reg = <0x11>;
332 reg = <0x12>;
336 reg = <0x13>;
341 reg = <0x14>;
346 reg = <0x15>;
351 reg = <0x19>;
355 reg = <0x81>;
359 reg = <0x84>;
406 thermal-sensors = <&scmi_sensor 0>;
454 reg = <0 0x48000000 0 0x10000>,
455 <0 0x48060000 0 0xc0000>;
467 reg = <0 0x48040000 0 0x20000>;
478 #phy-cells = <0>;
489 reg = <0x0 0x42000000 0x0 0x800000>;
490 ranges = <0x42000000 0x0 0x42000000 0x8000000>,
491 <0x28000000 0x0 0x28000000 0x10000000>;
497 reg = <0x42000000 0x210000>;
570 reg = <0x42210000 0x210000>;
643 reg = <0x42430000 0x10000>;
652 reg = <0x42490000 0x10000>;
661 reg = <0x424e0000 0x1000>;
669 reg = <0x424f0000 0x1000>;
677 reg = <0x42500000 0x1000>;
685 reg = <0x42510000 0x1000>;
693 reg = <0x42520000 0x10000>;
696 #size-cells = <0>;
705 reg = <0x42530000 0x10000>;
711 #size-cells = <0>;
712 dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>;
719 reg = <0x42540000 0x10000>;
725 #size-cells = <0>;
726 dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>;
733 #size-cells = <0>;
735 reg = <0x42550000 0x10000>;
740 dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>;
747 #size-cells = <0>;
749 reg = <0x42560000 0x10000>;
754 dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>;
762 reg = <0x42570000 0x1000>;
766 dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>;
774 reg = <0x42580000 0x1000>;
778 dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>;
786 reg = <0x42590000 0x1000>;
790 dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>;
798 reg = <0x425a0000 0x1000>;
802 dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>;
809 reg = <0x425b0000 0x10000>;
817 fsl,clk-source = /bits/ 8 <0>;
823 reg = <0x42600000 0x10000>;
831 fsl,clk-source = /bits/ 8 <0>;
837 reg = <0x425e0000 0x10000>, <0x28000000 0x8000000>;
840 #size-cells = <0>;
853 reg = <0x42650000 0x10000>;
859 dmas = <&edma2 61 0 FSL_EDMA_RX>, <&edma2 60 0 0>;
866 reg = <0x42660000 0x10000>;
872 dmas = <&edma2 68 0 FSL_EDMA_RX>, <&edma2 67 0 0>;
879 reg = <0x42670000 0x10000>;
885 dmas = <&edma2 70 0 FSL_EDMA_RX>, <&edma2 69 0 0>;
892 reg = <0x42680000 0x800>, <0x42680800 0x400>,
893 <0x42680c00 0x080>, <0x42680e00 0x080>;
895 interrupts = /* XCVR IRQ 0 */
904 dmas = <&edma2 65 0 1>, <&edma2 66 0 0>;
912 reg = <0x42690000 0x1000>;
916 dmas = <&edma2 26 0 FSL_EDMA_RX>, <&edma2 25 0 0>;
924 reg = <0x426a0000 0x1000>;
928 dmas = <&edma2 28 0 FSL_EDMA_RX>, <&edma2 27 0 0>;
935 reg = <0x426b0000 0x10000>;
941 #size-cells = <0>;
942 dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>;
949 reg = <0x426c0000 0x10000>;
955 #size-cells = <0>;
956 dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>;
963 reg = <0x426d0000 0x10000>;
969 #size-cells = <0>;
970 dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>;
977 reg = <0x426e0000 0x10000>;
983 #size-cells = <0>;
984 dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>;
991 #size-cells = <0>;
993 reg = <0x426f0000 0x10000>;
998 dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>;
1005 #size-cells = <0>;
1007 reg = <0x42700000 0x10000>;
1012 dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>;
1019 #size-cells = <0>;
1021 reg = <0x42710000 0x10000>;
1026 dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>;
1033 #size-cells = <0>;
1035 reg = <0x42720000 0x10000>;
1040 dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>;
1047 reg = <0x42730000 0x10000>;
1056 reg = <0x427c0000 0x10000>;
1064 fsl,clk-source = /bits/ 8 <0>;
1070 reg = <0x427d0000 0x10000>;
1078 fsl,clk-source = /bits/ 8 <0>;
1085 reg = <0 0x42800000 0 0x800000>;
1088 ranges = <0x42800000 0x0 0x42800000 0x800000>;
1092 reg = <0x42850000 0x10000>;
1109 reg = <0x42860000 0x10000>;
1126 reg = <0x428b0000 0x10000>;
1144 reg = <0x0 0x43810000 0x0 0x1000>;
1154 gpio-ranges = <&scmi_iomuxc 0 4 32>;
1160 reg = <0x0 0x43820000 0x0 0x1000>;
1170 gpio-ranges = <&scmi_iomuxc 0 104 8>, <&scmi_iomuxc 8 74 18>,
1171 <&scmi_iomuxc 26 42 2>, <&scmi_iomuxc 28 0 4>;
1177 reg = <0x0 0x43840000 0x0 0x1000>;
1187 gpio-ranges = <&scmi_iomuxc 0 46 28>, <&scmi_iomuxc 28 44 2>;
1193 reg = <0x0 0x43850000 0x0 0x1000>;
1203 gpio-ranges = <&scmi_iomuxc 0 92 12>, <&scmi_iomuxc 12 36 6>;
1209 reg = <0x0 0x44000000 0x0 0x800000>;
1210 ranges = <0x44000000 0x0 0x44000000 0x800000>;
1216 reg = <0x44000000 0x200000>;
1256 reg = <0x44220000 0x10000>;
1265 reg = <0x44310000 0x1000>;
1273 reg = <0x44320000 0x1000>;
1281 reg = <0x44330000 0x10000>;
1284 #size-cells = <0>;
1293 reg = <0x44340000 0x10000>;
1299 #size-cells = <0>;
1300 dmas = <&edma1 12 0 0>, <&edma1 13 0 FSL_EDMA_RX> ;
1307 reg = <0x44350000 0x10000>;
1313 #size-cells = <0>;
1314 dmas = <&edma1 14 0 0>, <&edma1 15 0 FSL_EDMA_RX> ;
1321 #size-cells = <0>;
1323 reg = <0x44360000 0x10000>;
1328 dmas = <&edma1 16 0 FSL_EDMA_RX>, <&edma1 17 0 0> ;
1335 #size-cells = <0>;
1337 reg = <0x44370000 0x10000>;
1342 dmas = <&edma1 18 0 FSL_EDMA_RX>, <&edma1 19 0 0> ;
1350 reg = <0x44380000 0x1000>;
1354 dmas = <&edma1 21 0 FSL_EDMA_RX>, <&edma1 20 0 0>;
1362 reg = <0x44390000 0x1000>;
1366 dmas = <&edma1 23 0 FSL_EDMA_RX>, <&edma1 22 0 0>;
1373 reg = <0x443a0000 0x10000>;
1381 fsl,clk-source = /bits/ 8 <0>;
1387 reg = <0x443b0000 0x10000>;
1393 dmas = <&edma1 25 0 FSL_EDMA_RX>, <&edma1 24 0 0>;
1400 reg = <0x44520000 0x10000>;
1412 dmas = <&edma1 6 0 5>;
1419 reg = <0x44530000 0x10000>;
1431 reg = <0x445b0000 0x1000>;
1440 reg = <0x445b1000 0x400>;
1441 ranges = <0x0 0x445b1000 0x400>;
1445 scmi_buf0: scmi-sram-section@0 {
1447 reg = <0x0 0x80>;
1452 reg = <0x80 0x80>;
1460 reg = <0x445d0000 0x10000>;
1469 reg = <0x445f0000 0x10000>;
1478 reg = <0x44630000 0x10000>;
1488 reg = <0x0 0x47320000 0x0 0x10000>;
1495 reg = <0x0 0x47350000 0x0 0x10000>;
1503 reg = <0x0 0x47400000 0x0 0x1000>;
1513 gpio-ranges = <&scmi_iomuxc 0 112 16>;
1520 reg = <0x0 0x47520000 0x0 0x10000>;
1528 reg = <0x0 0x47530000 0x0 0x10000>;
1536 reg = <0x0 0x47540000 0x0 0x10000>;
1544 reg = <0x0 0x47550000 0x0 0x10000>;
1551 reg = <0x0 0x47560000 0x0 0x10000>;
1559 reg = <0x0 0x47570000 0x0 0x10000>;
1567 reg = <0x0 0x49000000 0x0 0x800000>;
1568 ranges = <0x49000000 0x0 0x49000000 0x800000>;
1574 reg = <0x490d0000 0x100000>;
1587 reg = <0x0 0x4c010010 0x0 0x04>,
1588 <0x0 0x4c1f0000 0x0 0x20>;
1597 dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
1602 reg = <0x0 0x4c100000 0x0 0x10000>;
1612 iommus = <&smmu 0xe>;
1618 reg = <0x0 0x4c0100c0 0x0 0x1>;
1626 reg = <0x0 0x4c1f0040 0x0 0x40>,
1627 <0x0 0x4c1fc000 0x0 0x100>;
1630 #phy-cells = <0>;
1637 reg = <0x0 0x4c200000 0x0 0x200>;
1643 iommus = <&smmu 0xf>;
1646 fsl,usbmisc = <&usbmisc 0>;
1653 reg = <0x0 0x4c200200 0x0 0x200>,
1654 <0x0 0x4c010014 0x0 0x04>;
1660 reg = <0 0x4c300000 0 0x10000>,
1661 <0 0x60100000 0 0xfe00000>,
1662 <0 0x4c360000 0 0x10000>,
1663 <0 0x4c340000 0 0x4000>;
1665 ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>,
1666 <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>;
1670 linux,pci-domain = <0>;
1671 bus-range = <0x00 0xff>;
1677 interrupt-map-mask = <0 0 0 0x7>;
1678 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
1679 <0 0 0 2 &gic 0 0 GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
1680 <0 0 0 3 &gic 0 0 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
1681 <0 0 0 4 &gic 0 0 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
1686 <&hsio_blk_ctl 0>;
1692 assigned-clock-parents = <0>, <0>,
1695 /* pcie0's Devid(BIT[7:6]) is 0x00, stream id(BIT[5:0]) is 0x10~0x17 */
1696 msi-map = <0x0 &its 0x10 0x1>,
1697 <0x100 &its 0x11 0x7>;
1698 iommu-map = <0x000 &smmu 0x10 0x1>,
1699 <0x100 &smmu 0x11 0x7>;
1700 iommu-map-mask = <0x1ff>;
1707 reg = <0 0x4c300000 0 0x10000>,
1708 <0 0x4c360000 0 0x1000>,
1709 <0 0x4c320000 0 0x1000>,
1710 <0 0x4c340000 0 0x4000>,
1711 <0 0x4c370000 0 0x10000>,
1712 <0x9 0 1 0>;
1726 assigned-clock-parents = <0>, <0>,
1734 reg = <0 0x4c380000 0 0x10000>,
1735 <8 0x80100000 0 0xfe00000>,
1736 <0 0x4c3e0000 0 0x10000>,
1737 <0 0x4c3c0000 0 0x4000>;
1739 ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>,
1740 <0x82000000 0 0x10000000 0xa 0x10000000 0 0x10000000>;
1745 bus-range = <0x00 0xff>;
1751 interrupt-map-mask = <0 0 0 0x7>;
1752 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1753 <0 0 0 2 &gic 0 0 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1754 <0 0 0 3 &gic 0 0 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1755 <0 0 0 4 &gic 0 0 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>;
1760 <&hsio_blk_ctl 0>;
1766 assigned-clock-parents = <0>, <0>,
1769 /* pcie1's Devid(BIT[7:6]) is 0x10, stream id(BIT[5:0]) is 0x18~0x1f */
1770 msi-map = <0x0 &its 0x98 0x1>,
1771 <0x100 &its 0x99 0x7>;
1772 msi-map-mask = <0x1ff>;
1774 iommu-map = <0x000 &smmu 0x18 0x1>,
1775 <0x100 &smmu 0x19 0x7>;
1776 iommu-map-mask = <0x1ff>;
1783 reg = <0 0x4c380000 0 0x10000>,
1784 <0 0x4c3e0000 0 0x1000>,
1785 <0 0x4c3a0000 0 0x1000>,
1786 <0 0x4c3c0000 0 0x4000>,
1787 <0 0x4c3f0000 0 0x10000>,
1788 <0xa 0 1 0>;
1802 assigned-clock-parents = <0>, <0>,
1810 reg = <0x0 0x4c410000 0x0 0x10000>;
1825 reg = <0x0 0x4C500000 0x0 0x00050000>;
1839 reg = <0x0 0x4C550000 0x0 0x00050000>;
1853 reg = <0x0 0x4c810000 0x0 0x8>;
1865 reg = <0x0 0x4c880000 0x0 0x10000>;
1872 dmas = <&edma2 59 0 FSL_EDMA_RX>, <&edma2 58 0 0>;
1879 reg = <0x0 0x4cde0000 0x0 0x10000>,
1880 <0x0 0x4cdf0000 0x0 0x10000>,
1881 <0x0 0x4c81000c 0x0 0x18>;
1898 reg = <0x0 0x4ca00000 0x0 0x100000>;
1902 bus-range = <0x0 0x0>;
1903 msi-map = <0x0 &its 0x60 0x1>, //ENETC0 PF
1904 <0x10 &its 0x61 0x1>, //ENETC0 VF0
1905 <0x20 &its 0x62 0x1>, //ENETC0 VF1
1906 <0x40 &its 0x63 0x1>, //ENETC1 PF
1907 <0x80 &its 0x64 0x1>, //ENETC2 PF
1908 <0x90 &its 0x65 0x1>, //ENETC2 VF0
1909 <0xa0 &its 0x66 0x1>, //ENETC2 VF1
1910 <0xc0 &its 0x67 0x1>; //NETC Timer
1911 iommu-map = <0x0 &smmu 0x20 0x1>,
1912 <0x10 &smmu 0x21 0x1>,
1913 <0x20 &smmu 0x22 0x1>,
1914 <0x40 &smmu 0x23 0x1>,
1915 <0x80 &smmu 0x24 0x1>,
1916 <0x90 &smmu 0x25 0x1>,
1917 <0xa0 &smmu 0x26 0x1>,
1918 <0xc0 &smmu 0x27 0x1>;
1920 ranges = <0x82000000 0x0 0x4cc00000 0x0 0x4cc00000 0x0 0xe0000
1922 0xc2000000 0x0 0x4cd00000 0x0 0x4cd00000 0x0 0x10000
1924 0x82000000 0x0 0x4cd20000 0x0 0x4cd20000 0x0 0x60000
1926 0xc2000000 0x0 0x4cd80000 0x0 0x4cd80000 0x0 0x60000>;
1928 enetc_port0: ethernet@0,0 {
1930 reg = <0x000000 0 0 0 0>;
1936 enetc_port1: ethernet@8,0 {
1938 reg = <0x004000 0 0 0 0>;
1944 enetc_port2: ethernet@10,0 {
1946 reg = <0x008000 0 0 0 0>;
1950 netc_timer: ethernet@18,0 {
1951 reg = <0x00c000 0 0 0 0>;
1958 reg = <0x0 0x4cb00000 0x0 0x100000>;
1962 bus-range = <0x1 0x1>;
1964 ranges = <0x82000000 0x0 0x4cce0000 0x0 0x4cce0000 0x0 0x20000
1966 0xc2000000 0x0 0x4cd10000 0x0 0x4cd10000 0x0 0x10000>;
1968 netc_emdio: mdio@0,0 {
1970 reg = <0x010000 0 0 0 0>;
1972 #size-cells = <0>;
1980 reg = <0x0 0x4e090dc0 0x0 0x200>;