Lines Matching +full:0 +full:x44000000
23 #size-cells = <0>;
25 A55_0: cpu@0 {
28 reg = <0x0>;
45 reg = <0x100>;
62 reg = <0x200>;
79 reg = <0x300>;
96 reg = <0x400>;
113 reg = <0x500>;
227 #clock-cells = <0>;
228 clock-frequency = <0>;
234 #clock-cells = <0>;
241 #clock-cells = <0>;
242 clock-frequency= <0>;
248 #clock-cells = <0>;
249 clock-frequency= <0>;
255 #clock-cells = <0>;
256 clock-frequency= <0>;
262 #clock-cells = <0>;
263 clock-frequency= <0>;
269 #clock-cells = <0>;
270 clock-frequency= <0>;
276 #clock-cells = <0>;
283 reg = <0x0 0x204c0000 0x0 0x18000>;
284 ranges = <0x0 0x0 0x204c0000 0x18000>;
292 mboxes = <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>, <&mu2 5 1>;
295 #size-cells = <0>;
298 reg = <0x11>;
303 reg = <0x13>;
308 reg = <0x14>;
313 reg = <0x15>;
318 reg = <0x19>;
382 reg = <0 0x48000000 0 0x10000>,
383 <0 0x48060000 0 0xc0000>;
395 reg = <0 0x48040000 0 0x20000>;
410 reg = <0x0 0x42000000 0x0 0x800000>;
411 ranges = <0x42000000 0x0 0x42000000 0x8000000>,
412 <0x28000000 0x0 0x28000000 0x10000000>;
418 reg = <0x42000000 0x210000>;
491 reg = <0x42210000 0x210000>;
564 reg = <0x42430000 0x10000>;
573 reg = <0x42490000 0x10000>;
582 reg = <0x424e0000 0x1000>;
590 reg = <0x424f0000 0x1000>;
598 reg = <0x42500000 0x1000>;
606 reg = <0x42510000 0x1000>;
614 reg = <0x42530000 0x10000>;
620 #size-cells = <0>;
621 dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>;
628 reg = <0x42540000 0x10000>;
634 #size-cells = <0>;
635 dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>;
642 #size-cells = <0>;
644 reg = <0x42550000 0x10000>;
649 dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>;
656 #size-cells = <0>;
658 reg = <0x42560000 0x10000>;
663 dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>;
671 reg = <0x42570000 0x1000>;
675 dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>;
683 reg = <0x42580000 0x1000>;
687 dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>;
695 reg = <0x42590000 0x1000>;
699 dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>;
707 reg = <0x425a0000 0x1000>;
711 dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>;
718 reg = <0x425b0000 0x10000>;
726 fsl,clk-source = /bits/ 8 <0>;
732 reg = <0x42600000 0x10000>;
740 fsl,clk-source = /bits/ 8 <0>;
746 reg = <0x425e0000 0x10000>, <0x28000000 0x8000000>;
749 #size-cells = <0>;
762 reg = <0x42650000 0x10000>;
768 dmas = <&edma2 61 0 FSL_EDMA_RX>, <&edma2 60 0 0>;
775 reg = <0x42660000 0x10000>;
781 dmas = <&edma2 68 0 FSL_EDMA_RX>, <&edma2 67 0 0>;
788 reg = <0x42670000 0x10000>;
794 dmas = <&edma2 70 0 FSL_EDMA_RX>, <&edma2 69 0 0>;
801 reg = <0x42680000 0x800>, <0x42680800 0x400>,
802 <0x42680c00 0x080>, <0x42680e00 0x080>;
804 interrupts = /* XCVR IRQ 0 */
813 dmas = <&edma2 65 0 1>, <&edma2 66 0 0>;
821 reg = <0x42690000 0x1000>;
825 dmas = <&edma2 26 0 FSL_EDMA_RX>, <&edma2 25 0 0>;
833 reg = <0x426a0000 0x1000>;
837 dmas = <&edma2 28 0 FSL_EDMA_RX>, <&edma2 27 0 0>;
844 reg = <0x426b0000 0x10000>;
850 #size-cells = <0>;
851 dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>;
858 reg = <0x426c0000 0x10000>;
864 #size-cells = <0>;
865 dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>;
872 reg = <0x426d0000 0x10000>;
878 #size-cells = <0>;
879 dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>;
886 reg = <0x426e0000 0x10000>;
892 #size-cells = <0>;
893 dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>;
900 #size-cells = <0>;
902 reg = <0x426f0000 0x10000>;
907 dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>;
914 #size-cells = <0>;
916 reg = <0x42700000 0x10000>;
921 dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>;
928 #size-cells = <0>;
930 reg = <0x42710000 0x10000>;
935 dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>;
942 #size-cells = <0>;
944 reg = <0x42720000 0x10000>;
949 dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>;
956 reg = <0x42730000 0x10000>;
965 reg = <0x427c0000 0x10000>;
973 fsl,clk-source = /bits/ 8 <0>;
979 reg = <0x427d0000 0x10000>;
987 fsl,clk-source = /bits/ 8 <0>;
994 reg = <0 0x42800000 0 0x800000>;
997 ranges = <0x42800000 0x0 0x42800000 0x800000>;
1001 reg = <0x42850000 0x10000>;
1018 reg = <0x42860000 0x10000>;
1035 reg = <0x428b0000 0x10000>;
1053 reg = <0x0 0x43810000 0x0 0x1000>;
1063 gpio-ranges = <&scmi_iomuxc 0 4 32>;
1068 reg = <0x0 0x43820000 0x0 0x1000>;
1078 gpio-ranges = <&scmi_iomuxc 0 104 8>, <&scmi_iomuxc 8 74 18>,
1079 <&scmi_iomuxc 26 42 2>, <&scmi_iomuxc 28 0 4>;
1084 reg = <0x0 0x43840000 0x0 0x1000>;
1094 gpio-ranges = <&scmi_iomuxc 0 46 28>, <&scmi_iomuxc 28 44 2>;
1099 reg = <0x0 0x43850000 0x0 0x1000>;
1109 gpio-ranges = <&scmi_iomuxc 0 92 12>, <&scmi_iomuxc 12 36 6>;
1114 reg = <0x0 0x44000000 0x0 0x800000>;
1115 ranges = <0x44000000 0x0 0x44000000 0x800000>;
1121 reg = <0x44000000 0x200000>;
1161 reg = <0x44220000 0x10000>;
1170 reg = <0x44310000 0x1000>;
1178 reg = <0x44320000 0x1000>;
1186 reg = <0x44340000 0x10000>;
1192 #size-cells = <0>;
1193 dmas = <&edma1 12 0 0>, <&edma1 13 0 FSL_EDMA_RX> ;
1200 reg = <0x44350000 0x10000>;
1206 #size-cells = <0>;
1207 dmas = <&edma1 14 0 0>, <&edma1 15 0 FSL_EDMA_RX> ;
1214 #size-cells = <0>;
1216 reg = <0x44360000 0x10000>;
1221 dmas = <&edma1 16 0 FSL_EDMA_RX>, <&edma1 17 0 0> ;
1228 #size-cells = <0>;
1230 reg = <0x44370000 0x10000>;
1235 dmas = <&edma1 18 0 FSL_EDMA_RX>, <&edma1 19 0 0> ;
1243 reg = <0x44380000 0x1000>;
1247 dmas = <&edma1 21 0 FSL_EDMA_RX>, <&edma1 20 0 0>;
1255 reg = <0x44390000 0x1000>;
1259 dmas = <&edma1 23 0 FSL_EDMA_RX>, <&edma1 22 0 0>;
1266 reg = <0x443a0000 0x10000>;
1274 fsl,clk-source = /bits/ 8 <0>;
1280 reg = <0x443b0000 0x10000>;
1286 dmas = <&edma1 25 0 FSL_EDMA_RX>, <&edma1 24 0 0>;
1293 reg = <0x44520000 0x10000>;
1305 dmas = <&edma1 6 0 5>;
1312 reg = <0x44530000 0x10000>;
1323 reg = <0x445b0000 0x1000>;
1332 reg = <0x445b1000 0x400>;
1333 ranges = <0x0 0x445b1000 0x400>;
1337 scmi_buf0: scmi-sram-section@0 {
1339 reg = <0x0 0x80>;
1344 reg = <0x80 0x80>;
1352 reg = <0x445d0000 0x10000>;
1361 reg = <0x445f0000 0x10000>;
1370 reg = <0x44630000 0x10000>;
1380 reg = <0x0 0x47320000 0x0 0x10000>;
1387 reg = <0x0 0x47350000 0x0 0x10000>;
1395 reg = <0x0 0x47400000 0x0 0x1000>;
1405 gpio-ranges = <&scmi_iomuxc 0 112 16>;
1411 reg = <0x0 0x47520000 0x0 0x10000>;
1419 reg = <0x0 0x47530000 0x0 0x10000>;
1427 reg = <0x0 0x47540000 0x0 0x10000>;
1435 reg = <0x0 0x47550000 0x0 0x10000>;
1442 reg = <0x0 0x47560000 0x0 0x10000>;
1450 reg = <0x0 0x47570000 0x0 0x10000>;
1458 reg = <0x0 0x49000000 0x0 0x800000>;
1459 ranges = <0x49000000 0x0 0x49000000 0x800000>;
1465 reg = <0x490d0000 0x100000>;
1478 reg = <0 0x4c300000 0 0x10000>,
1479 <0 0x60100000 0 0xfe00000>,
1480 <0 0x4c360000 0 0x10000>,
1481 <0 0x4c340000 0 0x2000>;
1483 ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>,
1484 <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>;
1488 linux,pci-domain = <0>;
1489 bus-range = <0x00 0xff>;
1495 interrupt-map-mask = <0 0 0 0x7>;
1496 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
1497 <0 0 0 2 &gic 0 0 GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
1498 <0 0 0 3 &gic 0 0 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
1499 <0 0 0 4 &gic 0 0 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
1509 assigned-clock-parents = <0>, <0>,
1518 reg = <0 0x4c300000 0 0x10000>,
1519 <0 0x4c360000 0 0x1000>,
1520 <0 0x4c320000 0 0x1000>,
1521 <0 0x4c340000 0 0x2000>,
1522 <0 0x4c370000 0 0x10000>,
1523 <0x9 0 1 0>;
1537 assigned-clock-parents = <0>, <0>,
1545 reg = <0 0x4c380000 0 0x10000>,
1546 <8 0x80100000 0 0xfe00000>,
1547 <0 0x4c3e0000 0 0x10000>,
1548 <0 0x4c3c0000 0 0x2000>;
1550 ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>,
1551 <0x82000000 0 0x10000000 0xa 0x10000000 0 0x10000000>;
1556 bus-range = <0x00 0xff>;
1562 interrupt-map-mask = <0 0 0 0x7>;
1563 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1564 <0 0 0 2 &gic 0 0 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1565 <0 0 0 3 &gic 0 0 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1566 <0 0 0 4 &gic 0 0 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>;
1576 assigned-clock-parents = <0>, <0>,
1585 reg = <0 0x4c380000 0 0x10000>,
1586 <0 0x4c3e0000 0 0x1000>,
1587 <0 0x4c3a0000 0 0x1000>,
1588 <0 0x4c3c0000 0 0x2000>,
1589 <0 0x4c3f0000 0 0x10000>,
1590 <0xa 0 1 0>;
1604 assigned-clock-parents = <0>, <0>,
1612 reg = <0x0 0x4c810000 0x0 0x10000>;
1624 reg = <0x0 0x4c880000 0x0 0x10000>;
1631 dmas = <&edma2 59 0 FSL_EDMA_RX>, <&edma2 58 0 0>;
1638 reg = <0x0 0x4e090dc0 0x0 0x200>;