Lines Matching +full:fixed +full:- +full:burst
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8ulp-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/power/imx8ulp-power.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx8ulp-pinfunc.h"
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
34 #address-cells = <2>;
35 #size-cells = <0>;
39 compatible = "arm,cortex-a35";
41 enable-method = "psci";
42 next-level-cache = <&A35_L2>;
43 cpu-idle-states = <&cpu_sleep>;
48 compatible = "arm,cortex-a35";
50 enable-method = "psci";
51 next-level-cache = <&A35_L2>;
52 cpu-idle-states = <&cpu_sleep>;
55 A35_L2: l2-cache0 {
57 cache-level = <2>;
58 cache-unified;
61 idle-states {
62 entry-method = "psci";
64 cpu_sleep: cpu-sleep {
65 compatible = "arm,idle-state";
66 arm,psci-suspend-param = <0x0>;
67 local-timer-stop;
68 entry-latency-us = <1000>;
69 exit-latency-us = <700>;
70 min-residency-us = <2700>;
75 gic: interrupt-controller@2d400000 {
76 compatible = "arm,gic-v3";
79 #interrupt-cells = <3>;
80 interrupt-controller;
85 compatible = "arm,cortex-a35-pmu";
86 interrupt-parent = <&gic>;
89 interrupt-affinity = <&A35_0>, <&A35_1>;
93 compatible = "arm,psci-1.0";
97 thermal-zones {
98 cpu-thermal {
99 polling-delay-passive = <250>;
100 polling-delay = <2000>;
101 thermal-sensors = <&scmi_sensor 0>;
120 compatible = "arm,armv8-timer";
122 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
127 frosc: clock-frosc {
128 compatible = "fixed-clock";
129 clock-frequency = <192000000>;
130 clock-output-names = "frosc";
131 #clock-cells = <0>;
134 lposc: clock-lposc {
135 compatible = "fixed-clock";
136 clock-frequency = <1000000>;
137 clock-output-names = "lposc";
138 #clock-cells = <0>;
141 rosc: clock-rosc {
142 compatible = "fixed-clock";
143 clock-frequency = <32768>;
144 clock-output-names = "rosc";
145 #clock-cells = <0>;
148 sosc: clock-sosc {
149 compatible = "fixed-clock";
150 clock-frequency = <24000000>;
151 clock-output-names = "sosc";
152 #clock-cells = <0>;
156 compatible = "mmio-sram";
159 #address-cells = <1>;
160 #size-cells = <1>;
163 scmi_buf: scmi-sram-section@0 {
164 compatible = "arm,scmi-shmem";
171 compatible = "arm,scmi-smc";
172 arm,smc-id = <0xc20000fe>;
173 #address-cells = <1>;
174 #size-cells = <0>;
179 #power-domain-cells = <1>;
184 #thermal-sensor-cells = <1>;
189 cm33: remoteproc-cm33 {
190 compatible = "fsl,imx8ulp-cm33";
195 compatible = "simple-bus";
196 #address-cells = <1>;
197 #size-cells = <1>;
202 compatible = "fsl,imx8ulp-mu-s4";
205 #mbox-cells = <2>;
209 compatible = "simple-bus";
211 #address-cells = <1>;
212 #size-cells = <1>;
216 compatible = "fsl,imx8ulp-mu";
219 #mbox-cells = <2>;
224 compatible = "fsl,imx8ulp-mu";
228 #mbox-cells = <2>;
233 compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt";
237 assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
238 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
239 timeout-sec = <40>;
242 cgc1: clock-controller@292c0000 {
243 compatible = "fsl,imx8ulp-cgc1";
245 #clock-cells = <1>;
248 pcc3: clock-controller@292d0000 {
249 compatible = "fsl,imx8ulp-pcc3";
251 #clock-cells = <1>;
252 #reset-cells = <1>;
256 compatible = "fsl,sec-v4.0";
259 #address-cells = <1>;
260 #size-cells = <1>;
263 compatible = "fsl,sec-v4.0-job-ring";
269 compatible = "fsl,sec-v4.0-job-ring";
275 compatible = "fsl,sec-v4.0-job-ring";
281 compatible = "fsl,sec-v4.0-job-ring";
288 compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm";
293 clock-names = "ipg", "per";
298 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
303 clock-names = "per", "ipg";
304 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
305 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
306 assigned-clock-rates = <48000000>;
311 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
316 clock-names = "per", "ipg";
317 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
318 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
319 assigned-clock-rates = <48000000>;
324 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
328 clock-names = "ipg";
333 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
337 clock-names = "ipg";
342 #address-cells = <1>;
343 #size-cells = <0>;
344 compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
349 clock-names = "per", "ipg";
350 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
351 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
352 assigned-clock-rates = <48000000>;
357 #address-cells = <1>;
358 #size-cells = <0>;
359 compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
364 clock-names = "per", "ipg";
365 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>;
366 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
367 assigned-clock-rates = <48000000>;
373 compatible = "simple-bus";
375 #address-cells = <1>;
376 #size-cells = <1>;
379 pcc4: clock-controller@29800000 {
380 compatible = "fsl,imx8ulp-pcc4";
382 #clock-cells = <1>;
383 #reset-cells = <1>;
387 compatible = "nxp,imx8mm-fspi";
389 reg-names = "fspi_base", "fspi_mmap";
390 #address-cells = <1>;
391 #size-cells = <0>;
395 clock-names = "fspi_en", "fspi";
396 assigned-clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>;
397 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>;
402 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
407 clock-names = "per", "ipg";
408 assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>;
409 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
410 assigned-clock-rates = <48000000>;
415 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
420 clock-names = "per", "ipg";
421 assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>;
422 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
423 assigned-clock-rates = <48000000>;
428 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
432 clock-names = "ipg";
437 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
441 clock-names = "ipg";
446 compatible = "fsl,imx8ulp-iomuxc1";
451 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
457 clock-names = "ipg", "ahb", "per";
458 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>;
459 assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>,
461 assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>;
462 assigned-clock-rates = <389283840>, <389283840>;
463 fsl,tuning-start-tap = <20>;
464 fsl,tuning-step = <2>;
465 bus-width = <4>;
470 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
476 clock-names = "ipg", "ahb", "per";
477 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>;
478 assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>,
480 assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>;
481 assigned-clock-rates = <194641920>, <194641920>;
482 fsl,tuning-start-tap = <20>;
483 fsl,tuning-step = <2>;
484 bus-width = <4>;
489 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
495 clock-names = "ipg", "ahb", "per";
496 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
497 assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>,
499 assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>;
500 assigned-clock-rates = <194641920>, <194641920>;
501 fsl,tuning-start-tap = <20>;
502 fsl,tuning-step = <2>;
503 bus-width = <4>;
508 compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
512 power-domains = <&scmi_devpd IMX8ULP_PD_USB0>;
515 ahb-burst-config = <0x0>;
516 tx-burst-size-dword = <0x8>;
517 rx-burst-size-dword = <0x8>;
522 compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7d-usbmisc",
523 "fsl,imx6q-usbmisc";
525 #index-cells = <1>;
529 usbphy1: usb-phy@29910000 {
530 compatible = "fsl,imx8ulp-usbphy", "fsl,imx7ulp-usbphy";
534 #phy-cells = <0>;
539 compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
543 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
546 ahb-burst-config = <0x0>;
547 tx-burst-size-dword = <0x8>;
548 rx-burst-size-dword = <0x8>;
553 compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7d-usbmisc",
554 "fsl,imx6q-usbmisc";
556 #index-cells = <1>;
560 usbphy2: usb-phy@29930000 {
561 compatible = "fsl,imx8ulp-usbphy", "fsl,imx7ulp-usbphy";
565 #phy-cells = <0>;
570 compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec";
573 interrupt-names = "int0";
574 fsl,num-tx-queues = <1>;
575 fsl,num-rx-queues = <1>;
581 compatible = "fsl,imx8ulp-gpio";
583 gpio-controller;
584 #gpio-cells = <2>;
587 interrupt-controller;
588 #interrupt-cells = <2>;
591 clock-names = "gpio", "port";
592 gpio-ranges = <&iomuxc1 0 32 24>;
596 compatible = "fsl,imx8ulp-gpio";
598 gpio-controller;
599 #gpio-cells = <2>;
602 interrupt-controller;
603 #interrupt-cells = <2>;
606 clock-names = "gpio", "port";
607 gpio-ranges = <&iomuxc1 0 64 32>;
611 compatible = "simple-bus";
613 #address-cells = <1>;
614 #size-cells = <1>;
617 cgc2: clock-controller@2da60000 {
618 compatible = "fsl,imx8ulp-cgc2";
620 #clock-cells = <1>;
623 pcc5: clock-controller@2da70000 {
624 compatible = "fsl,imx8ulp-pcc5";
626 #clock-cells = <1>;
627 #reset-cells = <1>;
632 compatible = "fsl,imx8ulp-gpio";
634 gpio-controller;
635 #gpio-cells = <2>;
638 interrupt-controller;
639 #interrupt-cells = <2>;
642 clock-names = "gpio", "port";
643 gpio-ranges = <&iomuxc1 0 0 24>;