Lines Matching +full:ns +full:- +full:thermal
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/pads-imx8qm.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
31 vpu-core0 = &vpu_core0;
32 vpu-core1 = &vpu_core1;
33 vpu-core2 = &vpu_core2;
37 #address-cells = <2>;
38 #size-cells = <0>;
40 cpu-map {
68 compatible = "arm,cortex-a53";
71 enable-method = "psci";
72 i-cache-size = <0x8000>;
73 i-cache-line-size = <64>;
74 i-cache-sets = <256>;
75 d-cache-size = <0x8000>;
76 d-cache-line-size = <64>;
77 d-cache-sets = <128>;
78 next-level-cache = <&A53_L2>;
79 operating-points-v2 = <&a53_opp_table>;
80 #cooling-cells = <2>;
85 compatible = "arm,cortex-a53";
88 enable-method = "psci";
89 i-cache-size = <0x8000>;
90 i-cache-line-size = <64>;
91 i-cache-sets = <256>;
92 d-cache-size = <0x8000>;
93 d-cache-line-size = <64>;
94 d-cache-sets = <128>;
95 next-level-cache = <&A53_L2>;
96 operating-points-v2 = <&a53_opp_table>;
97 #cooling-cells = <2>;
102 compatible = "arm,cortex-a53";
105 enable-method = "psci";
106 i-cache-size = <0x8000>;
107 i-cache-line-size = <64>;
108 i-cache-sets = <256>;
109 d-cache-size = <0x8000>;
110 d-cache-line-size = <64>;
111 d-cache-sets = <128>;
112 next-level-cache = <&A53_L2>;
113 operating-points-v2 = <&a53_opp_table>;
114 #cooling-cells = <2>;
119 compatible = "arm,cortex-a53";
122 enable-method = "psci";
123 i-cache-size = <0x8000>;
124 i-cache-line-size = <64>;
125 i-cache-sets = <256>;
126 d-cache-size = <0x8000>;
127 d-cache-line-size = <64>;
128 d-cache-sets = <128>;
129 next-level-cache = <&A53_L2>;
130 operating-points-v2 = <&a53_opp_table>;
131 #cooling-cells = <2>;
136 compatible = "arm,cortex-a72";
139 enable-method = "psci";
140 i-cache-size = <0xC000>;
141 i-cache-line-size = <64>;
142 i-cache-sets = <256>;
143 d-cache-size = <0x8000>;
144 d-cache-line-size = <64>;
145 d-cache-sets = <256>;
146 next-level-cache = <&A72_L2>;
147 operating-points-v2 = <&a72_opp_table>;
148 #cooling-cells = <2>;
153 compatible = "arm,cortex-a72";
156 enable-method = "psci";
157 next-level-cache = <&A72_L2>;
158 operating-points-v2 = <&a72_opp_table>;
159 #cooling-cells = <2>;
162 A53_L2: l2-cache0 {
164 cache-level = <2>;
165 cache-unified;
166 cache-size = <0x100000>;
167 cache-line-size = <64>;
168 cache-sets = <1024>;
171 A72_L2: l2-cache1 {
173 cache-level = <2>;
174 cache-unified;
175 cache-size = <0x100000>;
176 cache-line-size = <64>;
177 cache-sets = <1024>;
181 a53_opp_table: opp-table-0 {
182 compatible = "operating-points-v2";
183 opp-shared;
185 opp-600000000 {
186 opp-hz = /bits/ 64 <600000000>;
187 opp-microvolt = <900000>;
188 clock-latency-ns = <150000>;
191 opp-896000000 {
192 opp-hz = /bits/ 64 <896000000>;
193 opp-microvolt = <1000000>;
194 clock-latency-ns = <150000>;
197 opp-1104000000 {
198 opp-hz = /bits/ 64 <1104000000>;
199 opp-microvolt = <1100000>;
200 clock-latency-ns = <150000>;
203 opp-1200000000 {
204 opp-hz = /bits/ 64 <1200000000>;
205 opp-microvolt = <1100000>;
206 clock-latency-ns = <150000>;
207 opp-suspend;
211 a72_opp_table: opp-table-1 {
212 compatible = "operating-points-v2";
213 opp-shared;
215 opp-600000000 {
216 opp-hz = /bits/ 64 <600000000>;
217 opp-microvolt = <1000000>;
218 clock-latency-ns = <150000>;
221 opp-1056000000 {
222 opp-hz = /bits/ 64 <1056000000>;
223 opp-microvolt = <1000000>;
224 clock-latency-ns = <150000>;
227 opp-1296000000 {
228 opp-hz = /bits/ 64 <1296000000>;
229 opp-microvolt = <1100000>;
230 clock-latency-ns = <150000>;
233 opp-1596000000 {
234 opp-hz = /bits/ 64 <1596000000>;
235 opp-microvolt = <1100000>;
236 clock-latency-ns = <150000>;
237 opp-suspend;
241 gic: interrupt-controller@51a00000 {
242 compatible = "arm,gic-v3";
248 #interrupt-cells = <3>;
249 interrupt-controller;
251 interrupt-parent = <&gic>;
255 compatible = "arm,armv8-pmuv3";
260 compatible = "arm,psci-1.0";
265 compatible = "arm,armv8-timer";
267 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
273 compatible = "arm,mmu-500";
274 interrupt-parent = <&gic>;
276 #global-interrupts = <1>;
277 #iommu-cells = <2>;
313 system-controller {
314 compatible = "fsl,imx-scu";
315 mbox-names = "tx0",
322 pd: power-controller {
323 compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";
324 #power-domain-cells = <1>;
327 clk: clock-controller {
328 compatible = "fsl,imx8qm-clk", "fsl,scu-clk";
329 #clock-cells = <2>;
333 compatible = "fsl,imx8qm-iomuxc";
337 compatible = "fsl,imx8qxp-sc-rtc";
341 compatible = "fsl,imx8qm-scu-ocotp";
342 #address-cells = <1>;
343 #size-cells = <1>;
344 read-only;
355 tsens: thermal-sensor {
356 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
357 #thermal-sensor-cells = <1>;
361 thermal-zones {
362 cpu0-thermal {
363 polling-delay-passive = <250>;
364 polling-delay = <2000>;
365 thermal-sensors = <&tsens IMX_SC_R_A53>;
381 cooling-maps {
384 cooling-device =
393 cpu1-thermal {
394 polling-delay-passive = <250>;
395 polling-delay = <2000>;
396 thermal-sensors = <&tsens IMX_SC_R_A72>;
412 cooling-maps {
415 cooling-device =
422 gpu0-thermal {
423 polling-delay-passive = <250>;
424 polling-delay = <2000>;
425 thermal-sensors = <&tsens IMX_SC_R_GPU_0_PID0>;
442 gpu1-thermal {
443 polling-delay-passive = <250>;
444 polling-delay = <2000>;
445 thermal-sensors = <&tsens IMX_SC_R_GPU_1_PID0>;
462 drc0-thermal {
463 polling-delay-passive = <250>;
464 polling-delay = <2000>;
465 thermal-sensors = <&tsens IMX_SC_R_DRC_0>;
483 clk_dummy: clock-dummy {
484 compatible = "fixed-clock";
485 #clock-cells = <0>;
486 clock-frequency = <0>;
487 clock-output-names = "clk_dummy";
490 clk_esai1_rx_clk: clock-esai1-rx {
491 compatible = "fixed-clock";
492 #clock-cells = <0>;
493 clock-frequency = <0>;
494 clock-output-names = "esai1_rx_clk";
497 clk_esai1_rx_hf_clk: clock-esai1-rx-hf {
498 compatible = "fixed-clock";
499 #clock-cells = <0>;
500 clock-frequency = <0>;
501 clock-output-names = "esai1_rx_hf_clk";
504 clk_esai1_tx_clk: clock-esai1-tx {
505 compatible = "fixed-clock";
506 #clock-cells = <0>;
507 clock-frequency = <0>;
508 clock-output-names = "esai1_tx_clk";
511 clk_esai1_tx_hf_clk: clock-esai1-tx-hf {
512 compatible = "fixed-clock";
513 #clock-cells = <0>;
514 clock-frequency = <0>;
515 clock-output-names = "esai1_tx_hf_clk";
518 clk_hdmi_rx_mclk: clock-hdmi-rx-mclk {
519 compatible = "fixed-clock";
520 #clock-cells = <0>;
521 clock-frequency = <0>;
522 clock-output-names = "hdmi-rx-mclk";
525 clk_mlb_clk: clock-mlb-clk {
526 compatible = "fixed-clock";
527 #clock-cells = <0>;
528 clock-frequency = <0>;
529 clock-output-names = "mlb_clk";
532 clk_sai5_rx_bclk: clock-sai5-rx-bclk {
533 compatible = "fixed-clock";
534 #clock-cells = <0>;
535 clock-frequency = <0>;
536 clock-output-names = "sai5_rx_bclk";
539 clk_sai5_tx_bclk: clock-sai5-tx-bclk {
540 compatible = "fixed-clock";
541 #clock-cells = <0>;
542 clock-frequency = <0>;
543 clock-output-names = "sai5_tx_bclk";
546 clk_sai6_rx_bclk: clock-sai6-rx-bclk {
547 compatible = "fixed-clock";
548 #clock-cells = <0>;
549 clock-frequency = <0>;
550 clock-output-names = "sai6_rx_bclk";
553 clk_sai6_tx_bclk: clock-sai6-tx-bclk {
554 compatible = "fixed-clock";
555 #clock-cells = <0>;
556 clock-frequency = <0>;
557 clock-output-names = "sai6_tx_bclk";
560 clk_spdif1_rx: clock-spdif1-rx {
561 compatible = "fixed-clock";
562 #clock-cells = <0>;
563 clock-frequency = <0>;
564 clock-output-names = "spdif1_rx";
567 lvds_ipg_clk: clock-controller-lvds-ipg {
568 compatible = "fixed-clock";
569 #clock-cells = <0>;
570 clock-frequency = <24000000>;
571 clock-output-names = "lvds0_ipg_clk";
574 dsi_ipg_clk: clock-controller-dsi-ipg {
575 compatible = "fixed-clock";
576 #clock-cells = <0>;
577 clock-frequency = <120000000>;
578 clock-output-names = "dsi_ipg_clk";
581 mipi_pll_div2_clk: clock-controller-mipi-div2-pll {
582 compatible = "fixed-clock";
583 #clock-cells = <0>;
584 clock-frequency = <432000000>;
585 clock-output-names = "mipi_pll_div2_clk";
589 compatible = "simple-bus";
590 #address-cells = <1>;
591 #size-cells = <1>;
595 compatible = "fsl,imx8qm-hifi4";
600 clock-names = "ipg", "ocram", "core";
601 power-domains = <&pd IMX_SC_R_MU_13B>,
608 mbox-names = "tx", "rx", "rxdb";
609 firmware-name = "imx/dsp/hifi4.bin";
615 #include "imx8-ss-cm41.dtsi"
616 #include "imx8-ss-audio.dtsi"
617 #include "imx8-ss-vpu.dtsi"
618 #include "imx8-ss-gpu0.dtsi"
619 #include "imx8-ss-mipi0.dtsi"
620 #include "imx8-ss-lvds0.dtsi"
621 #include "imx8-ss-mipi1.dtsi"
622 #include "imx8-ss-lvds1.dtsi"
623 #include "imx8-ss-img.dtsi"
624 #include "imx8-ss-dma.dtsi"
625 #include "imx8-ss-conn.dtsi"
626 #include "imx8-ss-lsio.dtsi"
627 #include "imx8-ss-hsio.dtsi"
630 #include "imx8qm-ss-img.dtsi"
631 #include "imx8qm-ss-dma.dtsi"
632 #include "imx8qm-ss-conn.dtsi"
633 #include "imx8qm-ss-lsio.dtsi"
634 #include "imx8qm-ss-audio.dtsi"
635 #include "imx8qm-ss-lvds.dtsi"
636 #include "imx8qm-ss-mipi.dtsi"
637 #include "imx8qm-ss-hsio.dtsi"
639 /delete-node/ &dsp;